SC14425XVJG

S C1 442 5 C om ple te Bas eb and pr oce sso r fo r D EC T B ase St atio ns PRELIMINARY FEBRUARY 2000 SC14425 Complete Baseband processor for DECT Base Stations with Caller-id and Handsfree General Description The SC14425SC14425 is a 3.3 Volt CMOS IC optimized to handle all the audio, signal and data processing needed within a DECT base station. An ADPCM transcoder, a very low power 14 bit Codec and Analog Frontend are integrated. Direct connections towards analog or ISDN line interface. The SC14425 has an on-chip dedicated flexible DSP optimized for telecom applications caller-id, handsfree and allows easy connection to digital telephone answering machine devices. The SC14425 is designed to be compatible with many radio interfaces. A dedicated TDMA controller handles all physical layer slot formats and radio control. The integrated National Semiconductor’s standard CR16B processor core takes care of all the higher protocol stack. Programmable I/O ports can be configured as chip selects for I/O expanders, Serial Flashes, interrupt source or I/O. A digital serial interface can be configured to interface to industry-standard c odecs and ISDN devices with µ-Law, a-Law, linear or transparent data formats. n Embedded flexible dedicated DSP executing Caller-id (CID), Caller-id on Call Waiting (CIDCW) and handsfree, two echo cancellers, two echo suppressors, extended DTMF detection, DTMF generation, sidetone and artificial echo loss. n Two full duplex 32 kbits/sec ADPCM transcoder. n On-chip Dedicated Instruction Processor (DiP) for all TDMA based events, which supports 1.152MHz, 0.576MHz and 0.288MHz data rates. n Protected and unprotected full and double slot B-fields n Standard DECT encryption with different keys for different MAC-connections. n At least 6 MAC connections can be handled simultaneously. n Flexible three wire interface to radio front synthesizer. n One 14-bit linear CODEC with programmable gain n Peak hold ADC for RSSI measurement n Two input 8 bit successive approximation ADC. n Three general purpose I/O ports with programmable interrupts n Full duplex UART, SPI T M and MICROWIRE T M interface. n Flexible 8 kHz synchronous Serial interface to external codecs and ISDN interface circuits. n Two general purpose timers and watch dog timer. n Programmable chip selects to 8 bit wide ROM, SRAM NAND Flash Memory and I/O expanders. n Two Capture timers for frequency measurement for e.g. metering, ringing and call progress tone detection. n 100 pin TQFP-100 package. Note 1: CompactRISCTM is a trademark of National Semiconductor Corporation, SPI T M is a trademark of Motorola. Features n Integrated DECT base band transceiver optimized for GAP base stations according to ETS 300 175-2,3 & 8. n 2.7 to 3.3 Volt operating voltage. n Embedded 16 bit CompactRISCT M CR16B Microprocessor with In System Emulation (ISE) mode. n On-chip 6kByte Data Memory. ________________________________________________________________________________________________ System Diagram sc14404 sc14404 ISDN or Data Interface ISDN sc14425 CID Handsfree PSTN Interface PSTN Interface sc14404 sc14404 sc14404 PSTN1 PSTN2 Copyright 2000 National Semiconductor Corp. 1 www.national.com Order Number SC14425XVJG (Standard version) X=silicon revision See NS Package Number VJG100A Note 1: All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled unless otherwise specified. PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled, A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled. Note 2: Note 3: Reset state of address and WRn, RDn pins: Hi-Z/1 means Hi-Z if RSTn is LOW, if RSTn goes HIGH is takes 32 SCLK cycles = 25 usec before these pin drives a ‘1’. 5 Volt protection pads: type *P may NOT be connected to an external pull down resistor Copyright 2000 National Semiconductor Corp. 2 I CL K COUT CIN DA C0 ADC0 HOLDACK N ADC1 SC 14 425 Co mp let e B ase ba nd pro ces sor fo r DE CT Ba se Sta tio ns 1.0 CONNECTION DIAGRAM P1 [5] AD1 8 INT5n AD4 AD5 AD6 AD7 AD12 AD15 AD16 WRn AD17 AD14 AD13 AD8 AD9 AD11 RDn AD10 RCSn VS S V DD DA B7 DA B6 DA B5 DA B4 DA B3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SCLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 VDD VSS RFCLK VDDRF DAC2 DAC Xtal1 CAP AVS AVD RSSI RDI CMPREF TDO MEN1n SO SK SC14425 DAB2 DAB 1 DAB0 AD0 AD1 AD2 AD3 P1[6] ACSn INTn6 P1[7] HOLDn MI INTn7 RSTn AVS2 AVD2 LRS2+ LRS2VREF2MIC2AGND MIC2+ VREF2+ CAP2+ CAP2N.C. N.C. N.C. N.C. U TX URX CS 0 CS 1 TONE REA DY CS 2 AD1 9 CLK 10 0 P10 _I NT I NTn 0 SCK I NTn 1 SEN I NTn 2 SDI I NTn 3 SDO I NTn 4 STR0 STR1 PWM P0 [0] P0 [1] P0 [2] P 0[3 ] P 0[4 ] P 0[5 ] P 0[6 ] P 0[7 ] P 1[0 ] P 1[1 ] P 1[2 ] P 1[3 ] P 1[4 ] P 2[0 ] P 2[1 ] P 2[2 ] VDD VS S P 2[3 ] P 2[4 ] P 2[5 ] P 2[6 ] P 2[7 ] ADC2 TP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 www.national.com SC14425 Complete Baseband processor for DECT Base Stations READY HOLDACK HOLDN F ebruary 2000, VSS1,2,3 VDD1,2,3 CLK100 ACSN RCSN WRN RDN SCLK CS0, 1, 2 .. AVS CAP XTAL1 RSTN P2. 0 PWM P0.0 P0.7 P1.0 P1.7 P2. 7 MI Watchdog Timer0 Timer1 P0 Xtal Osc VDDRF RFCLK CLOCK P1 Debounce Timer P2 PWM CR16B SBI ICU UART SPI DAB(7..0) AD(19..0) 8 bit DAC DAC DAC2 ADC0 DAC0 ADC1 ADC2 P1.0 TONE RDI CMPREF 3 Clock/Data Recovery 6 bit DAC Data RAM Boot ROM Seq RAM 8 bit DAC 8 bit ADC Capture Timer/ Counter 1,2 ECZ1,2 Bus arbiter BMC Shared Data RAM Dedicated Instruction Processor TDO Gaussian Filter peakhold ADC RSSI 0 PD7 . . PD1 PIN WIRE MICRO 2X Cyphering ADPCM Caller-id DTMF CAS FSK detect Echo Canceller, suppressor DTMF tone generator Conferencing summator Alaw/uLaw conversion Handsfree, Listen-in CODEC2 MIC2+ MIC2LRS2+ LRS2AVD2 AVS2 AG ND SO SK MEN1N CO UT CI N CAP1 CAP2+ CAP2VREF2+ VREF2- FIGURE 1. SC14425 Block diagram STR1 STR0 ICLK (3-6-98) SC 14 425 Co mp let e B ase ba nd pro ces sor fo r DE CT Ba se Sta tio ns 1.0 Package information pin 1 16.0+/- 0.15) 14.00+/- 0.10) 13.95+/-0.10 .17-.27 .5 1.4+/-0.108 13.95+/-0.10 .09-.20 SEATING PLANE 14.00+/-0.10 0.25 16.0+/-0.15 4220180 0.60+/-0.15 FIGURE 1. 100 pins TP Quad Flat Pack. NS Package Number VJG100A Copyright 2000 National Semiconductor Corp. 4 www.national.com S C1 442 5 C om ple te Bas eb and pr oce sso r fo r D EC T B ase St atio ns 2.0 Product status definitions Definition of Terms Data Sheet Identification Advance Information Product Status Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data. Supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by National Semiconductor Corporation. The datasheet is printed for reference information only. Formative or In Design Preliminary First Production No Identification Noted Full Production Obsolete Not In Production National Semiconductor B.V reserves the right to make changes without notice to any products herein to improve reliability, function or design. National does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the right of others. ________________________________________________________________________________________________ . LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: (+49) 0-180-530 85 86 europe.support@nsc.com (+49) 0-180-530 85 85 (+49) 0-180-532 78 32 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-254-4466 Fax: 65-250-4466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Copyright 2000 National Semiconductor Corp. 5 www.natiional.com