SC14428

SC14428 Baseband Processor for FP & PP DECT and WDCT ADVANCED INFORMATION March 2004 SC14428 Baseband Processor for FP & PP DECT and WDCT 1.0 General description .The SC14428 is a CMOS IC optimized to handle all the audio, signal and data processing needed within a DECT (1.9 GHz) or 2.4GHz ISM digital band base stations and handsets. A four channel ADPCM transcoder, a very low power 16 bit Codec and Analog Frontend are integrated. Direct connections towards PSTN or ISDN line interface are possible. The SC14428 has a programmable Generic DSP optimized for telecom applications. The SC14428 is designed to fit to any radio interface. A dedicated TDMA controller handles all physical layer slot formats and radio control. National Semiconductor’s standard CompactRISCTM CR16C microprocessor takes care of all the higher protocol stack. ■ Programmable 16 bits system bus interface with bus master and slave operation. ■ User programmable GENeric DSP with fixed telecom processing routines. ■ Four full duplex 32 kbits/sec ADPCM transcoder. ■ On-chip Dedicated Instruction Processor (DiP) for all TDMA based events, which supports DCT 1.152MHz, 0.576MHz and 0.288MHz data rates. ■ ISM band and DECT with 9.216, 10.368 and 13.824 MHz xtals. ■ Protected and unprotected full and double slot B-fields ■ Flexible 1.152 Mbit/sec three wire interface to radio front synthesizer. ■ One 16-bit linear CODEC ■ Selectable Fast Antenna Diversity operation or RSSI measurement with peak hold ADC. ■ Three input general purpose 8 bit ADC ■ Two general purpose timers and watch dog timer. ■ Two Capture timers for frequency measurement for e.g. metering, ringing and call progress tone detection. ■ Three general purpose I/O ports with two edge/level programmable interrupts ■ Full duplex UART and MICROWIRETM interface. ■ SPITM interface (Master/Slave). ■ Flexible 8 kHz synchronous Serial interface to external codecs and ISDN interface circuits. ■ Three programmable chip selects ■ Integrated opamp for caller-id ■ (80 pin PFQP and 80,)128,160 pins TQFP packages. 2.0 Features ■ Complies with DECT ETS 300 175-2,3 & 8 SWAP-CA V1.3 Rev 1.3 20000616 ■ 1.8Volt operating voltage with 2.65V (typ) IO pads. ■ Two chip low drop voltage regulators ■ 16 bit CompactRISCTM CR16C Microprocessor with programmable clock speeds up to 20.736 MHz. ■ Four channel DMA controller. ■ Serial Debug interface, Nexus Class-1 compliant. ■ 16kbyte shared, 6kbyte non shared RAM ■ 4kbyte shared RAM for TAM DSP ■ Versions with ROM, FLASH and data FLASH 3.0 System Diagram SC14428 SC14428 SC14428 CID HANDSFREE ISDN OR DATA INTERFACE PSTN INTERFACE PSTN INTERFACE ISDN PSTN1 PSTN2 SC14428 SC14428 SC14428 CompactRISCTM is a trademark of National Semiconductor Corporation © 2004 National Semiconductor Corporation www.national.com LMX9820 3.0 System Diagram (Continued) P2[7-0] P1[7-0] P0[7-0] 1->5 CR16C COMPACTRISC 16 BIT MICRO CONTROLLER XTAL TRIMMING FLASH/ PLL 16 BITS SCLK CLOCK DIVIDER BOOT ROM ROM PWM ACCESS BUS1 UART IRDA SDI+ SPI DMA SYSTEM BUS INTERFACE 16 BITS ACCESS BUS2 6KBYTE DATA RAM 8 KBYTE DATA FLASH ICU TIMERS 8 BIT ADC TEMPERATURE SENSOR SCALER 16KBYTE SHARED RAM 1 KBYTE MICRO CODE RAM DC/DC CONVERTOR BATTERY & CHARGE CONTROL DEDICATED INSTRUCTION PROCESSOR 2X VOLTAGE REGULATOR ENCRYP CODEC GENDSP ADPCM TION BMC RF CONTROL PINS MICRO WIRE 3 BITS AFE PCM IF FIR FILTER 8 BIT DAC GAUSSIAN SHAPER CLOCK RECOVERY P3[7-1] MUX PSTN IF 30W ISDN, CODEC RF INTERFACE HEADSET Figure 1. SC14428 Block diagram www.national.com 2 (Confidential) Revision 1.0 SC14428 4.0 Specifications All min/max specification limits are guaranteed by design, or production test, or statistical methods. Table 1. ABSOLUTE MAXIMUM RATINGS1 Parameter Vbat1_max Vbat2_max Ibat1_max Ibat2_max Ivddiotot_max Ivddio_max Vdd_max Vddiof_max Vddio_max Vldo1_ctrl_max Vldo2_ctrl_max Vpon_max Vcharge_max Vbat3_max Vadc1_max Vrdidig_max Vrdiana_max Vdig_max Vana_max Iprot_max Iprotcid_max Iprotmic_max Iprotpon_max Iprotcharge_max Iprotvbat3_max Iprotadc1_max Tstorage Ppackage Ilu Ilu_rdi_25 Ilu_rdi_60 Vesd_mm Vesd_hbm Description Max Battery supply voltage VBAT1 Max Battery supply voltage VBAT2 Max negative current into VBAT1 Max negative current into VBAT2 Max total current into VDDIOs Max current through I/O pins Max Core supply voltage (VDD-VSS / AVD-AVS / AVD2-AVS / VDDRF-VSSRF) Max I/O Supply voltage for devices with FLASH (VDDIO-VSS) Max I/O supply voltage for devices without FLASH (VDDIO-VSS) Max voltage on pin LDO1_CTRL Max voltage on pin LDO2_CTRL Max voltage on pin PON Max voltage on pin CHARGE Max voltage on pin VBAT3 Max voltage on pin ADC1 Max voltage on pin RDI digital mode (max 3.6V) Max voltage on pin RDI analog mode Max voltage on digital Input pins (max 3.6V) Max voltage on any other input (incl analog pads) Max current through prot. diodes on any pin to VDDIO Max current through prot. diode pins CID+/- to AGND Current through prot. diode pin MIC+/- to AGND Max current through prot. circuit of PON pin. Max current through prot. circuit of CHARGE pin. Max current through prot. circuit of VBAT3 pin. Max current through prot. circuit of ADC1 pin. Storage temperature Package power dissipation @ 25 °C Latch-up current all pins according JEDEC 78 Latch-up current RDI pin Latch-up current RDI pin ESD voltage according to man machine model ESD voltage according to human body model Conditions Min Max 5.5 5.5 300 300 90 20 2.0 Units V V mA mA mA mA V V V V V V V V V V V V V mA mA mA mA mA mA mA °C mW mA mA mA V V Note2 Note3 Note4 Note4 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 3.0 3.6 5.25 5.25 2.85 2.85 2.85 2.85 VDDIO+0.3 2.0 VDDIO+0.3 2.0 100 1.0 2.4 Note5 Note5 Note5 -65 TA = 65 °C TA = 25 °C TA = 65 °C 0.6 0.6 0.6 0.6 +150 500 100 100 50 100 1000 1.Absolute maximum ratings are those values that may be applied for maximum 50 hours. Beyond these values, damage to the device may occur. 2.A voltage between 2.8V and 3.0V may applied for a maximum time of 1 hour in order to guarantee the device specifications. 3.A voltage between 3.3V and 3.6V may applied for a maximum time of 50 hours in order to guarantee the device specifications. 4.For LDO1_CTRL, LDO2_CTRL, with 5V input protection, VDD must be between 1.75V and 2.0V or Vbat 1 >2.0V or Vbat2>2.8V. Revision 1.0 (Confidential) 3 LMX9820 4.0 Specifications (Continued) 5.The protection current can be calculated as follows: In case P1[6]/PON, P1[7]/CHARGE, VBAT3, P2[3]/ADC1 is input, Iprotxxx_max = (Vext 2.55)/(500+Rext) Rext is an external resistor which is needed if the external voltage Vext exceeds the 2.8V. (A lower protection current value of e.g. 100 uA is recommended in case power saving is important) In case P1[6]/PON, P1[7]/CHARGE , P2[3]/ADC1 is output, Iprotxxx_max = (VDDIO - 2.55)/(500) Table 2. OPERATING CONDITIONS 1 PARAMETER Vbat1 Vbat2 Vdd Avd Avd2 Vddrf Vddiof Vddio Vdcs Vpon Vcharge Vbat3 Vadc1 Vprot_mic Iprotpon Iprotcharge Iprotvbat3 Iprotadc1 DESCRIPTION Battery supply voltage VBAT1-AVS Battery supply voltage VBAT2-AVS Digital core supply voltage VDD-VSS Analog core supply voltage AVD-AVS Analog core supply voltage AVD2-AVS Analog xtal and RFCLK supply voltage VDDRF-VSSRF Digital I/O supply voltage VDDIO-VSS for devices with FLASH Digital I/O supply voltage VDDIO-VSS for devices without FLASH Voltage on DC_Sense pin Voltage on PON Voltage on CHARGE Voltage on VBAT3 Voltage on ADC1 Voltage on pins MICn, CIDp/n if protection enabled Current through protection circuit of PON pin. Current through protection circuit of CHARGE pin. Current through protection circuit of VBAT3/RINGING pin. Current through protection circuit of ADC1 pin. Voltage on LDO1_CTRL Maximum voltage on LDO2_CTRL PLL operating range Ambient temperature Note5 28 -10 All states 3 All states 3 Note3 Note3 Note4 Note3 Note3 Note3 Note3 0.4 Note2 Note2 Note2 Note2 CONDITIONS MIN 2.0 2.8 1.75 1.75 1.75 1.75 2.5 1.75 1.8 1.8 1.8 1.8 2.65 TYP MAX 5.0 5.0 1.98 1.98 1.98 1.98 2.8 3.3 2.0 2.8 2.8 2.8 2.8 1.4 0.5 0.5 0.5 0.5 UNITS V V V V V V V V V V V V V V mA mA mA mA Vldo1_ctrl Vldo2_ctrl Fpll_range TA 5.0 5.0 48 60 V V MHz °C 1.Within the specified limits, a life time of 10 years is guaranteed. 2.Full operating mode; the differences between AVD, VDD may never be more than 300mV; during a short period of time e.g. during power up more than 300mV difference is allowed. Analog performance is only guaranteed from 1.75-1.98V www.national.com 4 (Confidential) Revision 1.0 SC14428 3.The protection current can be calculated as follows: In case P1[6]/PON, P1[7]/CHARGE, VBAT3, P2[3]/ADC1 is input, Iprotxxx_max = (Vext - 2.55)/(500+Rext) Rext is an external resistor which is needed if the external voltage Vext exceeds the 2.8V. (A lower protection current value of e.g. 100 uA is recommended in case power saving is important) In case P1[6]/PON, P1[7]/CHARGE , P2[3]/ADC1 is output, Iprotxxx_max = (VDDIO - 2.55)/(500) 4.For pads with the protection circuit enabled, the protection current must be limited with external source resistor Rext if the input voltage exceeds 0.4V resp 1.4V. Rext can be calculated as follows: Rext >(Vext-1.4)/Iprotxxx). 5.Within this temperature range full operation is guaranteed.Upto +70 degrees Celsius analog performance is not guaranteed. 5.0 Product Status Definitions Datasheet Status Advance Information Product Status Formative or in Design Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data. Supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by National Semiconductor Corporation. The datasheet is printed for reference information only. Preliminary First Production No Identification Noted Full production Obsolete Not in Production 6.0 National Semiconductor B.V reserves the right to make changes without notice to any products herein to improve reliability, function or design. National does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the right of others. Revision 1.0 (Confidential) 5 SC14428 Baseband Processor for FP & PP DECT and WDCT 7.0 Package information inches (millimeters) unless otherwise noted Figure 2. 80 Pins PQFP. NS Package number: VJE80A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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