SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
May 2006
SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
General Description
The SCAN15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on National’s 10-, 16-, and 18- bit Bus LVDS SerDes, or to CML or LVPECL signals. Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and highspeed differential PCB interconnects. The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85˚C temperature range.
Features
n 1.5 Gbps data rate per channel n Configurable off/on pre-emphasis drives lossy backplanes and cables n LVDS/BLVDS/CML/LVPECL compatible inputs, LVDS compatible outputs n Low output skew and jitter n On-chip 100Ω input and output termination n IEEE 1149.1 and 1149.6 compliant n 15 kV ESD protection on LVDS inputs/outputs n Hot plug Protection n Single 3.3V supply n Industrial -40 to +85˚C temperature range n 48-pin LLP Package
Typical Application
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Block Diagram
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FIGURE 1. SCAN15MB200 Block Diagram
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DS201328
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SCAN15MB200
Pin Descriptions
Pin Name SIA_0+ SIA_0− SIA_1+ SIA_1− SIB_0+ SIB_0− SIB_1+ SIB_1− LI_0+ LI_0− LI_1+ LI_1− SOA_0+ SOA_0− SOA_1+ SOA_1− SOB_0+ SOB_0− SOB_1+ SOB_1− LO_0+ LO_0− LO_1+ LO_1− MUX_S0 MUX_S1 PREA_0 PREA_1 PREB_0 PREB_1 PREL_0 PREL_1 ENA_0 ENA_1 ENB_0 ENB_1 ENL_0 ENL_1 TDI TDO TMS TCK TRST POWER LLP Pin Number 30 29 19 20 28 27 21 22 40 39 9 10 34 33 15 16 32 31 17 18 42 41 7 8 38 11 26 23 25 24 44 5 36 13 35 14 45 4 2 1 46 47 3 I/O, Type Description
SWITCH SIDE DIFFERENTIAL INPUTS I, LVDS I, LVDS I, LVDS I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS I, LVDS I, LVDS
SWITCH SIDE DIFFERENTIAL OUTPUTS O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1, 3). I, LVTTL I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through to the Line-side. Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and B-side has a separate pin to control the pre-emphasis on or off.
LINE SIDE DIFFERENTIAL OUTPUTS
DIGITAL CONTROL INTERFACE
I, LVTTL I, LVTTL
Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side has a separate pin to control the pre-emphasis on or off. Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and B-side has a separate enable pin.
I, LVTTL I, LVTTL I, LVTTL I, LVTTL I, LVTTL
Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate enable pin. Test Data Input to support IEEE 1149.1 features Test Mode Select to support IEEE 1149.1 features Test Clock to support IEEE 1149.1 features Test Reset to support IEEE 1149.1 features
O, LVTTL Test Data Output to support IEEE 1149.1 features
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SCAN15MB200
Pin Descriptions
Pin Name VDD GND LLP Pin Number 6, 12, 37, 43, 48 (Note 2)
(Continued) Description VDD = 3.3V ± 0.3V. Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance.
I/O, Type I, Power I, Power
Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned). Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package. Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device have been optimized for point-to-point backplane and cable applications.
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SCAN15MB200
Connection Diagrams
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LLP Top View DAP = GND
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Directional Signal Paths Top View (Refer to pin names for signal polarity)
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SCAN15MB200
Output Characteristics
The output characteristics of the SCAN15MB200 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. A 100Ω output (source) termination resistor is incorporated in the device to eliminate the need for an external resistor, providing excellent drive characteristics by locating the source termination as close to the output as physically possible.
Multiplexer Truth Table
Data Inputs SIA_0 X valid X SIB_0 valid X X MUX_S0 0 1 X
(Note 5) Output LO_0 SIB_0 SIA_0 Z
Control Inputs ENL_0 1 1 0 (Note 6)
X = Don’t Care Z = High Impedance (TRI-STATE)
Pre-Emphasis Controls
The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or on per the Pre-emphasis Control Table. PREx_n (Note 4) 0 1 Output Pre-emphasis 0% 100%
Repeater/Buffer Truth Table
Data Input LI_0 X valid valid valid Control Inputs ENA_0 0 0 1 1 ENB_0 0 1 0 1
(Note 5)
Outputs SOA_0 Z LI_0 LI_0 SOB_0 LI_0 Z LI_0 Z (Note 6) Z (Note 6)
X = Don’t Care Z = High Impedance (TRI-STATE) Note 5: Same functionality for channel 1 Note 6: When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the applications section titled TRI-STATE and Powerdown modes.
Note 4: Applies to PREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1
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SCAN15MB200
Absolute Maximum Ratings (Note 7)
Supply Voltage (VDD) CMOS Input Voltage LVDS Receiver Input Voltage (Note 8) LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Solder, 4sec) Max Pkg Power Capacity @ 25˚C Thermal Resistance (θJA) Package Derating above +25˚C ESD Last Passing Voltage HBM, 1.5kΩ, 100pF LVDS pins to GND only −0.3V to +4.0V -0.3V to (VDD+0.3V) -0.3V to (VDD+0.3V) -0.3V to (VDD+0.3V) +40 mA +150˚C −65˚C to +150˚C 260˚C 5.2W 24˚C/W 41.7mW/˚C 8kV 15kV
EIAJ, 0Ω, 200pF CDM
250V 1000V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) (Note 8) Output Voltage (VO) Operating Temperature (TA) Industrial −40˚C to +85˚C 3.0V to 3.6V 0V to VCC 0V to VCC
Note 7: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions. Note 8: VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 9) Max Units
LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n, TDI, TDO, TCK, TMS, TRST) VIH VIL IIH IIHR IIL IILR CIN1 COUT1 VCL VOH VOL IOS IOZ VTH VTL VID VCMR CIN2 IIN High Level Input Voltage Low Level Input Voltage High Level Input Current High Level Output Current Low Level Input Current Low Level Input Current Input Capacitance Output Capacitance Input Clamp Voltage High Level Output Voltage (TDO) Low Level Output Voltage (TDO) Output Short Circuit Current Output TRI-STATE Current Differential Input High Threshold (Note 10) Differential Input Low Threshold (Note 10) Differential Input Voltage Common Mode Voltage Range Input Capacitance Input Current VIN = VDD = VDDMAX PREA_n, PREB_n, PREL_n VIN = VSS, VDD = VDDMAX TDI, TMS, TRST Any Digital Input Pin to VSS Any Digital Output Pin to VSS ICL = −18 mA IOH = −12 mA, VDD = 3.0 V IOH = −100 µA, VDD = 3.0 V IOL = 12 mA, VDD = 3.0 V IOL = 100 µA, VDD = 3.0 V TDO TDO VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VCM = 0.8V to 3.55V, VDD = 3.6V VID = 150 mV, VDD = 3.6V IN+ or IN− to VSS VIN = 3.6V, VDD = VDDMAX or 0V VIN = 0V, VDD = VDDMAX or 0V −15 −15 −100 100 0.05 2.0 +15 +15 -15 -10 −1.5 2.4 VDD-0.2 0.5 0.2 -125 +10 2.0 GND −10 40 −10 -40 2.0 4.0 −0.8 VDD 0.8 +10 200 +10 -200 V V µA µA µA µA pF pF V V V V V mA µA
LVDS INPUT DC SPECIFICATIONS (SIA ± , SIB ± , LI ± ) 0 0 2400 3.55 100 mV mV mV V pF µA µA
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SCAN15MB200
Electrical Characteristics
Symbol Parameter
(Continued) Over recommended operating supply and temperature ranges unless other specified. Conditions Min Typ (Note 9) Max Units
LVDS OUTPUT DC SPECIFICATIONS (SOA_n ± , SOB_n ± , LO_n ± ) VOD ∆VOD VOS ∆VOS IOS COUT2 Differential Output Voltage, 0% Pre-emphasis (Note 10) Change in VOD between Complementary States Offset Voltage (Note 11) Change in VOS between Complementary States Output Short Circuit Current Output Capacitance OUT+ or OUT− Short to GND OUT+ or OUT− to GND when TRI-STATE All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. ENA_0 = ENB_0 = ENL_0= ENA_1 = ENB_1 = ENL_1 = L RL is the internal 100Ω between OUT+ and OUT− 250 -35 1.05 -35 −21 4.0 1.22 360 500 35 1.475 35 -40 mV mV V mV mA pF
SUPPLY CURRENT (Static) ICC Supply Current 225 275 mA
ICCZ
Supply Current - Powerdown Mode
0.6
4.0
mA
SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT tHLT tPLHD tPHLD tSKD1 tSKCC Differential Low to High Transition Use an alternating 1 and 0 pattern at Time 200 Mb/s, measure between 20% and Differential High to Low Transition 80% of VOD. (Note 16) Time Differential Low to High Propagation Delay Differential High to Low Propagation Delay Pulse Skew Output Channel to Channel Skew Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. |tPLHD–tPHLD| (Note 16) Difference in propagation delay (tPLHD or tPHLD) among all output channels. (Note 16) RJ - Alternating 1 and 0 at 750MHz (Note 13) DJ - K28.5 Pattern, 1.5 Gbps (Note 14) TJ - PRBS 27-1 Pattern, 1.5 Gbps (Note 15) tON LVDS Output Enable Time Time from ENA_n, ENB_n, or ENL_n to OUT ± change from TRI-STATE to active. Time from ENA_n, ENB_n, or ENL_n to OUT ± change from Powerdown to active Time from ENA_n, ENB_n, or ENL_n to OUT ± change from active to TRI-STATE or powerdown. 170 170 1.0 1.0 25 50 1.1 20 14 250 250 2.5 2.5 75 115 1.5 34 28 ps ps ns ns ps ps psrms psp-p psp-p
tJIT
Jitter (0% Pre-emphasis) (Note 12)
0.5
1.5
µs
tON2
LVDS Output Enable time from powerdown mode LVDS Output Disable Time
10
20
µs
tOFF
12
ns
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SCAN15MB200
Electrical Characteristics
Symbol Parameter
(Continued) Over recommended operating supply and temperature ranges unless other specified. Conditions Min Typ (Note 9) Max Units
SWITCHING CHARACTERISTICS - SCAN FEATURES fMAX tS tH tS tH tW tW tREC Maximum TCK Clock Frequency TDI to TCK, H or L TDI to TCK, H or L TMS to TCK, H or L TMS to TCK, H or L TCK Pulse Width, H or L TRST Pulse Width, L Recovery Time, TRST to TCK RL = 500Ω, CL = 35 pF 25.0 3.0 0.5 3.0 0.5 10.0 2.5 2.0 MHz ns ns ns ns ns ns ns
Note 9: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 10: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 11: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 12: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 13: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Note 14: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 15: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, 27-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). Note 16: Not Production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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SCAN15MB200
Typical Performance Characteristics
Power Supply Current vs. Bit Data Rate Total Jitter vs. Bit Data Rate
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Dynamic power supply current was measured with all channels active and toggling at the bit data rate. Data pattern has no effect on the power consumption. VDD = 3.3V, TA = +25˚C, VID = 0.5V, VCM = 1.2V
Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with one channel active, all other channels are disabled. VDD = 3.3V, TA = +25˚C, VID = 0.5V, pre-emphasis off.
Total Jitter vs. Temperature
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Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with one channel active, all other channels are disabled. VDD = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, pre-emphasis off.
FIGURE 2. LLP Performance Characteristics
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SCAN15MB200
TRI-STATE and Powerdown Modes
The SCAN15MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows each output individually to be placed in a low power TRISTATE mode while the device remains active, and is useful to reduce power consumption on unused channels. In TRISTATE mode, some outputs may remain active while some are in TRI-STATE. When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators. When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the outputs because of the ramp to power up the internal bandgap reference generators. Any single output enable that remains active will hold the device in active mode even if the other five outputs are in TRI-STATE. When in Powerdown mode, any output enable that becomes active will wake up the device back into active mode, even if the other five outputs are in TRI-STATE.
voltage will be at the normal LVPECL levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage, VCM, range. Most National Semiconductor LVDS receivers have wide VCM range. The exceptions are noted in devices’ respective datasheets. Those LVDS devices that do have a wide VCM range do not vary in performance significantly when receiving a signal with a common mode other than standard LVDS VCM of 1.2 V.
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FIGURE 4. AC Coupled LVPECL to LVDS Interface An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 4 illustrates an AC coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device (Note 17), provide DC load for the emitter followers and may range between 140-220Ω for most LVPECL devices for this particular configuration. The 15MB200 includes an internal 100Ω resistor to terminate the transmission line for minimal reflections. The signal after ac coupling capacitors will swing around a level set by internal biasing resistors (i.e. fail-safe) which is either VDD/2 or 0 V depending on the actual failsafe implementation. If internal biasing is not implemented, the signal common mode voltage will slowly drift to GND level.
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. Please refer to application note AN1194, “Failsafe Biasing of LVDS Interfaces” for more information.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source. This drives a pair of emitter-followers that require a 50Ω to VCC-2.0 load. A modern LVPECL driver will typically include the termination scheme within the device for the emitter follower. If the driver does not include the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB, therefore, a load scheme without a unique power supply requirement may be used.
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FIGURE 3. DC Coupled LVPECL to LVDS Interface Figure 3 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for the driver emitter followers, and may be included as part of the driver device (Note 17). The 15MB200 includes a 100Ω input termination for the transmission line. The common mode
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SCAN15MB200
Interfacing LVDS to LVPECL
An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a differential resistive load in the range of 70 to 130Ω to generate LVDS levels. In a system, the load should be selected to match transmission line characteristic differential impedance so that the line is properly terminated. The termination resistor should be placed as close to the receiver inputs as possible. When interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within the common mode range of the receiver. This may be done by using separate biasing voltage which demands another power supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB).
Design-For-Test (DfT) Features
IEEE 1149.1 SUPPORT The SCAN15MB200 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are included in the same boundary scan chain but instead contain IEEE1149.6 cells. IEEE1149.6 is the improved IEEE standard for testing high-speed differential signals. Refer to the BSDL file located on National’s website for the details of the SCAN15MB200 IEEE 1149.1 implementation. IEEE 1149.6 SUPPORT AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-coupled), single ended networks. IEEE 1149.6 is specifically designed for testing high-speed differential, including AC coupled networks. The SCAN15MB200 is intended for high-speed signalling up to 1.5 Gbps and includes IEEE1149.6 on all differential inputs and outputs.
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FIGURE 5. DC Coupled LVDS to LVPECL Interface Figure 5 illustrates interface between an LVDS driver and a LVPECL with a VT pin available. R1 and R2, if not present in the receiver (Note 17), provide proper resistive load for the driver and termination for the transmission line, and VT sets desired bias for the receiver.
FAULT INSERTION Fault Insertion is a technique used to assist in the verification and debug of diagnostic software. During system testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect and diagnose these faults. In the SCAN15MB200 an IEEE1149.1 "stuckat" instruction can create a stuck-at condition, either high or low, on any pin or combination of pins. A more detailed description of the stuck-at feature can be found in NSC Applications note AN-1313.
Packaging Information
The Leadless Leadframe Package (LLP) is a leadframe based chip scale package (CSP) that may enhance chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The small size and very low profile make this package ideal for high density PCBs used in small-scale electronic applications such as cellular phones, pagers, and handheld PDAs. The LLP package is offered in the no Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the edge of the package. This feature offers a visible solder fillet after board mounting. The LLP has the following advantages: • Low thermal resistance • Reduced electrical parasitics
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FIGURE 6. AC Coupled LVDS to LVPECL Interface Figure 6 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VT pin available. The resistors R1, R2, R3, and R4, if not present in the receiver (Note 17), provide a load for the driver, terminate the transmission line, and bias the signal for the receiver.
Note 17: The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and common mode operating ranges.
• Improved board space efficiency • Reduced package height • Reduced package mass For more details about LLP packaging technology, refer to applications note AN-1187, "Leadless Leadframe Package"
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SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Pin LLP NS Package Number SQA48a Ordering Code SCAN15MB200TSQ (250 piece Tape and Reel) SCAN15MB200TSQX (2500 piece Tape and Reel)
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