SCAN50C400AUT

SCAN50C400A 1.25/2.5/5.0 Gbps Quad Multi-rate Backplane Transceiver OBSOLETE February 2007 SCAN50C400A 1.25/2.5/5.0 Gbps Quad Multi-Rate Backplane Transceiver General Description The SCAN50C400A is a four-channel high-speed backplane transceiver (SERDES) designed to support multiple line data rates at 1.25, 2.5 or 5.0 Gbps over a printed circuit board backplane. It provides a data link of up to 20 Gbps total through-put in each direction. Each transmit section of the SCAN50C400A takes a 4-bit differential LVDS source synchronous data bus, serializing it to a differential high-speed serial bit stream and output from a CML driver. The receive section of the SCAN50C400A consists of a differential input stage, a clock/data recovery PLL, a serial-to-parallel converter, and a LVDS output bus. Deemphasis at the high-speed driver outputs and a limiting amplifier circuit at the receiver inputs are used to reduce ISI distortions to enable error-free data transmission over more than 26 inches point-to-point link with a low cost FR4 backplane. Internal low jitter PLLs are used to derive the high-speed serial clock from a differential reference clock source. Two channels share common transmit and receive LVDS clocks. The SCAN50C400A has built-in self-test (BIST) circuitry and also loopback test modes to support at-speed self-testing. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Quad Backplane SERDES transceiver Multiple data rates at 1.25, 2.5 or 5 Gbps 40 Gbps total full duplex throughput Better than 10−15 bit error rate Test Modes: On-chip at-speed BIST circuitry, Loopbacks On-chip LVDS and CML terminations High-speed CML driver with optional signal conditioning 4-bit differential source synchronous LVDS parallel I/O Low-jitter PLL reference to external differential HSTL clock at 125 MHz Designed for use with low cost FR4 backplane TIA/EIA 644-A compatible LVDS IO IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible IEEE 1149.1 (JTAG) compliant test mode 1.35V for core, high-speed circuitry and MDIO 3.3V ±5% for LVDS IO, Control and JTAG interface Low power, 4.5W (TYP) 23 mm x 23 mm thermally enhanced BGA package Typical Application 20046101 © 2007 National Semiconductor Corporation 200461 www.national.com SCAN50C400A Equivalent Functional Diagram 20046102 Ordering Information NSID / Marking (logo) # SCAN50C400AUT Lot#, Wafer# Data Rate Support 1.25/2.5/5.0 Gbps Operation www.national.com 2 Connection Diagram SCAN50C400A 3 20046103 TOP VIEW Order Number SCAN50C400AUT See NS Package Number UFJ440A www.national.com SCAN50C400A Pin Descriptions Pin Name Ball Number L22 L21 J22 J21 G22 G21 E22 E21 N22 N21 R22 R21 U22 U21 W22 W21 I/O, Type Description HIGH-SPEED DIFFERENTIAL I/O HT1+ HT1− HT2+ HT2− HT3+ HT3− HT4+ HT4− HR1+ HR1− HR2+ HR2− HR3+ HR3− HR4+ HR4− O, CML Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 1. Data is sourced from T1_1±, T1_2±, T1_3± and T1_4±. On-chip 50Ω termination resistors connect from HT1+ and HT1− to VDDHS. Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 2. Data is sourced from T1_5±, T1_6±, T1_7± and T1_8±. On-chip 50Ω termination resistors connect from HT2+ and HT2− to VDDHS. Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 3. Data is sourced from T2_1±, T2_2±, T2_3± and T2_4±. On-chip 50Ω termination resistors connect from HT3+ and HT3− to VDDHS. Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 4. Data is sourced from T2_5±, T2_6±, T2_7± and T2_8±. On-chip 50Ω termination resistors connect from HT4+ and HT4− to VDDHS. Inverting and non-inverting high-speed differential inputs of the deserializer, channel 1. Data is de-serialized and output at R1_1±, R1_2±, R1_3± and R1_4±. On-chip 50Ω termination resistors connect from HR1+ and HR1− to an internal bias. Inverting and non-inverting high-speed differential inputs of the deserializer, channel 2. Data is de-serialized and output at R1_5±, R1_6±, R1_7± and R1_8±. On-chip 50Ω termination resistors connect from HR2+ and HR2− to an internal bias. Inverting and non-inverting high-speed differential inputs of the deserializer, channel 3. Data is de-serialized and output at R2_1±, R2_2±, R2_3± and R2_4±. On-chip 50Ω termination resistors connect from HR3+ and HR3− to an internal bias. Inverting and non-inverting high-speed differential inputs of the deserializer, channel 4. Data is de-serialized and output at R2_5±, R2_6±, R2_7± and R2_8±. On-chip 50Ω termination resistors connect from HR4+ and HR4− to an internal bias. Inverting and non-inverting differential reference clock to the PLL for generating internal highspeed clocks. A low jitter 125 MHz ±100 ppm clock should be connected to SCLK±. All four serializers and deserializers are frequency-locked to SCLK±. A 50 Ω termination to Ground is present on each input pin. Differential transmit input data for channel 1. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T1[1–4]± are synchronous to clock T1_CLK±. Data at T1[1–4]± are serialized and output at HT1±. T1_1 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T1_CLK±. O, CML O, CML O, CML I, CML I, CML I, CML I, CML REFERENCE CLOCK SCLK+ SCLK− A16 B16 I, HSTL TRANSMIT INPUT DATA T1_1+ T1_1− T1_2+ T1_2− T1_3+ T1_3− T1_4+ T1_4− T1_5+ T1_5− T1_6+ T1_6− T1_7+ T1_7− T1_8+ T1_8− T1_CLK+ T1_CLK− K3 K4 J3 J4 H1 H2 G1 G2 F3 F4 E3 E4 D1 D2 C1 C2 K1 K2 I, LVDS I, LVDS Differential transmit input data for channel 2. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T1[5–8]± are synchronous to clock T1_CLK±. Data at T1[5–8]± are serialized and output at HT2±. T1_5 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T1_CLK±. I, LVDS Differential 625 MHz transmit nibble clock for channels 1 and 2. Data at T1[1–4]± and T1[5–8] ± are strobed-in at both rising and falling edges of T1_CLK±, forming an 8-bit input data bus at 1.25 Gbps. T1_CLK± should be frequency-locked to reference clock SCLK±. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. www.national.com 4 SCAN50C400A Pin Name T2_1+ T2_1− T2_2+ T2_2− T2_3+ T2_3− T2_4+ T2_4− T2_5+ T2_5− T2_6+ T2_6− T2_7+ T2_7− T2_8+ T2_8− T2_CLK+ T2_CLK− Ball Number A7 B7 C8 D8 A9 B9 A10 B10 C11 D11 C12 D12 A13 B13 A14 B14 C6 D6 I/O, Type I, LVDS Description Differential transmit input data for channel 3. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T2[1–4]± are synchronous to clock T2_CLK±. Data at T2[1–4]± are serialized and output at HT3±. T2_1 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T2_CLK±. I, LVDS Differential transmit input data for channel 4. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T2[5–8]± are synchronous to clock T2_CLK±. Data at T2[5–8]± are serialized and output at HT4±. T2_5 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T2_CLK±. I, LVDS Differential 625 MHz transmit nibble clock for channels 3 and 4. Data at T2[1–4]± and T2[5–8] ± are strobed-in at both rising and falling edges of T2_CLK±, forming an 8-bit input data bus at 1.25 Gbps. T2_CLK± should be frequency-locked to reference clock SCLK±. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. Channel 1 deserialized recovered data. Data at HR1± is de-serialized and output at R1[1–4]±, clocked by both rising and falling edges of R1_CLK±. RECEIVE OUTPUT DATA R1_1+ R1_1− R1_2+ R1_2− R1_3+ R1_3− R1_4+ R1_4− R1_5+ R1_5− R1_6+ R1_6− R1_7+ R1_7− R1_8+ R1_8− R1_CLK+ R1_CLK− R2_1+ R2_1− R2_2+ R2_2− R2_3+ R2_3− R2_4+ R2_4− N3 N4 P3 P4 R1 R2 T1 T2 U3 U4 V3 V4 W1 W2 Y1 Y2 N1 N2 AB7 AA7 Y8 W8 AB9 AA9 AB10 AA10 O, LVDS O, LVDS Channel 2 deserialized recovered data. Data at HR2± is de-serialized and output at R1[5–8]±, clocked by both rising and falling edges of R1_CLK±. O, LVDS Differential recovered nibble clock for channel 1 and 2. R1_CLK± is a 625 MHz clock sourced from the clock recovery PLL. R1_CLK±, together with R1[1–4]± and R1[5–8]±, form a source synchronous 8-bit output data bus at 1.25 Gbps. Channel 3 deserialized recovered data. Data at HR3± is de-serialized and output at R2[1–4]±, clocked by both rising and falling edges of R2_CLK±. O, LVDS 5 www.national.com SCAN50C400A Pin Name R2_5+ R2_5− R2_6+ R2_6− R2_7+ R2_7− R2_8+ R2_8− R2_CLK+ R2_CLK− Ball Number Y11 W11 Y12 W12 AB13 AA13 AB14 AA14 Y6 W6 I/O, Type O, LVDS Description Channel 4 deserialized recovered data. Data at HR4± is de-serialized and output at R2[5–8]±, clocked by both rising and falling edges of R2_CLK±. O, LVDS Differential recovered nibble clock for channel 3 and 4. R2_CLK± is a 625 MHz clock sourced from the clock recovery PLL. R2_CLK±, together with R2[1–4]± and R2[5–8]±, form a source synchronous 8-bit output data bus at 1.25 Gbps. Synchronous clock to the management serial data input/output interface. The clock rate can be 0 MHz–2.5 MHz. MDC can be asynchronous to transmit or receive clocks (SCLK±, T1_CLK ±, T2_CLK±, R1_CLK±, R2_CLK±). This pin includes an internal 30kΩ pull-up to the 1.35V rail. Bi-directional management data line where control data is transferred between station management and SCAN50C400A transceiver. This pin includes an internal 30 kΩ pull-up resistor to the 1.35V rail. An external pull-up resistor is typically connected from MDIO to the 1.35V rail. PHYAD0–4 define the 5-bit PHY address to the SCAN50C400A transceiver. PHYAD4 is the MSB. These pins include an internal 30kΩ pull-up to the 1.35V rail. SERIAL INTERFACE — 1.35V Levels (1.5V Tolerant) MDC AA3 I, LVCMOS MDIO AA4 IO, LVCMOS PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 RESETB LSLB AB6 AB3 AB4 AB5 AA5 Y4 A5 I, LVCMOS CONTROL INTERFACE — 3.3V Levels I,LVCMOS I, LVCMOS A logic low at RESETB initiates hardware reset function. RESETB must be low for more than 1ms with SCLK running. This pin includes an internal pull-up. A logic low at LSLB enables LVDS loopback test mode for all four channels. The serialized bit stream is internally connected to the high-speed serial input of each channel's deserializer. It forms a diagnosis data path from the LVDS parallel transmit inputs (T1[1-8]±, T2[1-8]±), through the SCAN50C400A, and back to the LVDS parallel LVDS outputs (R1[1-8]±, R2[1-8]±). The data inputs at HR± are ignored, but the input terminations at HR+ and HR− remain active. During normal operation, LSLB should be tied high. See Figure 6. This pin includes an internal pull-up. LSLB HSLB 1 1 Normal SERDES mode. 1 0 High-Speed Loopback enabled. 0 1 LVDS Loopback enabled. 0 0 Not recommended. SCAN50C400A defaulted to LVDS loopback. A logic low at HSLB enables High-speed loopback test mode for all four channels. The deserialized data at the LVDS side are internally connected to the transmit input data of each channel's serializer. It forms a diagnosis data path from the high-speed serial inputs (HR±), through the SCAN50C400A, and back to the high-speed serial outputs (HT±). The data inputs at T1[1-8]± and T2[1-8]± are ignored, but the on-chip differential terminations remain active. During normal operation, HSLB should be tied high. See Figure 7 and truth table in LSLB description. This pin includes an internal pull-up. MODE0–1 selects the line data rate. These pins include internal pull-ups. MODE1 MODE0 0 0 Serializer outputs at 5 Gbps, Deserializer inputs at 5 Gbps. 1 0 Serializer outputs at 2.5 Gbps, Deserializer inputs at 2.5 Gbps. 0 1 Serializer outputs at 1.25 Gbps, Deserializer inputs at 1.25 Gbps. 1 1 Serializer outputs at 5 Gbps, Deserializer inputs at 5 Gbps. HSLB B5 I, LVCMOS MODE0 MODE1 AA6 B6 I, LVCMOS www.national.com 6 SCAN50C400A Pin Name PDNB Ball Number Y5 I/O, Type I, LVCMOS Description A logic low at PDNB activates the hardware power down mode. In power down mode, the MDIO Management interface is not functioning. This pin includes an internal pull-down (default is OFF). Test Reset Input per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. Test Reset is active low. Test Mode Select per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. Test Data Input per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. Test Clock Input per IEEE 1149.1. There is an internal weak pull-down on this pin. Test Data Output per IEEE 1149.1. Default is TRI-STATE. Reserved for testing purposes. Do not connect. SCAN INTERFACE — 3.3V Levels TRSTB TMS TDI TCK TDO RES0 RES1 RES2 RES3 RES4 RES5 POWER VDDIO VDDHS GND VDDPLL GND_PLL NO CONNECT NC Not used by SCAN50C400A. I, Power I, Power I, Power I, Power I, Power VDDIO = 3.3V ±5%. It powers the LVDS parallel IO interface, LVCMOS control logic and SCLK input stage. VDDHS = 1.35V. It powers the high-speed CML I/O circuitry and MDIO serial control logic. Ground reference. GND should be tied to a solid ground plane through a low impedance path. GND and GND_PLL should both be at the same potential. VDDPLL− GND_PLL = 1.35V. It powers PLL circuitry of the device. Ground reference to PLL circuitry. GND_PLL should be tied to a solid plane through a low inductance path. GND and GND_PLL should both be at the same potential. A6 B4 A4 B3 A3 B19 L19 P19 W16 AA16 AB19 I, LVCMOS I, LVCMOS I, LVCMOS I, LVCMOS O, LVCMOS RESERVED / TEST PINS 7 www.national.com SCAN50C400A Pin Descriptions - Power Pin / Type / Ball Number Pin Name VDDIO VDDPLL VDDHS Voltage 3.3V 1.35V 1.35V Ball Numbers E5, E6, E7, E8, F5, G5, H5, J5, K5, L5, M5, N5, P5, R5, T5, U5, V5, V6, V7, V8 G18, H18, J18, K18, L18, M18, N18, P18, R18, T18 E10, E11, E12, E13, E14, E15, E16, E17, E18 V10, V11, V12, V13, V14, V15, V16, V17, V18, T4 D14, D17, D19, F19, H19, K19, W14, D21, F21, H21, P21, T21, V21 E1, F1, J1, L1, M1, P1, U1, V1 C3, D3, H3, L3, M3, R3, T3, W3, Y3 C5, C7, Y7, A8, AB8, Y9, C10, Y10, A12, AB12, C13, Y13 D15, Y15, AB15, B18, Y18, AB18, D22, F22, H22, K22, M22, P22, T22, V22, Y22   G7, H7, J7, K7, L7, M7, N7, P7, R7, T7 G8, H8, J8, K8, L8, M8, N8, P8, R8, T8 G9, H9, J9, K9, L9, M9, N9, P9, R9, T9 G10, H10, J10, K10, L10, M10, N10, P10, R10, T10 G11, H11, J11, K11, L11, M11, N11, P11, R11, T11 G12, H12, J12, K12, L12, M12, N12, P12, R12, T12 G13, H13, J13, K13, L13, M13, N13, P13, R13, T13 G14, H14, J14, K14, L14, M14, N14, P14, R14, T14 G15, H15, J15, K15, L15, M15, N15, P15, R15, T15 G16, H16, J16, K16, L16, M16, N16, P16, R16, T16 A1, B1, AA1, AB1, A2, B2, E2, F2, J2, L2, M2, P2, U2, V2, AA2, AB2 G3, C4, D4, G4, H4, L4, M4, R4, W4, D5, W5, D7, W7, B8, AA8 C9, D9, E9, V9, W9, D10, W10, A11, B11, AA11, AB11, B12, AA12, D13, W13 C14, Y14, A15, B15, C15, W15, AA15 C16, D16, Y16, AB16, A17, B17, C17, W17, Y17, AA17 A18, C18, D18, F18, U18, W18, AA18 A19, C19, E19, G19, J19, M19, N19, R19, T19, U19, V19, W19, Y19, AA19 A20, B20, C20, D20, E20, F20, G20, H20, J20, K20, L20, M20, N20, P20, R20, T20, U20, V20, W20, Y20, AA20, AB20 A21, B21, C21, K21, M21, Y21, AA21, AB21 A22, B22, C22, AA22, AB22 AB17 GND 0V GND_PLL 0V NC Float Note: I = Input O = Output IO = Input/Output www.national.com 8 SCAN50C400A Functional Descriptions REFERENCE CLOCK The reference clock SCLK± is a differential input clock that synchronizes the transmitters of the SCAN50C400A. Internal low-jitter PLLs are used to frequency-lock to the lower speed SCLK± at 125 MHz, multiply and generate the internal clocks that sample the input LVDS transmit data, and the high-speed bit-clock that shifts out the transmit serial data at HT±. The input stage at SCLK± accepts HSTL differential clock signals and provides a 50 Ω termination to Ground on each input. It should be connected to a low-jitter clock source free from periodic jitter with less than 2ps-rms random jitter. Figure 1 illustrates a possible connection to SCLK. LVDS input data and transmit clocks (T1_CLK± and T2_CLK±) should be frequency-locked to SCLK±. Figure 1 illustrates the SCLK input stage. 20046104 FIGURE 1. SCLK± Driven by HSTL Clock Driver / Crystals 9 www.national.com SCAN50C400A DATA RATE / DEVICE CONFIGURATION SCAN50C400A supports multiple data rates at 1.25, 2.50 or 5.0 Gbps selected by two control pins, MODE0 and MODE1. SCLK± is fixed at 125 MHz, and the transfer rate at the parallel LVDS side is also fixed at 1.25 Gbps, regardless of the line data rate selected. The SCAN50C400A is a selectable 1:1, 2:1 or 4:1 serializer/deserializer at line data rate of 1.25, 2.5, or 5.0 Gbps. See Figure 2. MODE1 MODE0 0 1 0 1 Mode control is set at power-up via the MODE0 and MODE1 pins. These pins include internal pull-up devices, thus default to (1,1) 5 Gbps Mode if undriven. After power-up the mode of the device may be changed at any time. When mode is changed data integrity is not guaranteed until after each active channel has re-locked. Lock time is dependant upon the data pattern. Description 5.0 Gbps, 4:1 Serializer/Deserializer T1[1-4]± to HT1±. LSB T1_1± is the first bit transmitted. T1[5-8]± to HT2±. LSB T1_5± is the first bit transmitted. T2[1-4]± to HT3±. LSB T2_1± is the first bit transmitted. T2[5-8]± to HT4±. LSB T2_5± is the first bit transmitted. HR1± to R1[1-4]±. LSB R1_1± is the first bit received. HR2± to R1[5-8]±. LSB R1_5± is the first bit received. HR3± to R2[1-4]±. LSB R2_1± is the first bit received. HR4± to R2[5-8]±. LSB R2_5± is the first bit received. 2.5 Gbps, 2:1 Serializer/Deserializer (T1_1±, T1_3±) to HT1±. LSB T1_1± is the first bit transmitted. T1_2± and T1_4± are ignored. (T1_5±, T1_7±) to HT2±. LSB T1_5± is the first bit transmitted. T1_6± and T1_8± are ignored. (T2_1±, T2_3±) to HT3±. LSB T2_1± is the first bit transmitted. T2_2± and T2_4± are ignored. (T2_5±, T2_7±) to HT4±. LSB T2_5± is the first bit transmitted. T2_6± and T2_8± are ignored. HR1± to (R1_1±, R1_3±). LSB R1_1± is the first bit received. R1_2±, R1_4± replicate R1_1± and R1_3±. HR2± to (R1_5±, R1_7±). LSB R1_5± is the first bit received. R1_6±, R1_8± replicate R1_5± and R1_7±. HR3± to (R2_1±, R2_3±). LSB R2_1± is the first bit received. R2_2±, R2_4± replicate R2_1± and R2_3±. HR4± to (R2_5±, R2_7±). LSB R2_5± is the first bit received. R2_6±, R2_8± replicate R2_5± and R2_7±. 1.25 Gbps, Feed-through 1:1 Serializer/Deserializer. T1_1± to HT1±. T1[2-4]± are ignored. T1_5± to HT2±. T1[6-8]]± are ignored. T2_1± to HT3±. T2[2-4]± are ignored. T2_5± to HT4±. T2[6-8]± are ignored. HR1± to R1_1±. R1[2-4]± replicate R1_1±. HR2± to R1_5±. R1[6-8]± replicate R1_5±. HR3± to R2_1±. R2[2-4]± replicate R2_1±. HR4± to R2_5±. R2[6-8]± replicate R2_5±. 1 0 0 1 www.national.com 10 SCAN50C400A 20046105 FIGURE 2. SCAN50C400A at 5, 2.5 and 1.25 Gbps Modes, Channel 1 Shown (x = don't care) 11 www.national.com SCAN50C400A LVDS TRANSMIT DATA BUS The 4-bit LVDS transmit data bus of channels 1 and 2, are registered by both the rising and falling edges of T1_CLK±. Similarly, the 4-bit LVDS transmit data bus of channels 3 and 4, are registered by T2_CLK±. The LVDS data bus has a fixed transfer rate of 1.25 Gbps. T1_CLK± and T2_CLK± are 625 MHz and must be frequency-locked to the reference clock SCLK±. Internal FIFO's are used to compensate against the phase skew between T1_CLK± or T2_CLK± and the internal clock that samples the input transmit data. Channels 1 and 2 share the same transmit clock T1_CLK±, while channels 3 and 4 share the same transmit clock T2_CLK±. The two channels, 1 and 2, or 3 and 4, effectively form an 8-bit LVDS transmit data bus that are serialized into two high-speed serial bit streams, providing an aggregated through-put of up to 10 Gbps in either direction. Each serializer follows a bit interleaving order with the LSB of the 4-bit LVDS transmit data being the first bit to be transmitted at HT±. Figure 9 shows the timing diagram of the transmit LVDS interface. HIGH-SPEED DATA OUTPUT The high-speed serialized bit stream is output at HT±, driven by a current-mode-logic (CML) driver with optional signaling conditioning and optional VOD adjustment to optimize performance over a wide range of transmission length and attenuation distortion result from a low cost FR4 backplane. The CML I/O is designed for AC coupling. Internal 50Ω resistors connected from HT+ and HT− to VDDHS terminate the outputs of each driver. The output level can be programmed from 650 mVp-p to 315mVp-p in 8 steps. It is programmed through the serial control interface (See Table 2). CML VOD Adjust Typical Levels STEP SettingMDIO Register (offset 30.49) (0x0000) (0x0492) - Default (0x0924) (0x0DB6) (0x1248) (0x16DA) (0x1B6C) (0x1FFE) AC CoupledVOD (mV) TYP 650 550 430 420 405 380 350 315 20046106 FIGURE 3. High-Speed CML Output Waveforms with de-emphasis disabled (Full VOD) Each high-speed CML driver of the SCAN50C400A includes a de-emphasis filter. It is a user-programmable 2-tap FIR filter used to equalize the transmission channel to reduce intersymbol interference. The FIR filter is designed to reduce the output level of lower frequency components of the data bit stream. Figure 4 shows the HT waveform of 2 continuous 1’s (or 2 continuous 0’s), in which the output level of the 2nd bit (and subsequent bits of the continuous 1’s) is reduced. The configuration of the FIR filter is user programmable through registers 30.5 and 30.6 which are accessible through the Serial control Interface. www.national.com 12 SCAN50C400A 20046107 FIGURE 4. High-Speed CML Output Waveforms with signal conditioning enabled Signal Conditioning Levels -Registers 1, 2 (Offset = 30.5, 30.6) Register 30.5 0000’h F224’h F234’h F040’h F448’h Register 30.6 0000’h 0D44’h 0A46’h 0808’h 0688’h De-emphasis (in dB) 0 (Default) −1.6 −3.5 −6.5 −8.5 VODSB (mVP-P) 1100 715 710 880 850 VODS2 (mVP-P) 1100 590 470 420 320 13 www.national.com SCAN50C400A DESERIALIZER Serial bit stream is received at HR± terminals. The input stage is designed for AC-coupling. Internal 50Ω termination resistors connect HR+ and HR− to an internal bias. At power-up, in the absence of data, the clock/data recovery circuit will be frequency-locked to SCLK. A clock/data recovery circuit locks to the incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The clock/data recovery circuit expects a coded input bit stream with no more than 20 bits (@5Gbps) of continuous one's or continuous zero's. Similarly, at 2.5 Gbps with 2 multiplexed 8b/10b bit streams, the receiver expects no more than 10 bits of continuous 1’s or continuous 0’s, and at 1.25 Gbps, the receiver expects no more than 5 bits of continuous 1’s or 0’s, as guaranteed by 8b/10b coding. The recovered bit clock is used to re-time the incoming data, after which the serial bit stream is deserialized. The recovered nibble clock from either Channel 1 or Channel 2 is automatically selected as the recovered clock at R1_CLK± and used to strobe the recovered data R1[1-4]± and R1[5-8]±. An internal FIFO is used to compensate against phase skew between the recovered clocks of the two channels. In the absence of data transitions at one of the two channels (for example, a loss of the link), user intervention is recommended to power-down the deserializer (through register 30.1) that has lost the link. This will ensure use of the recovered clock from the channel with valid data. Similarly, one recovered nibble clock from either Channel 3 or Channel 4 is selected as the recovered clock at R2_CLK±. Figure 10 shows a timing diagram of the recovered LVDS data bus. The de-serializing process does not rely on any framing protocol. As a result, at 5 Gbps, any one particular bit in the serial bit stream may appear in any one of the 4 LVDS output data bits at start-up; and at 2.5 Gbps, any one particular bit in the serial bit stream may appear in any one of the 2 LVDS output data bits at start up. Subsequent de-serialization follows a bit de-interleaving order. This bit de-interleaving process is illustrated in Figure 2. 20046108 FIGURE 5. High-Speed IO, AC Coupled www.national.com 14 SCAN50C400A LVDS LOOPBACK (Local Serial Loopback) To support local self-testing, the SCAN50C400A is equipped with LVDS loopback test mode, activated by pulling LSLB low. LSLB affects all four channels. It enables an internal loopback path from each serializer's high-speed bit stream to its deserializer inputs. It provides a diagnosis path from the LVDS transmit data bus at T1[1-8]± and T2[1-8]±, through the serializers, loopback to the deserializers, and output at the deserializer's LVDS receive data bus at R1[1-8]± and R2[1-8] ±. The recovered LVDS receive data can be compared to the LVDS transmit data for self-testing through the host. This loopback mode is also commonly referred as local serial loopback. For normal operation, LSLB and HSLB should be driven high. In this loopback mode the HT outputs are disabled. See Loopback Mode table. LSLB pin includes an internal pull-up and defaults to normal SERDES mode. 20046109 FIGURE 6. SCAN50C400A in LVDS Loopback (Channel 1 at 5 Gbps Shown) HIGH-SPEED LOOPBACK (Remote Loopback or Line Loopback To support remote self-testing, the SCAN50C400A is equipped with High-Speed Loopback test mode, activated by pulling HSLB low. HSLB affects all four channels. It enables an internal loopback path from each deserializer's low -speed LVDS receive data bus to its transmitter LVDS inputs. It provides a diagnosis path from the high-speed serial bit stream at HR±, through the deserializer, loopback to the transmit inputs of the serializer and output at the CML outputs HT±. When the test is originated from an upstream device, the High-Speed Loopback test mode supports self-testing of 2 transceivers and the transmission channel. The SCAN50C400A supports high-speed loopback for a synchronous system in which both the local and remote SCAN50C400A transceivers are frequency-locked to the same system clock SCLK. The high-speed loopback is also commonly referred as remote loopback, or line loopback. When both LSLB and HSLB are driven low, the SCAN50C400A will be defaulted to the LVDS Loopback test mode. For normal operation, HSLB and LSLB should be driven high. See Loopback Mode table. HSLB pin includes an internal pull-up and defaults to normal SERDES mode. 15 www.national.com SCAN50C400A 20046110 FIGURE 7. SCAN50C400A in High-Speed Loopback (5 Gbps Shown) Loopback Mode Table LSLB 1 1 0 0 HSLB 1 0 1 0 Mode Normal SERDES Mode (default state) High-Speed Loopback Mode (HR looped to HT) LVDS Loopback Mode (T data looped to R) Not Recommended. Defaults to LVDS Loopback Mode. default values, and the MDIO management bus is inhibited. RESETB should be driven low for more than 1ms while SCLK is running. When RESETB goes high, the SCAN50C400A exits the reset state, the MDIO management bus is enabled, and the transmit PLL starts to acquire lock, typically within 100us. After RESETB goes high, the receiver PLL’s are initially frequency locked to SCLK. When valid data is presented at the receiver inputs, HR±, the receiver’s PLL’s are phaselocked to the incoming data. RESETB pin includes an internal pull-up. Software reset can be activated through the Serial Control Interface. See Control Register 1 (offset=30.1) for details. During software reset, the Serial Control Interface remains functional, but all registers are preset to their default values. Software reset can only be activated in normal mode when both LSLB and HSLB are at a logic high.. POWER DOWN When PDNB is pulled low, the SCAN50C400A is put into the hardware power down mode. Most internal circuitry is shut down to conserve power. All high-speed CML IO's are at static high due to the internal termination resistor (pulled-high to 1.35V). All LVDS inputs are at high impedance state with internal 100Ω termination resistor connecting between each complimentary input pair. All LVDS outputs are floating. The MDIO management bus is inactive. If powered down by the PDNB pin, it must then be enabled by the PDNB pin. Software power down can also be activated through the Serial Control Interface. During software power down, the MDIO management bus remains functional. See Control Register 1 (offset=30.1) for details. If powered down by the software, the device must be reenabled through the software power down bit. PDNB pin includes an internal pull-down and defaults to Power Down mode, device is disabled until actively driven (enabled). RESET When RESETB is driven low, the SCAN50C400A is put into the reset state. In this state, all MDIO registers are set to the www.national.com 16 SCAN50C400A UN-USED INPUTS AND FAILSAFE CONDITIONS When LVDS inputs are open, internal fail-safe circuitry will force both of them low, and the high-speed CML drivers will output a logic low. (See specific conditions in table below). When CML inputs are open, the internal clock/data recovery circuitry will be frequency-locked to the SCLK clock. The LVDS output drivers will be forced to static logic high. LVCMOS inputs (MODE0, MODE1, LSLB, HSLB, RESETB) have internal pull-up resistors to 3.3V rail. 5 Gbps normal SERDES mode is the default state. LVCMOS input PDNB has an internal pull-down resistors. This must be driven or tied high to enable the device. All Serial Management Interface pins (MDC, MDIO, PHYADn) have internal pull-high resistors. Typical pull-up is 30 kΩ to the 1.35V rail. Failsafe Condition Table—Serializer INPUTS SCLK running running running running floating X = either High or Low OUTPUTS LVDS DATA INPUTS Tn+ floating X X X X Tn− floating X X X X CML OUTPUTS HTn+ Low Low Low Last valid state High HTn− High High High Last valid state High Notes Logic Low Logic Low Logic Low Logic High or Low Both High, 0V Differential TCLK running floating since power-up Static since power-up Running, then float or static X Failsafe Condition Table—Deserializer INPUTS SCLK running floating CML INPUTS HR+ floating X HR− floating X LVDS DATA OUTPUTS Rn+ High High Rn− Low Low OUTPUTS Rn-CLK Running (625 MHz) Running (