SCAN90CP02

SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 October 2004 SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 General Description The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch. High speed data paths and flow-through pinout minimize internal device jitter, while configurable 0/25/50/100% pre-emphasis overcomes external ISI jitter effects of lossy backplanes and cables. The differential inputs interface to LVDS and Bus LVDS signals such as those on National’s 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The SCAN90CP02 can also be used with ASICs and FPGAs. The non-blocking crosspoint architecture is pinconfigurable as a 1:2 clock or data splitter, 2:1 redundancy mux, crossover function, or dual buffer for signal booster and stub hider applications. Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and differential LVDS PCB interconnect. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85˚C temperature range. Features n n n n n n n n n n n n 1.5 Gbps per channel Low power: 70 mA in dual repeater mode @1.5 Gbps Low output jitter Configurable 0/25/50/100% pre-emphasis drives lossy backplanes and cables Non-blocking architecture allows 1:2 splitter, 2:1 mux, crossover, and dual buffer configurations Flow-through pinout LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs IEEE 1149.1 and 1149.6 compliant Single 3.3V supply Separate control of inputs and outputs allows for power savings Industrial -40 to +85˚C temperature range 28-lead LLP package, or 32-lead LQFP package Block Diagram 20071401 FIGURE 1. SCAN90CP02 Block Diagram © 2004 National Semiconductor Corporation DS200714 www.national.com SCAN90CP02 Pin Descriptions Pin Name LLP Pin Number LQFP Pin Number 9 10 13 14 32 31 28 27 7 6 8 17 4 3 2 1 22 23 21 19 24 I/O, Type Description DIFFERENTIAL INPUTS COMMON TO ALL MUXES IN0+ IN0− IN1+ IN1− OUT0+ OUT0− OUT1+ OUT1− SEL0, SEL1 EN0, EN1 PEM00, PEM01 PEM10, PEM11 TDI TDO TMS TCK TRST N/C POWER VDD 11, 14, 16, 22, 25 12, 16, 18, 25, 29 I, Power VDD = 3.3V ± 0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from VDD to GND plane. Ground reference to LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. 9 10 12 13 27 26 24 23 6 5 7 15 4 3 2 1 19 20 18 17 21 8, 28 I, LVDS I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. Inverting and non-inverting differential outputs. OUT0 ± can be connected to any one pair IN0 ± , or IN1 ± . LVDS compatible (Note 2). Inverting and non-inverting differential outputs. OUT1 ± can be connected to any one pair IN0 ± , or IN1 ± . LVDS compatible (Note 2). Select Control Inputs Output Enable Inputs Channel 0 Output Pre-emphasis Control Inputs Channel 1 Output Pre-emphasis Control Inputs Test Data Input to support IEEE 1149.1 features Test Data Output to support IEEE 1149.1 features Test Mode Select to support IEEE 1149.1 features Test Clock to support IEEE 1149.1 features Test Reset to support IEEE 1149.1 features Not Connected SWITCHED DIFFERENTIAL OUTPUTS O, LVDS O, LVDS DIGITAL CONTROL INTERFACE I, LVTTL I, LVTTL I, LVTTL I, LVTTL I, LVTTL O, LVTTL I, LVTTL I, LVTTL I, LVTTL GND (Note 1) 5, 11, 15, 20, 26, 30 Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package. Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized for point-to-point backplane and cable applications. www.national.com 2 SCAN90CP02 Connection Diagrams 20071404 LQFP Top View 20071403 LLP Top View DAP = GND Configuration Select Truth Table SEL0 0 0 1 1 0 1 0 0 X 0 1 1 1 SEL1 0 1 0 1 1 1 0 1 X 0 0 0 1 EN0 0 0 0 0 0 0 1 1 1 0 0 1 1 EN1 0 0 0 0 1 1 0 0 1 1 1 0 0 OUT0 IN0 IN0 IN1 IN1 IN0 IN1 PD PD PD OUT1 IN0 IN1 IN0 IN1 PD PD IN0 IN1 PD Dual Channel Repeater Dual Channel Switch 1:2 Splitter (IN0 powered down) Single Channel Repeater (Channel 1 powered down) Single Channel Switch (IN0 and OUT1 powered down) Single Channel Switch (IN1 and OUT0 powered down) Single Channel Repeater (Channel 0 powered down) Both Channels in Power Down Mode Invalid State* Invalid State* Invalid State* Invalid State* Mode 1:2 Splitter (IN1 powered down) PD = Power Down mode to minimize power consumption X = Don’t Care * Entering these states is not forbidden, however device operation is not defined in these states. Pre-emphasis The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per the Preemphasis Control Selection Table. PEM01 0 0 1 1 Pre-emphasis Control Selection Table Channel 0 PEM00 0 1 0 1 Channel 1 PEM11 0 0 1 1 PEM10 0 1 0 1 0% 25% 50% 100% Pre-emphasis Output Characteristics The output characteristics of the SCAN90CP02 device have been optimized for point-to-point backplane and cable applications. 3 www.national.com SCAN90CP02 Applications Information 20071402 FIGURE 2. SCAN90CP02 Configuration Select Decode www.national.com 4 SCAN90CP02 Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) CMOS Input Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Soldering, 4sec.) Maximum Package Power Dissipation at 25˚C LLP-28 LQFP-32 4.31 W 1.47W −0.3V to +4.0V −0.3V to (VDD +0.3V) −0.3V to +3.6V −0.3V to +3.6V 40mA +150˚C −65˚C to +150˚C +260˚C Derating above 25˚C LLP-28 LQFP-32 Thermal Resistance, θJA LLP-28 LQFP-32 ESD Rating HBM, 1.5 kΩ, 100 pF EIAJ, 0Ω, 200 pF 6.5 kV 29˚C/W 85˚C/W 34.5 mW/˚C 11.8 mW/˚C > 250V Recommended Operating Conditions Min Supply Voltage (VDD– GND) Receiver Input Voltage Operating Free Air Temperature Junction Temperature 3.0 0 −40 25 Typ 3.3 Max 3.6 3.6 85 150 Unit V V ˚C ˚C Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 4) Max Units LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2, PEM00, PEM01, PEM10, PEM11, TDI, TCK, TMS, TRST) VIH VIL IIH IIL IILR CIN1 COUT1 VCL VOH VOL IOS VTH VTL VID VCMR CIN2 IIN High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Low Level Input Current Input Capacitance Output Capacitance Input Clamp Voltage High Level Output Voltage (TDO) Low Level Output Voltage (TDO) Output Short Circuit Current Differential Input High Threshold (Note 5) Differential Input Low Threshold Differential Input Voltage Common Mode Voltage Range Input Capacitance Input Current VIN = VDD = VDDMAX VIN = VSS, VDD = VDDMAX TDI, TMS, TRST Any Digital Input Pin to VSS Any Digital Output Pin to VSS ICL = −18 mA IOH = −12 mA, VDD = 3.0 V IOH = −100 µA, VDD = 3.0 V IOL = 12 mA, VDD = 3.0 V IOL = 100 µA, VDD = 3.0 V TDO VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VCM = 0.8V to 3.55V, VDD = 3.6V VID = 150 mV, VDD = 3.6V IN+ or IN− to VSS VIN = 3.6V, VDD = VDDMAX or 0V VIN = 0V, VDD = VDDMAX or 0V −10 −10 −50 100 0.05 3.5 +10 +10 3.55 -15 −1.5 2.4 VDD-0.2 0.5 0.2 -125 2.0 GND −10 −10 -40 3.5 5.5 −0.8 VDD 0.8 +10 +10 -200 V V µA µA µA pF pF V V V V V mA LVDS INPUT DC SPECIFICATIONS (IN0 ± , IN1 ± ) 0 0 50 mV mV mV V pF µA µA 5 www.national.com SCAN90CP02 Electrical Characteristics Symbol Parameter (Continued) Over recommended operating supply and temperature ranges unless other specified. Conditions Min Typ (Note 4) Max Units LVDS OUTPUT DC SPECIFICATIONS (OUT0 ± , OUT1 ± ) VOD ∆VOD VOS ∆VOS IOS IOSB COUT2 Differential Output Voltage, 0% Pre-emphasis (Note 5) Change in VOD between Complementary States Offset Voltage (Note 6) Change in VOS between Complementary States Output Short Circuit Current, One Complementary Output Output Short Circuit Current, both Complementary Outputs Output Capacitance OUT+ or OUT− Short to GND OUT+ or OUT− Short to VDD OUT+ and OUT− Short to GND OUT+ and OUT− Short to VCM OUT+ or OUT− to GND when TRI-STATE All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. Single channel crossover switch or single channel repeater modes (1 channel active, one channel in power down mode) Splitter mode (One input powered down, both outputs active) Both input/output Channels in Power Down Mode RL = 100Ω between OUT+ and OUT− 250 −35 1.09 −35 −15 15 −15 15 5.5 1.25 400 575 35 1.475 35 -40 40 -30 30 mV mV V mV mA mA mA mA pF SUPPLY CURRENT (Static) ICC0 Supply Current 42 22 60 30 mA mA ICC1 Supply Current - one channel powered down ICC2 ICCZ Supply Current - one input powered down TRI-STATE Supply Current 30 40 mA 1.4 2.5 mA SWITCHING CHARACTERISTICS — LVDS OUTPUTS (Figures 3, 4) tLHT tHLT tPLHD tPHLD tSKD1 tSKCC Differential Low to High Transition Use an alternating 1 and 0 pattern at Time 200 Mb/s, measure between 20% and Differential High to Low Transition 80% of VOD. Time Differential Low to High Propagation Delay Differential High to Low Propagation Delay Pulse Skew Output Channel to Channel Skew Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. |tPLHD–tPHLD| Difference in propagation delay (tPLHD or tPHLD) among all output channels in Splitter mode (any one input to all outputs). RJ - Alternating 1 and 0 at 750 MHz DJ - K28.5 Pattern 1.5 Gbps TJ - PRBS 223-1 Pattern 1.5 Gbps LVDS Output Enable Time tOFF LVDS Output Disable Time LQFP LLP LQFP LLP 50 70 50 0.5 0.5 150 135 2.4 2.4 55 215 180 3.5 3.5 120 ps ps ns ns ps 0 130 315 ps tJIT tON Jitter (0% Pre-emphasis) (Note 7) 1.4 110 42 125 105 110 5 2.5 140 75 160 140 150 12 psrms psp-p psp-p psp-p psp-p ns ns Time from ENx to OUT ± change from TRI-STATE to active. Time from ENx to OUT ± change from active to TRI-STATE. www.national.com 6 SCAN90CP02 Electrical Characteristics Symbol tSW Parameter LVDS Switching Time SELx to OUT ± (Continued) Over recommended operating supply and temperature ranges unless other specified. Conditions Time from configuration select (SELx) to new switch configuration effective for OUT ± . Min Typ (Note 4) 110 Max Units 150 ns SCAN Circuitry Timing Requirements Symbol fMAX tS tH tS tH tW tW tREC Parameter Maximum TCK Clock Frequency TDI to TCK, H or L TDI to TCK, H or L TMS to TCK, H or L TMS to TCK, H or L TCK Pulse Width, H or L TRST Pulse Width, L Recovery Time, TRST to TCK Conditions RL = 500Ω, CL = 35 pF Min 25.0 1.0 2.0 2.0 1.5 10.0 2.5 2.0 Typ Max Units MHz ns ns ns ns ns ns ns Note 3: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 5: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 7: JIT is the jitter from any input to any one differential LVDS output running at the specified data rate and data pattern, the other channel is powered off. Jitter is not production tested, but guaranteed through characterization on a sample basis. Random Jitter is measured RMS with a histogram including 1500 histogram window hits. K28.5 pattern is repeating bit streams of (0011111010 1100000101). This deterministic jitter or DJ pattern is measured to a histogram mean with a sample size of 350 hits. Total Jitter is measured peak to peak with a histogram including 3500 window hits. Timing Diagrams 20071415 FIGURE 3. LVDS Signals 7 www.national.com SCAN90CP02 Timing Diagrams (Continued) 20071416 FIGURE 4. LVDS Output Transition Time 20071417 FIGURE 5. LVDS Output Propagation Delay 20071420 FIGURE 6. Configuration and Output Enable/Disable Timing www.national.com 8 SCAN90CP02 Typical Performance Characteristics for LLP Package Power Supply Current vs. Bit Data Rate Total Jitter (TJ) vs. Bit Data Rate 20071441 20071442 Dynamic power supply current was measured while running a PRBS 223-1 pattern in dual channel repeater mode. VCC = 3.3V, TA = +25˚C, VID = 0.5V, VCM = 1.2V Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in single channel repeater mode. VCC = 3.3V, TA = +25˚C, VID = 0.5V, 0% Pre-emphasis Total Jitter (TJ) vs. Temperature Positive Edge Transition vs. Pre-emphasis Level 20071455 20071443 Dynamic power supply current was measured while running a PRBS 223-1 pattern in dual channel repeater mode. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, 0% Pre-emphasis FIGURE 7. Typical Performance Characteristics 9 www.national.com SCAN90CP02 Design-For-Test (DfT) Features IEEE 1149.1 SUPPORT The SCAN90CP02 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. The TAP also provides access to the IEEE 1149.6 test features if AC-coupled interconnects are used. Refer to the BSDL file located on National’s website for the details of the SCAN90CP02 IEEE 1149.1 implementation. IEEE 1149.6 SUPPORT AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-coupled), single ended networks. It is unable to test dynamic (AC-coupled) digital networks because the AC-coupling blocks static signals. The SCAN90CP02 - which is intended for use in up to 1.5 Gbps data paths - has been designed with IEEE 1149.6 support to enable test of AC-coupled interconnects. FAULT INSERTION StuckAt is a feature that enables the user to override logic values on any of the external pins during normal operation. StuckAt can be thought of as having the same capabilities as the IEEE-1149.1 EXTEST instruction but on a per pin bases. Because this feature occurs on a per-pin basis, normal device operation (mission mode) is possible with the exception of the desired faults. For more information on any of these features, refer to Application Note AN-1313, SCAN90CP02 Design-for-Test Features. www.national.com 10 SCAN90CP02 Physical Dimensions inches (millimeters) unless otherwise noted LLP, Plastic, QUAD, Order Number SCAN90CP02SP (1000 piece Tape and Reel), SCAN90CP02SPX (4500 piece Tape and Reel) NS Package Number SPA28A 11 www.national.com SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LQFP, Plastic, Quad Order Number SCAN90CP02VY (250 piece Tray) SCAN90CP02VYX (1000 piece Tape and Reel) NS Package Number VBE32A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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