SCAN926260

SCAN926260 Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST March 6, 2008 SCAN926260 Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST General Description The SCAN926260 integrates six 10-bit deserializer devices into a single chip. The SCAN926260 can simultaneously deserialize up to six data streams that have been serialized by National Semiconductor’s 10-bit Bus LVDS serializers. In addition, the SCAN926260 is compliant with IEEE standard 1149.1 and also features an At-Speed Built-In Self Test (BIST). For more details, please see the sections titled "IEEE 1149.1 Test Modes" and "BIST Alone Test Modes." Each deserializer block in the SCAN926260 has it’s own powerdown pin (PWRDWN[n])and operates independently with its own clock recovery circuitry and lock-detect signaling. In addition, a master powerdown pin (MS_PWRDWN) which puts all the entire device into sleep mode is provided. The SCAN926260 uses a single +3.3V power supply and consumes 1.2W at 3.3V with a PRBS-15 pattern on all channels at 660Mbps. Features ■ Deserializes one to six Bus LVDS input serial data streams with embedded clocks ■ IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test ■ ■ ■ ■ ■ ■ ■ ■ modes Parallel clock rate 16-66MHz On chip filtering for PLL High impedance inputs upon power off (Vcc = 0V) Single power supply at +3.3V 196-pin LBGA package (Low-profile Ball Grid Array) package Industrial temperature range operation: −40°C to +85°C ROUTn[0:9] and RCLKn default high when channel is not locked Powerdown per channel to conserve power on unused channels Typical Application 20028302 Ordering Information Order Number SCAN926260TUF SCAN926260TUFX Function Six Channel 10-bit BLVDS Deserializer with IEEE 1149.1 and At-Speed BIST Six Channel 10-bit BLVDS Deserializer with IEEE 1149.1 and At-Speed BIST Package UJB196A (Trays) UJB196A (Tape and Reel) TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 200283 www.national.com SCAN926260 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) BLVDS Input Voltage (Rin ±) Maximum Package Power Dissipation Capacity @ 25°C Package Thermal Resistance  θJA 196 LBGA:  θJC 196 LBGA: Storage Temp. Range -0.3 to 3.8V -0.3V to +3.9V 3.7W Junction Temperature Lead Temperature (Soldering 10 Seconds) ESD Ratings: Human Body Model Machine Model +125°C +225°C >2KV >750V Recommended Operating Conditions Supply Voltage (VDD) Operating Free Air Temperature (TA) 3.0V to 3.6V -40°C to +85°C 34°C/W 8°C/W -65°C to +150°C Electrical Characteristics specified. (Note 2) Symbol Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current Input Current High Level Output Voltage Low Level Output Voltage Output short Circuit Current TRI-STATE Output Current High Level Output Voltage Low Level Output Voltage TRI-STATE Output Current Differential Threshold High Voltage Differential Threshold Low Voltage Input Current LVCMOS/LVTTL DC Specifications: VIH VIL VCL IIN IIN VOH VOL IOS IOZ VOH VOL IOS Over recommended operating supply and temperature ranges unless otherwise Pin/Freq. Min Typ Max Units Conditions 2.0 REN, REFCLK, PWRDWNn , MS_PWRDWN Vin = 0 or 3.6V Vin = 0 or 3.6V IOH = −6mA IOL = 6mA Vout = 0V MS_PWRDWN or REN = 0.8V Vout = 0V or VCC IOH = −12mA IOL = 12mA Vout = 0V TDO TRST, TMS, TDI, BIST_SEL[0:2] GND -0.87 -10 -20 2 GND -15 3 0.18 -46 VCC 0.8 -1.5 +10 +20 VCC 0.5 -85 V V V uA uA V V mA ROUT, RCLK, LOCKn -10 ±0.2 +10 µA 2 GND -15 VCC 0.5 -120 V V mA Bus LVDS DC specifications VTH VTL VCM = 0.025, 1.250, 2.375V (VRI+-VRI-) Vin = +2.4V, Vcc = 3.6 or 0V Vin =0V, Vcc = 3.6 or 0V RI+, RI-10 -10 ±1 ±1 +10 +10 µA µA +3 -50mV -2 +50 mV mV IIN www.national.com 2 SCAN926260 Symbol Supply Current Parameter Conditions Checker Board Pattern, CL=15pF PRBS-15 Pattern, CL=15pF Checker Board Pattern MS_PWRDN= 0.8V, (Note 4) Pin/Freq. Min Typ Max Units 66 MHz 500 600 mA ICCR Total Supply Current 66 MHz 385 mA ΔICCR ICCXR Reduction in Supply Current per Channel Total Supply Current when Powered Down 66 MHz 55 77 100 mA 1.5 2.2 mA Timing Requirements for REFCLK tRFCP tRFDC tRFCP/tTCP tRFTT REFCLK Period REFCLK Duty Cycle Ratio of REFCLK to TCLK REFCLK Transition Time RCLK Period RCLK Duty Cycle LVCMOS/LVTTL Lowto-High Transition Time LVCMOS/LVTTL Highto-Low Transition Time Rout Data Valid before RCLK Rout Data Valid after RCLK High to TRI-STATE Delay Low to TRI-STATE Delay TRI-STATE to High Delay TRI-STATE to Low Delay Deserializer Delay Deserializer PLL LOCK Time from PWRDNn (with SYNCPAT) Deserializer PLL Lock Time from SYNCPAT Deserializer Right Noise Margin Deserializer Left Noise Margin Figure 1 (All Cases) 66 MHz Only tDSR1 Figure 4 (Note 7) Figure 5 (Note 7) Figure 8 (Note 8) 66MHz 16MHz 66MHz 16MHz 66MHz 16MHz 66MHz 16MHz 400 1.3 440 1.4 500 2.51 600 2.59 RCLK 1.75*tRCP+5 1.75*tRCP+6 1.75*tRCP+7 1.75*tRCP+7 (Note 5) CL = 15pF, Figure 3, (Note 6) Figure 2 Figure 2 LOCK, RCLK, ROUT 15.15 41 1.3 1.0 0.4*tRCP -0.4*tRCP 10 10 Figure 7 12 12 1.75*tRCP+10 1.75*tRCP+9 2.5 7.0 1.1 4.5 ns ns ns ns µs µs µs µs ps ns ps ns 50 1.8 1.5 15.15 30 0.95 50 62.5 70 1.05 8 ns ns % Deserializer Switching Characteristics tRCP tRDC tCLH tCHL tROS tROH tHZR tLZR tZHR tZLR RCLK 62.5 55 2.2 2.0 ns % ns ns ns ns ns ns tDD tDSR2 tRNMI-RIGHT tRNMI-LEFT Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. 3 www.national.com SCAN926260 Note 2: Typical values are given for VDD = 3.3V and TA =25°C Note 3: Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VTH and VTL which are differential voltages. Note 4: Total Supply Current when Powered Down (ICCXR) is higher than previous six channel devices because previous devices asserted ROUTn and RCLKn into TRI-STATE upon loss-of-lock, whereas the SCAN926260 now asserts ROUTn and RCLKn HIGH upon loss-of-lock. Note 5: tRDC was specified by measuring the positive pulse on the RCLK and dividing this number by the ideal pulse width. Note 6: tCLH and tCHL are Guranteed by Statistical Analysis (GBSA). Please see Figure 3 for a graphical representation. Note 7: For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions of the incoming data stream (SYNCPATs). tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data and is not specified. Note 8: tRNMI-LEFT and tRNMI-RIGHT are a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer noise margin specification does not include transmitter jitter and is Guaranteed By Statistical Analysis (GBSA). Please see Figure 8 for a graphical representation. SCAN Circuitry Timing Requirements Symbol fMAX tS tH tS tH tW tW tREC Parameter Maximum TCK Clock Frequency TDI to TCK, H or L TDI to TCK, H or L TMS to TCK, H or L TMS to TCK, H or L TCK Pulse Width, H or L TRST Pulse Width, L Recovery Time, TRST to TCK Conditions RL = 500Ω, CL = 35 pF Min 25.0 2.0 1.0 2.5 1.0 10.0 2.5 2.0 Typ 50.0 Max Units MHz ns ns ns ns ns ns ns www.national.com 4 SCAN926260 Timing Diagrams 20028304 FIGURE 1. Deserializer Delay tDD 20028307 FIGURE 2. Output Timing tROS and tROH (Data Valid) 20028331 FIGURE 3. Deserializer CMOS/LVTTL Output Load and Transition Times 5 www.national.com SCAN926260 20028309 FIGURE 4. Locktime from PWRDNn tDSR1 20028311 FIGURE 5. Locktime to SYNCPAT tDSR2 20028313 FIGURE 6. Loss of Lock www.national.com 6 SCAN926260 20028318 FIGURE 7. Deserializer TRI-STATE Test Circuit and Timing 20028330 Note: For an explanation of Ideal Crossing Point and Noise Margin, please see the Application Information section. FIGURE 8. Deserializer Noise Margin and Sampling Window 7 www.national.com SCAN926260 Block Diagram 20028301 Functional Description The SCAN926260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a Bus LVDS data stream from National Semiconductor's DS92LV1021, DS92LV1023, DS92LV8028, SCAN921023, or SCAN921025 Serializer. The deserializers then recover the clock and data to deliver the resulting 10-bit wide words to the outputs. Each of the six channels acts completely independent of each other. Each independent channel has outputs for a 10-bit wide data word, a recovered clock output, and a lock-detect output. The SCAN926260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition, there are two passive states: Powerdown and TRI-STATE. During normal operation, the SCAN6260 also has the capability of utilizing the IEEE 1149.1 test modes (JTAG) or the Built-In Self Test mode (BIST). The following sections describe each operating mode, passive states, and the JTAG and BIST modes. Initialization Before the SCAN926260 receives and deserializes data, it and the transmitting Serializer must initialize the link. Initialization refers to synchronizing the Serializer's and the Deserializer's PLL's to local clocks. The local clocks must be within ±5% of the incoming transmitter clock frequency. After all devices synchronize to local clocks, the Deserializer synchronizes to the Serializer as the second and final initialization step. Step 1: After applying power to the Deserializer, the outputs are held high and the on-chip Power-on Reset (POR) circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in each deserializer begins locking to the local clock www.national.com 8 SCAN926260 (REFCLK). A local on-board oscillator or other source that provides the specified clock input to the REFCLK pin. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the Serializer data sheet for proper operation during the Initialization State. The Deserializer identifies the rising clock edge in a synchronization pattern or pseudo-random data and after 80 clock cycles will synchronize to the data stream from the Serializer. At the point where the Deserializer's PLL locks to the embedded clock, the LOCKn pin goes low and valid data appears at the outputs. clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven high. The system must monitor the LOCKn pin to determine when data is valid. The user has the choice of allowing the deserializer to re-sync to the data stream or to force synchronization by asserting the Serializer SYNC1 or SYNC2 pin high. This scheme is left up to user discretion. One recommendation is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for local or remote control.. Data Transfer After initialization, the Serializer transfers data to the Deserializer. The serial data stream includes a start and stop bit appended by the serializer, which frames the ten data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial 'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 = 400 Mbps. TCLK is provided by the data source and must be in the range of 16MHz to 66MHz. When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low and synchronously delivers valid data at its outputs. The Deserializer locks to the embedded clock, uses it to generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn pin is synchronous to the data on the ROUTn[0:9] pins. While LOCKn is low, data on ROUTn[0:9] is valid. Otherwise, ROUTn[0:9] and RCLKn are high. All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 66 MHz clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls TRI-STATE of all the outputs. The Deserializer input pins are high impedance during Powerdown (PWRDNn or MS_PWRDN low) and power-off (Vcc = 0V). Powerdown The Powerdown state is a low power sleep mode that the Deserializer typically occupies while waiting for initialization or to reduce power consumption when no data is transferred. While in Powerdown Mode, the PLL stops and RCLK and ROUTn[0:9] are high, which reduces the supply current for each channel by approximately 80mA. Each channel has a powerdown (PWRDWNn) pin that puts the respective channel into sleep mode when asserted low. In addition, the SCAN926260 has a master powerdown (MS_PWRDWN) pin that overrides each individual powerdown pin and puts the entire device into sleep mode when asserted low (This same condition can be replicated by asserting all six individual powerdown pins low.). The powerdown pins are internally pulled low which defaults the device into sleep mode. Active operation requires asserting a high on MS_PWRDWN and the selected channel’s PWRDWNn pin. Upon exiting Powerdown, the Deserializer enters the Initialization state. The system must then allow time to Initialize before data transfer can begin. TRI-STATE® When the system drives the REN pin low, the Deserializer enters TRI-STATE. This will TRI-STATE the receiver output pins (ROUTn[0:9]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the previous state as long as all other control pins remain static (PWRDWNn, MS_PWRDWN). The LOCKn pin is not affected by REN and continues to be active, signalling LOCK status. This allows the system to be sure the channel is locked before enabling the data outputs. Resynchronization Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the embedded 9 www.national.com SCAN926260 SCAN926260 Control Signal Truth Table SCAN Mode Internal Signals STATE SCAN (Note 1) SCAN (Note 1) Powerdown (Note 2) Powerdown (Note 3) Normal, Not Locked (Note 5) Normal, Locked (Note 5) REN = Low, Not Locked (Note 4, 6) REN = Low, Locked (Note 4, 6) SCAN_HIZB 0 1 1 1 SCAN_BIST X 1 0 0 MS_PWRDWN X X 0 1 INPUTS PWRDWN[n] X X X All 6 @ 0 REN X X X X LOCK[n] Z Z 1 1 OUTPUTS ROUTn[0:9] 10 @ Z 10 @ Z 10 @ 1 10 @ 1 RCLK[n] Z Z 1 1 1 0 1 1 1 1 10 @ 1 1 1 0 1 1 1 0 data clock 1 0 1 1 0 1 10 @ Z Z 1 0 1 0 1 0 0 0 0 1 10 @ Z 10 @ 1 Z 1 Default State (Note 6) Key: Z = High Impedance X = Don’t Care 10 @ Z = All 10 ROUT for the respective Channel are High Impedance 1 = High Voltage Level 0 = Low Voltage Level SCAN_HIZB = the internal control signal from the HighZ command at the TAP Controller SCAN_BIST = the internal control signal from the BIST command at the TAP Controller Notes: 1) JTAG/SCAN has the highest priority. SCAN_HIZB is active low and SCAN_BIST is active high. If either control is active, the outputs will be in TRI-STATE. 2) MS_PWRDWN has the second highest priority. When MS_PWRDWN is low, the entire chip enters sleep mode and all outputs (ROUTn[0:9], RCLK[n], and LOCK[n]) are high. 3) PWRDWN[n] are the six individual power-down pins. Each will power down the respective channel. A special case occurs when all six PWRDWN[n] pins are low-the common bias circuits will also be powered down. This state is equivalent to the case when MS_PWRDWN is low. 4) REN has a lower priority than PWRDWN[n]. When REN is low, the output data (ROUTn[0:9] and RCLK[n]) will be in TRI-STATE. The LOCK[n] signal’s output is not affected by REN. 5) During normal operation mode (no SCAN, no Power-down, and REN high), LOCK[n] controls the ROUTn[0:9] and RCLK[n] outputs. When LOCK[n] is high (unlocked), all outputs will be 1, and when LOCK[n] is low (locked), both data and clock will be valid at the outputs. BIST-ALONE mode is considered part of normal operation and can be overriden by any of the above priorities. 6) There are internal pull-downs on the REN, PWRDWNn and MS_PWRDWN pins. Active operation requires asserting these pins high. www.national.com 10 SCAN926260 IEEE 1149.1 Test Modes The SCAN926260 features interconnect test access that is compliant to the IEEE 1149.1 Standard for Boundary Scan Test (JTAG). All digital TTL I/O's on the device are accessible using IEEE 1149.1, and entering this test mode will override all input control cases including power down and REN. In addition to the four required Test Access Port (TAP) signals of TMS, TCK, TDI, and TDO, TRST is provided for test reset. To supplement the test coverage provided by the IEEE 1149.1 test access to the digital TTL pins, the SCAN926260 has two instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at LVDS levels and is only intended as a go no-go test (e.g. missing cables). The second method is the RUNBIST instruction. It is an "at-system-speed" interconnect test. It is executed in approximately 33ms with a system clock speed of 66MHz. There are 12 bits in the RX BIST data register for notification of PASS/FAIL and TEST_COMPLETE, with two bits for each of the six channels. The RX BIST register is defined as (from MSB to LSB): DS92LV8028, the SCAN921023 and the SCAN921025 Serializers. An important detail is that once both devices have the RUNBIST instruction loaded into their respective instruction registers, both devices must move into the RTI state within 4K system clocks (At a system CLK of 66MHz and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan chain or LSP. However, it can be a problem with some multi-drop devices. This test mode has been simulated and verified using National's Enhanced SCAN Bridge (SCANSTA111). BIST Alone Test Modes The SCAN926260 also supports a BIST Alone feature which can be run without enabling the JTAG TAP controller. This feature provides the ability to run continuous BER testing on all channels, or on individual channels without affecting live traffic on other channels. The ability to run the BERT (Bit-Error-Rate-Test) while adjacent channels are carrying normal traffic is a useful tool to determine how normal traffic will affect the BER on any given channel. The BIST Alone features can be accessed using the 5 pins defined as BIST_SEL0, BIST_SEL1, BIST_SEL2, BIST_ACT, and BISTMODE_REQ. BIST_ACT activates the BIST Alone mode. The BIST Alone mode will continue until deactivated by the BIST_ACT pin. The BIST_ACT input must be high or low for four or more clock cycles in order to activate or deactivate the BIST Alone mode. The BIST_ACT input is pulled low internally. BISTMODE_REQ is used to select either gross error reporting or a specific output error report. When the BIST Alone mode is active, the LOCKn output for all channels running BIST Alone will go low and the respective ROUTn(0:9) output will report any errors. When BISTMODE_REQ is low, the error reporting is set to Gross Mode, and whenever a bit contains one or more errors, ROUT(0:9) for that channel goes high and stays high until deactivation by the BIST_ACT input. When BISTMODE_REQ is high, the output error reporting is set to Bit Error mode. Whenever any data bit contains an error, the data output for that corresponding bit goes high. The default setting is Gross Error mode. The three BIST_SELn inputs determine which channel is in BIST Alone mode according to the following table: RX BIST Register Bit Number 11 (MSB) 10 9 8 7 6 5 4 3 2 1 0 (LSB) Description BIST COMPLETE for Channel 6 BIST PASS/FAIL for Channel 6 BIST COMPLETE for Channel 5 BIST PASS/FAIL for Channel 5 BIST COMPLETE for Channel 4 BIST PASS/FAIL for Channel 4 BIST COMPLETE for Channel 3 BIST PASS/FAIL for Channel 3 BIST COMPLETE for Channel 2 BIST PASS/FAIL for Channel 2 BIST COMPLETE for Channel 1 BIST PASS/FAIL for Channel 1 A "pass" indicates that the BER (Bit-Error-Rate) is better than 10-7. This is a minimum test, so a "fail" indication means that the BER is higher than 10-7. The BIST features of the SCAN926260 six channel deserializer are compatible with the BIST features on the BIST Alone Mode Selection BIST_ACT 1 1 1 1 1 1 1 1 0 BIST_SEL2 0 0 0 0 1 1 1 1 X BIST_SEL1 0 0 1 1 0 0 1 1 X BIST_SEL0 0 1 0 1 0 1 0 1 X BIST for Channel 0 1 2 3 4 5 All Channels IDLE IDLE 11 www.national.com SCAN926260 Application Information USING THE SCAN926260 The SCAN926260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream up to 660 Mbps from one of National Semiconductor's 10-Bit Serializers. The Deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the output. The Deserializer uses a separate reference clock (REFCLK) and an on-board PLL to extract the clock information from the incoming data stream and then deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCKn output high when loss of lock occurs. POWER CONSIDERATIONS An all CMOS design of the Deserializer makes it an inherently low power device. POWERING UP THE DESERIALIZER The SCAN926260 can be powered up at any time. The REFCLK input can be running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs (ROUTn[0:9]), the recovered clock (RCLKn), and LOCKn are high until the Deserializer detects data transmission at its inputs and locks to the incoming data stream. DATA TRANSFER Once the Deserializer powers up, it must be phase locked to the transmitter to transfer data. Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to one of the SYNC inputs of the Serializer will guarantee that enough SYNC patterns are sent to achieve Deserializer lock. The Deserializer can also lock to incoming data by simply powering up the device and allowing the “lock to pseudo random data” circuitry to find and lock to the data stream. While the Deserializer LOCKn output is low, data at the respective channel’s Deserializer outputs (ROUTn[0:9]) is valid, except for the specific case when loss of lock occurs during transmission which is further discussed in the "Recovering from LOCK Loss" section below. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data. Various environmental and systematic factors include: Serializer: TCLK jitter, VDD noise (noise bandwidth and outof-band noise) Media: ISI, Large VCM shifts Deserializer: VDD noise Please see the section on "Using tRNM to Validate Signal Quality" for more information. RECOVERING FROM LOCK LOSS In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received two times in a row to indicate www.national.com 12 loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be suspect for bit errors. The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as described above, or by locking to pseudo random data, which can take more time, depending on the data patterns being received. HOT INSERTION All Bus LVDS Deserializers are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 9. 20028315 FIGURE 9. Hot Insertion Lock to Pseudo-Random Data TRANSMISSION MEDIA The Serializer and Deserializer can also be used in point-topoint configurations, through PCB trace, through twisted pair cable, or twinax cables. In point-to-point configurations, the transmission media need only be terminated at the receiver end. Please note that in point-to-point configurations, the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. In some applications, multidrop configurations may be possible. Bus LVDS provides a ±1.0V common mode range at the receiver inputs. FAILSAFE BIASING FOR THE SCAN926260 The SCAN926260 has internal failsafe biasing and an improved input threshold sensitivity of ±50mV versus ±100mV for the DS92LV1210.. This allows for a greater differential noise margin. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the SCAN926260 can pickup noise as a signal and cause unintentional locking. For example, this can occur when an input cable is disconnected. External resistors can be added to the receiver circuit board to boost the level of failsafe biasing. Typically, the non-inverting receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The pull-up and pulldown resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors should be chosen so that enough current is drawn to provide a +15mV minimum drop across the termination resistor in the presence of anticipated input noise. Also, in systems where use of the individual channel is well known or controlled, using the respective channel’s PWRDWNn pin(s) may eliminate the need for ex- SCAN926260 ternal Failsafe Biasing. Please see Figure 11 for the Failsafe Biasing Setup. DIFFERENCES BETWEEN the DS92LV1260, the SCAN921260, and the SCAN926260 The DS92LV1260 is a six channel, ten bit, Bus LVDS Deserializer with random lock capability and a parallel clock rate up to 40MHz. Each channel contains a recovered clock (RCLKn) and lock (LOCKn) output. The DS92LV1260 also contains a seventh serial input channel that serves as a redundant input. Also, unlike previous deserializers, the LOCKn signal is synchronous to valid data appearing on the outputs. Please see the DS92LV1260 datasheet for more specific details about the seventh redundant channel and further details. The SCAN921260 contains the same basic functions as the DS92LV1260. However, the SCAN921260 has an increased parallel clock rate up to 66MHz, is IEEE 1149.1 (JTAG) compliant and also contains at-speed Built-In-Self-Test (BIST). The SCAN926260 contains the same basic functions as the SCAN921260. However, in addition to a master powerdown, the SCAN926260 has individual powerdown pins per channel, has eliminated the seventh redundant channel, and now asserts all outputs ROUTn[0:9] and RCLKn high during powerdown and during loss of lock. Please also note that the LOCKn pin output is no longer affected by REN. Also, the SCAN926260 is footprint compatible and may be used interchangibly with the SCAN921260. USING NOISE MARGIN TO VALIDATE SIGNAL QUALITY The parameters tRNMI-LEFT and tRNMI-RIGHT are calculated by first measuring how much of the ideal bit the receiver needs to ensure correct sampling. After determining this amount, what remains of the ideal bit that is available for external sources of noise is called noise margin. Noise margin does not include transmitter jitter. Please see Figure 8 for a graphical explanation. Also, for a more detailed explanation of noise margin, please see Application Note 1217 titled "How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask." The vertical limits of the mask are determined by the SCAN926260 receiver input threshold of ±50mV. BYPASS Circuit board layout and stack-up for the BLVDS devices should be designed to provide noise-free power to the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power / ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 3X the power supply voltage being used. It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are recommended due to their smaller parasitics. 13 When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLL circuitry. Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) signals away from the LVDS lines to prevent coupling. Closely-coupled differential lines of 100 Ohms ZDIFF are typically recommended for LVDS interconnects. The closely-coupled lines help to ensure that coupled noise will appear as common-mode and is rejected by the receivers. Also, the tight coupled lines will radiate less. Termination of the LVDS interconnect is required. For pointto-point applications, termination should be located at the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver. Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the national web site at: www.national.com/lvds. For packaging information on BGA's, please see AN-1126. Guidance for the SCAN926260 is provided next: SCAN926260: SIX 1 TO 10 DESERIALIZERS General guidance is provided below. Exact guidance can not be given as it is dictated by other board level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated circuit power supply needs. DVDD = DIGITAL SECTION POWER SUPPLY These pins supply the digital portion and receiver output buffers of the device. Receiver DVDD pins require more bypass to power outputs under synchronous switching conditions. An estimate of local capacitance requires a minimum of 20nF. This is calculated by taking 66 (60 LVTTL Outputs + 6 RCLK Outputs) times the maximum output short circuit current (IOS) of 85mA. Multiplying this number by the maximum rise time (tCLH) of 4ns and dividing by the maximum allowed droop in VDD (assume 50mV) yields 448.8nF. Dividing this number by the number of DVDD pins (25) yields 18nF. Rounding up to a standard value, 0.1uF is selected for each DVDD pin. The capacitative bandwidth for this capacitor may be extended by placing a 0.01uF capacitor in parallel. The 0.01uF capacitor should be placed closer to the DVDD pin than the 0.1uF capacitor. PVDD = PLL SECTION POWER SUPPLY The PVDD pin supplies the PLL circuit. PLL circuits require clean power for the minimization of jitter. A supply noise frequency in the 300kHZ to 1MHz range can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is best to provide a stable VDD, suppression of the noise band, and good high-frequency response (clock fundamental). This may be accomplished with a pie filter www.national.com SCAN926260 (CRC or CLC). If employed, a separate pie filter is recommended for each PLL to minimize drop in potential due to the series resistance. Separate power planes for the PVDD pins is typically not required. AVDD = LVDS SECTION POWER SUPPLY The AVDD pin supplies the LVDS portion of the circuit. The SCAN926260 has four AVDD pins. Due to the nature of the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space is available, the 0.01uF capacitor may be used in parallel with the 0.1uF capacitor for additional high frequency filtering. GROUNDs The AGND pin should be connected to the signal common in the cable for the return path of any common-mode current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of current may be evenmode due to coupled noise and driver imbalances. This current should return via a low impedance known path. For a typical application circuit, please see Figure 10. 20028329 FIGURE 10. Typical Application Circuit (Only one power/ground for each supply type shown for clarity-bypass networks should be repeated for all power/ground pairs.) 20028327 FIGURE 11. Optional Additional External Failsafe Biasing www.national.com 14 SCAN926260 Pin Diagram Top View of SCAN926260TUF (196 pin LBGA) 20028314 Note: * = OVERBAR 15 www.national.com SCAN926260 Pin Descriptions Pin Name GND RINn± N/C Type GND Bus LVDS Input Pins B2, B14, L4, L5 A3-A4, A6-A7, A9-10, C5C6, C8-C9, C10-C11 E3 Description Ground pins for ESD structures. Bus LVDS differential input pins. Failsafe described in Application Information section. This pin is not bonded out. Therefore, you may tie this pin High, Low, or as a N/C. However, for board layout compatibility with the SCAN921260 or the DS92LV1260, tie this pin LOW. DVdd B1, B3, C4, D6, D12, E6, E7, E9, E10, F7, F10, F12, G6, G10, H6, H10, J5, J8, Supply voltage for digital section. J9, J10, K5, K6, K7, K10, L10 A1, D4, D5, D7, D9, D11, E5, E8, F5, F6, F8, F9, G5, Ground pins for digital section. G7, G8, G9, H5, H7, H8, H9, J6, J7, K8, K9, L7 E1, F1, F14, G14, J1, J14, Supply voltage for PLL circuitry. K1, K14,P5, P6, P9, P10 A14, B12, D10, G1, G2, G13, H1, H13, H14, J4, J13, Ground pins for PLL circuitry. N7, N8, P7, P8 A11, B6, B9, C7 A5, A8, B7, B8, B11 Supply voltage for analog circuitry. Ground pins for analog circuitry. A low on one of these pins puts the corresponding channel into sleep mode and a high makes the corresponding channel active. There is an internal pull-down on each of these pins that defaults the PWRDWNn input to sleep mode. Active operation requires asserting a high on the PWRDWNn and MS_PWRDWN input. A low on this pin puts the device into sleep mode and a high makes the part active. There is an internal pull-down that defaults the MS_PWRDWNn input to sleep mode. Active operation requires asserting a high on the MS_PWRDWNn input. Enables the ROUTn[0:9], RCLKn, outputs. There is an internal pull-down that defaults REN to TRI-STATE the outputs. Active outputs require asserting a high on REN. Please note that LOCKn is not affected by REN. Frequency reference input. Used by the PLL while locking onto incoming LVDS streams.Has no phase relation to RCLK. Indicates the status of the PLLs for the individual deserializers: LOCKn= L indicates locked, LOCKn= H indicates unlocked. DGND PVdd PGND AVdd AGND PWRDWN [0:5] 3.3V CMOS Input A12, A13, C3, C12, E11, F11 MS_PWRDWN 3.3V CMOS Input B5 REN 3.3V CMOS Input 3.3V CMOS Input 3.3V CMOS Output A2 REFCLK LOCK[0:5] B4 D13, F3, N3, P1, P12, P13 ROUTn[0:9] 3.3V CMOS Output E2, E4, E12, E13, E14, F4, G3, G4, G11, G12, H2, H3, H4, H11, H12, J2, J3, J11, J12, K2, K3, K4, K12, K13, Outputs for the ten bit deserializers; n = deserializer number. L1, L3, L6, L8, L9, L11, L12, When a channel is not locked, ROUT[0:9] are high for that L13, L14, M1, M2, M3, M4, channel. M5, M6, M7, M8, M9, M10, M11, M12, M14, N1, N2, N4, N6, N9, N11, N12, N13, N14, P2, P3, P4, P11, P14 F2, F13, L2, M13,N5, N10 Recovered clock for each deserializer's output data. When a channel is not locked, the RCLK for that channel is high. RCLK[0:5] 3.3V CMOS Output www.national.com 16 SCAN926260 Pin Name Type 3.3V CMOS Input 3.3V CMOS Input 3.3V CMOS Input 3.3V CMOS Input 3.3V CMOS Output 3.3V CMOS Input Pins Description Test Mode Select input to support IEEE 1149.1. There is a weak internal pull-up on TMS that defaults TRST, TDI, TCK and TDO to be inactive. However, in noisy environments, pulling TMS high ensures the JTAG test access port (TAP) is never activated. Test Reset Input to support IEEE 1149.1. There is a weak internal pull-up on this pin. Test Data Input to support IEEE 1149.1. There is a weak internal pull-up on this pin. Test Clock to support IEEE 1149.1 Test Data Output to support IEEE 1149.1. BIST Alone Error Reporting Mode Select Input. These pins control which channels are active for the BIST Alone operating mode. The BIST Alone Mode Selection Table describes their function. There are internal pull-ups that default all BIST_SEL[0:2] to high, which is the idle state for all channels in the BIST Alone mode. A high on this pin activates the BIST Alone operating mode. There is a weak internal pull-down that should default the BIST_ACT to de-activate the BIST Alone operating mode. In a noisy operating environment, it is recommended that an external pull down be used to ensure that BIST_ACT stays in the low state. Unused solder ball location. Do not connect. TMS C1 TRST TDI TCK TDO BISTMODE_REQ C2 D1 D2 D3 B10 BIST_SEL[0:2] 3.3V CMOS Input C14, D8, D14 BIST_ACT 3.3V CMOS Input K11 N/C B13, C13 17 www.national.com SCAN926260 Physical Dimensions inches (millimeters) unless otherwise noted Order Number SCAN926260TUF (Tray) Order Number SCAN926260TUFX (Tape and Reel) NS Package Number UJB196A www.national.com 18 SCAN926260 Notes 19 www.national.com SCAN926260 Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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