SCAN92LV090

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN February 2005 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is less than ± 100 mV over a ± 1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). Features IEEE 1149.1 (JTAG) Compliant Bus LVDS Signaling Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ± 100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin LQFP package and BGA package n High impedance Bus pins on power off (VCC = 0V) n n n n n n n n n n n n n Simplified Functional Diagram 10124201 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS101242 www.national.com SCAN92LV090 Connection Diagrams 10124202 Top View Order Number SCAN92LV090VEH See NS Package Number VEH064DB 10124216 Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A www.national.com 2 SCAN92LV090 Pinout Description Pin Name DO+/RI+ DO−/RI− DIN RO RE DE GND VCC AGND AVCC TRST TMS TCK TDI TDO TQFP Pin # 27, 31, 35, 37, 41, 45, 47, 51, 55 26, 30, 34, 36, 40, 44, 46, 50, 54 2, 6, 12, 18, 20, 22, 58, 60, 62 3, 7, 13, 19, 21, 23, 59, 61, 63 17 16 4, 5, 9, 14, 25, 56 10, 15, 24, 57, 64 28, 33, 43, 49, 53 29, 32, 42, 48, 52 39 38 1 8 11 BGA Pin # A7, B8, C6, D5, D8, E6, F7, G5, G6 B5, B6, C7, D6, E5, E8, F6, G8, H7 A2, A4, C3, C4, D2, E3, G3, G4, H3 A3, B3, C1, C2, D4, E4, F4, G1, H2 H1 G2 B1, B4, D3, E1, F2, H5 A1, A5, F1, F3, H4 A8, C5, D7, F5, G7 A6, B7, C8, H6, H8 F8 E7 B2 D1 E2 Input/Output I/O I/O I O I I Power Power Power Power I I I I O Descriptions True Bus LVDS Driver Outputs and Receiver Inputs. Complimentary Bus LVDS Driver Outputs and Receiver Inputs. TTL Driver Input. TTL Receiver Output. Receiver Enable TTL Input (Active Low). Driver Enable TTL Input (Active High). Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. Analog VCC (must connect to VCC on PC board). These pins connected internally. Test Reset Input to support IEEE 1149.1 (Active Low) Test Mode Select Input to support IEEE 1149.1 Test Clock Input to support IEEE 1149.1 Test Data Input to support IEEE 1149.1 Test Data Output to support IEEE 1149.1 3 www.national.com SCAN92LV090 Absolute Maximum Ratings (Notes 2, 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Enable Input Voltage (DE, RE) Driver Input Voltage (DIN) Receiver Output Voltage (ROUT) Bus Pin Voltage (DO/RI ± ) ESD (HBM 1.5 kΩ, 100 pF) Driver Short Circuit Duration Receiver Short Circuit Duration Maximum Package Power Dissipation at 25˚C LQFP Derate LQFP Package 1.74 W 13.9 mW/˚C −0.3V to (VCC +0.3V) −0.3V to +3.9V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) 4.0V θja θjc Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 sec.) 71.7˚C/W 10.9˚C/W +150˚C −65˚C to +150˚C 260˚C Recommended Operating Conditions Min Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature Maximum Input Edge Rate (Note 6)(20% to 80%) Data Control 1.0 3.0 3.0 0.0 −40 Max 3.6 2.4 +85 Units V V ˚C ∆t/∆V ns/V ns/V > 4.5 kV momentary momentary DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol VOD ∆VOD VOS ∆VOS VOH VOL IOSD VOH Parameter Output Differential Voltage VOD Magnitude Change Offset Voltage Offset Magnitude Change Driver Output High Voltage Driver Output Low Voltage Output Short Circuit Current (Note 10) Voltage Output High (Note 11) RL = 27Ω RL = 27Ω VOD = 0V, DE = VCC, Driver outputs shorted together VID = +300 mV Inputs Open Inputs Terminated, RL = 27Ω VOL IOD Voltage Output Low Receiver Output Dynamic Current (Note 10) Input Threshold High Input Threshold Low Receiver Common Mode Range Input Current DE = 0V, RE = 2.4V, VIN = +2.4V or 0V VCC = 0V, VIN = +2.4V or 0V IOL = 2.0 mA, VID = −300 mV VID = 300mV, VOUT = VCC−1.0V VID = −300mV, VOUT = 1.0V DE = 0V, VCM = 1.5V DO+/RI+, DO−/RI− −110 IOH = −400 µA ROUT VCC−0.2 VCC−0.2 VCC−0.2 0.05 |75| |75| 110 +100 −100 |VID|/2 2.4 − |VID|/2 0.075 1.1 1.3 5 1.4 0.95 1.1 |36| |65| Conditions RL = 27Ω, Figure 1 Pin DO+/RI+, DO−/RI− Min 240 Typ 300 Max 460 27 1.5 10 1.65 Units mV mV V mV V V mA V V V V mA mA mV mV V µA µA VTH VTL VCMR IIN −25 −20 ±1 ±1 +25 +20 www.national.com 4 SCAN92LV090 DC Electrical Characteristics Symbol VIH VIL IIH IIL VCL IIH Parameter Minimum Input High Voltage Maximum Input Low Voltage Input High Current Input Low Current Input Diode Clamp Voltage Input High Current (Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Conditions Pin DIN, DE, RE, TCK, TRST, TMS, TDI VIN = VCC or 2.4V VIN = GND or 0.4V ICLAMP = −18 mA VIN = VCC TDI, TMS, TCK, TRST TDI, TMS, TRST TCK VCC 50 80 mA DIN, DE, RE Min 2.0 GND −20 −20 −1.5 -20 Typ Max VCC 0.8 Units V V µA µA V +20 µA ± 10 ± 10 −0.8 +20 +20 IILR IIL ICCD Input Low Current Input Low Current Power Supply Current Drivers Enabled, Receivers Disabled Power Supply Current Drivers Disabled, Receivers Enabled Power Supply Current, Drivers and Receivers TRI-STATE ® Power Supply Current, Drivers and Receivers Enabled Power Supply Current (SCAN Test Mode), Drivers and Receivers Enabled Power Off Leakage Current Capacitance @ Bus Pins Capacitance @ ROUT VIN = GND, VCC = 3.6v VIN = GND No Load, DE = RE = VCC, DIN = VCC or GND DE = RE = 0V, VID = ± 300mV -25 -20 -115 +20 µA µA ICCR 50 DE = 0V; RE = VCC, DIN = VCC or GND DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω, TAP in any state other than Test-Logic-Reset VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) DO+/RI+, DO−/RI− DO+/RI+, DO−/RI− ROUT −20 80 mA ICCZ 50 80 mA ICC 160 210 mA ICCS 180 230 mA IOFF +20 µA COUTPUT COUTPUT 5 7 pF pF AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tTLH tTHL Parameter Differential Prop. Delay High to Low (Note 8) Differential Prop. Delay Low to High (Note 8) Differential Skew |tPHLD–tPLHD| (Note 9) Chip to Chip Skew (Note 12) Channel to Channel Skew (Note 13) Transition Time Low to High Transition Time High to Low 0.25 0.5 0.5 Conditions RL = 27Ω, Figure 2, Figure 3 CL = 10 pF Min 1.0 1.0 Typ 1.8 1.8 120 1.6 0.55 1.2 1.2 Max 2.6 2.6 Units ns ns ps ns ns ns ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS 5 www.national.com SCAN92LV090 AC Electrical Characteristics Symbol tPHZ tPLZ tPZH tPZL tPHLD tPLHD tSDK1 tSDK2 tSDK3 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX tS tH tS tH tW tW tREC Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Parameter Disable Time High to Z (Continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Conditions RL = 27Ω, Figure 4, Figure 5 CL = 10 pF Min Typ 3 3 3 3 Figure 6, Figure 7 CL = 35 pF 2.0 2.0 2.4 2.4 210 1.9 0.35 1.5 1.5 RL = 500Ω, Figure 8, Figure 9 CL = 35 pF 4.5 3.5 3.5 3.5 RL = 500Ω, CL = 35 pF 25.0 1.5 1.5 2.5 1.5 10.0 2.5 2.0 75.0 0.7 2.5 2.5 10 8 8 8 Max 8 8 8 8 3.9 3.9 Units ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS Differential Prop. Delay High to Low (Note 8) Differential Prop Delay Low to High (Note 8) Differential Skew |tPHLD–tPLHD| (Note 9) Chip to Chip Skew (Note 12) Channel to Channel skew (Note 13) Transition Time Low to High Transition Time High to Low Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum TCK Clock Frequency TDI to TCK, H or L TDI to TCK, H or L TMS to TCK, H or L TMS to TCK, H or L TCK Pulse Width, H or L TRST Pulse Width, L Recovery Time, TRST to TCK SCAN CIRCUITRY TIMING REQUIREMENTS Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ∆VOD and VID. Note 3: All typicals are given for VCC = +3.3V and TA = +25˚C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V. Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = < 1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs. Note 8: Propagation delays are guaranteed by design and characterization. Note 9: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. Note 11: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, common edge. www.national.com 6 SCAN92LV090 Applications Information General application guidelines and hints may be found in the following application notes: AN-808, AN-1108, AN-977, AN-971, and AN-903. There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. In addition, randomly distributed by-pass capacitors should be used. TABLE 1. Functional Table MODE SELECTED DRIVER MODE RECEIVER MODE TRI-STATE MODE LOOP BACK MODE DE H L L H RE H L H L TABLE 2. Transmitter Mode INPUTS DE H H H L DIN L H 0.8V < DIN < 2.0V X TABLE 3. Receiver Mode INPUTS RE L L L H (RI+) – (RI−) L ( < −100 mV) H ( > +100 mV) −100 mV < VID < +100 mV X L H X Z OUTPUT OUTPUTS DO+ L H X Z DO− H L X Z • Use the termination resistor which best matches the differential impedance of your transmission line. • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to < 0.5 inches. • Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION: • Use controlled impedance media. The backplane and connectors should have a matched differential impedance. X = High or Low logic state L = Low state Z = High impedance state H = High state Test Circuits and Timing Waveforms 10124203 FIGURE 1. Differential Driver DC Test Circuit 7 www.national.com SCAN92LV090 Test Circuits and Timing Waveforms (Continued) 10124204 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit 10124205 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms 10124206 FIGURE 4. Driver TRI-STATE Delay Test Circuit www.national.com 8 SCAN92LV090 Test Circuits and Timing Waveforms (Continued) 10124207 FIGURE 5. Driver TRI-STATE Delay Waveforms 10124208 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit 10124214 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms 10124215 FIGURE 8. Receiver TRI-STATE Delay Test Circuit 9 www.national.com SCAN92LV090 Test Circuits and Timing Waveforms (Continued) 10124211 FIGURE 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations 10124212 Bi-Directional Half-Duplex Point-to-Point Applications 10124213 Multi-Point Bus Applications www.national.com 10 SCAN92LV090 Description of Boundary-Scan Circuitry The SCAN92LV090 features two unique Scan test modes, each which requires a unique BSDL model depending on the level of test access and fault coverage goals. In the first mode (Mode0), only the TTL Inputs and Outputs of each transceiver are accessible via a 1149.1 compliant protocol. In the second mode (Mode1), the TTL Inputs and Outputs are accessible by a 1149.1 compliant method while the Differential I/O pins are accessible by a 1149.1 compatible technique which evaluates the signal integrity and modifies the data in the differential BSR as appropriate. All test modes are handled by the ATPG software, and BSDL selection should be invisible to the user. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 Instruction Register Scan Chain Definition 10124210 MSB → LSB (Mode0) Instruction Code 00000000 10000010 10000111 00000110 All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ BYPASS MSB → LSB (Mode1) Instruction Code 10011001 10010010 10001111 00000110 All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ BYPASS 10124209 The INSTRUCTION register is an eight-bit register which captures the value 00111101. 10124220 10124221 Mode 0 Boundary Scan Register Configuration Mode 1 Boundary Scan Register Configuration 11 www.national.com SCAN92LV090 Physical Dimensions unless otherwise noted inches (millimeters) 64-Lead Molded LQFP Package Order Number SCAN92LV090VEH NS Package Number VEH064DB 64-Lead Ball Grid Array Package Order Number SCAN92LV090SLC NS Package Number SLC64A www.national.com 12 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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