SCAN92LV090_06

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN December 2006 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V. The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ IEEE 1149.1 (JTAG) Compliant Bus LVDS Signaling Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin LQFP package and BGA package ■ High impedance Bus pins on power off (VCC = 0V) Simplified Functional Diagram 10124201 Connection Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 101242 www.national.com SCAN92LV090 10124202 Top View Order Number SCAN92LV090VEH See NS Package Number VEH064DB 10124216 Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A www.national.com 2 SCAN92LV090 Pinout Description Pin Name DO+/RI+ DO−/RI− DIN RO RE DE GND VCC AGND AVCC TRST TMS TCK TDI TDO TQFP Pin # BGA Pin # Input/Output I/O I/O I O I I Power Power Power Power I I I I O Descriptions True Bus LVDS Driver Outputs and Receiver Inputs. Complimentary Bus LVDS Driver Outputs and Receiver Inputs. TTL Driver Input. TTL Receiver Output. Receiver Enable TTL Input (Active Low). Driver Enable TTL Input (Active High). Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. Analog VCC (must connect to VCC on PC board). These pins connected internally. Test Reset Input to support IEEE 1149.1 (Active Low) Test Mode Select Input to support IEEE 1149.1 Test Clock Input to support IEEE 1149.1 Test Data Input to support IEEE 1149.1 Test Data Output to support IEEE 1149.1 27, 31, 35, 37, 41, 45, A7, B8, C6, D5, D8, E6, 47, 51, 55 F7, G5, G6 26, 30, 34, 36, 40, 44, B5, B6, C7, D6, E5, E8, 46, 50, 54 F6, G8, H7 2, 6, 12, 18, 20, 22, 58, A2, A4, C3, C4, D2, E3, 60, 62 G3, G4, H3 3, 7, 13, 19, 21, 23, 59, A3, B3, C1, C2, D4, E4, 61, 63 F4, G1, H2 17 16 4, 5, 9, 14, 25, 56 10, 15, 24, 57, 64 28, 33, 43, 49, 53 29, 32, 42, 48, 52 39 38 1 8 11 H1 G2 B1, B4, D3, E1, F2, H5 A1, A5, F1, F3, H4 A8, C5, D7, F5, G7 A6, B7, C8, H6, H8 F8 E7 B2 D1 E2 3 www.national.com SCAN92LV090 Absolute Maximum Ratings (Notes 2, 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Enable Input Voltage (DE, RE) Driver Input Voltage (DIN) Receiver Output Voltage (ROUT) Bus Pin Voltage (DO/RI±) 4.0V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to +3.9V  θjc Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 sec.) 10.9°C/W +150°C −65°C to +150°C 260°C Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature Maximum Input Edge Rate  (Note 6)(20% to 80%) Data Control Min 3.0 0.0 −40 Max 3.6 2.4 +85 Units V V °C Δt/ΔV ns/V ns/V ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C LQFP 1.74 W Derate LQFP Package 13.9 mW/°C  θja 71.7°C/W 1.0 3.0 DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol VOD ΔVOD VOS ΔVOS VOH VOL IOSD VOH Parameter Output Differential Voltage VOD Magnitude Change Offset Voltage Offset Magnitude Change Driver Output High Voltage RL = 27Ω Driver Output Low Voltage RL = 27Ω 0.95 Output Short Circuit Current VOD = 0V, DE = VCC, Driver outputs (Note 10) shorted together Voltage Output High (Note 11) VID = +300 mV Inputs Open Inputs Terminated, RL = 27Ω VOL IOD VTH VTL VCMR IIN Voltage Output Low Receiver Output Dynamic Current (Note 10) Input Threshold High Input Threshold Low Receiver Common Mode Range Input Current DE = 0V, RE = 2.4V, VIN = +2.4V or 0V VCC = 0V, VIN = +2.4V or 0V VIH VIL IIH IIL VCL Minimum Input High Voltage Maximum Input Low Voltage Input High Current Input Low Current VIN = VCC or 2.4V VIN = GND or 0.4V DIN, DE, RE, TCK, TRST, TMS, TDI DIN, DE, RE IOL = 2.0 mA, VID = −300 mV VID = 300mV, VOUT = VCC−1.0V VID = −300mV, VOUT = 1.0V DE = 0V, VCM = 1.5V DO+/RI+, DO−/RI− −100 |VID|/2 2.4 − | VID|/2 ±1 ±1 +25 +20 VCC 0.8 ±10 ±10 −0.8 +20 +20 −110 IOH = −400 µA ROUT VCC−0.2 VCC−0.2 VCC−0.2 0.05 |75| |75| 110 +100 0.075 Conditions RL = 27Ω, Figure 1 Pin DO+/RI+, DO−/RI− Min 240 1.1 Typ 300 1.3 5 1.4 1.1 |36| |65| Max 460 27 1.5 10 1.65 Units mV mV V mV V V mA V V V V mA mA mV mV V µA µA V V µA µA V −25 −20 2.0 GND −20 −20 −1.5 Input Diode Clamp Voltage ICLAMP = −18 mA www.national.com 4 SCAN92LV090 Symbol IIH IILR IIL ICCD Parameter Input High Current Input Low Current Input Low Current VIN = VCC Conditions Pin TDI, TMS, TCK, TRST TDI, TMS, TRST TCK VCC Min -20 -25 -20 Typ Max +20 -115 +20 Units µA µA µA mA VIN = GND, VCC = 3.6v VIN = GND Power Supply Current No Load, DE = RE = VCC, Drivers Enabled, Receivers DIN = VCC or GND Disabled Power Supply Current DE = RE = 0V, VID = ±300mV Drivers Disabled, Receivers Enabled Power Supply Current, DE = 0V; RE = VCC, Drivers and Receivers TRI- DIN = VCC or GND STATE® Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω 50 80 ICCR 50 80 mA ICCZ 50 80 mA ICC 160 210 mA ICCS Power Supply Current DE = VCC; RE = 0V, (SCAN Test Mode), Drivers DIN = VCC or GND, and Receivers Enabled RL = 27Ω, TAP in any state other than Test-Logic-Reset Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) Capacitance @ Bus Pins Capacitance @ ROUT DO+/RI+, DO−/RI− DO+/RI+, DO−/RI− ROUT −20 180 230 mA IOFF +20 µA COUTPUT COUTPUT 5 7 pF pF AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter Conditions Min Typ Max Unit s ns ns ps 1.6 0.25 0.5 0.5 RL = 27Ω, Figure 4, Figure 5 CL = 10 pF 3 3 3 3 0.55 1.2 1.2 8 8 8 8 ns ns ns ns ns ns ns ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD tPLHD tSKD1 tSKD2 tSKD3 tTLH tTHL tPHZ tPLZ tPZH tPZL Differential Prop. Delay High to Low (Note 8) Differential Prop. Delay Low to High (Note 8) Differential Skew |tPHLD–tPLHD| (Note 9) Chip to Chip Skew (Note 12) Channel to Channel Skew (Note 13) Transition Time Low to High Transition Time High to Low Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low RL = 27Ω, Figure 2, Figure 3 CL = 10 pF 1.0 1.0 1.8 1.8 120 2.6 2.6 DIFFERENTIAL RECEIVER TIMING REQUIREMENTS 5 www.national.com SCAN92LV090 Symbol tPHLD tPLHD tSDK1 tSDK2 tSDK3 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX tS tH tS tH tW tW tREC Parameter Differential Prop. Delay High to Low (Note 8) Differential Prop Delay Low to High (Note 8) Differential Skew |tPHLD–tPLHD| (Note 9) Chip to Chip Skew (Note 12) Channel to Channel skew (Note 13) Transition Time Low to High Transition Time High to Low Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum TCK Clock Frequency TDI to TCK, H or L TDI to TCK, H or L TMS to TCK, H or L TMS to TCK, H or L TCK Pulse Width, H or L TRST Pulse Width, L Recovery Time, TRST to TCK Conditions Figure 6, Figure 7 CL = 35 pF Min 2.0 2.0 Typ 2.4 2.4 210 Max 3.9 3.9 1.9 Unit s ns ns ps ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns 0.35 1.5 1.5 RL = 500Ω, Figure 8, Figure 9 CL = 35 pF 4.5 3.5 3.5 3.5 RL = 500Ω, CL = 35 pF 25.0 1.5 1.5 2.5 1.5 10.0 2.5 2.0 75.0 0.7 2.5 2.5 10 8 8 8 SCAN CIRCUITRY TIMING REQUIREMENTS Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. Note 3: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V. Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf =