SCANSTA476

SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor August 2005 SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor General Description The SCANSTA476 is a low power, Analog Voltage Monitor used for sampling or monitoring up to 8 analog/mixed-signal input channels. Analog Voltage Monitors are valuable during product development, environmental test, production, and field service for verifying and monitoring power supply and reference voltages. In a supervisory role, the ’STA476 is useful for card or system-level health monitoring and prognostics applications. Instead of requiring an external microcontroller with a GPIO interface, the ’STA476 features a common IEEE 1149.1 (JTAG) interface to select the analog input, initiate a measurement, and access the results - further extending the capabilities of an existing JTAG infrastructure. The SCANSTA476 uses the VREF input as a reference. This enables the SCANSTA476 to operate with a full-scale input range of 0 to VDD, which can range from +2.7V to +5.5V. The SCANSTA476 is packaged in a 16-lead non-pullback LLP package that provides an extremely small footprint for applications where space is a critical consideration. This product operates over the industrial temperature range of −40˚C to +85˚C. Features n n n n n n n Eight selectable Analog input channels Analog full-scale input range 0V to VDD Typical accuracy of 2 mV at maximum VDD Very low power operation Small package footprint in 16-lead, 5 x 5 x 0.8 mm LLP Single +2.7V to +5.5V supply operation IEEE 1149.1 (JTAG) compliant interface Applications Measurement of Point Voltages Real-time Signal Monitoring System Health Monitoring and Prognostics Debug, Environmental Test, Production Test, Field Service n Supplement In-Circuit Tester (ICT) access n Vital in Servers, Computing, Telecommunication and Industrial equipment n Essential in Medical, Data Storage, and Networking equipment n n n n Block Diagram 20083521 © 2005 National Semiconductor Corporation DS200835 www.national.com SCANSTA476 Connection Diagram 20083522 DAP = GND (Top View) Pin Descriptions Pin No. ANALOG I/O 16 15 14 13 12 11 10 9 2 A0 A1 A2 A3 A4 A5 A6 A7 VREF Analog input 0. This signal can range from 0V to VREF. Analog input 1. This signal can range from 0V to VREF. Analog input 2. This signal can range from 0V to VREF. Analog input 3. This signal can range from 0V to VREF. Analog input 4. This signal can range from 0V to VREF. Analog input 5. This signal can range from 0V to VREF. Analog input 6. This signal can range from 0V to VREF. Analog input 7. This signal can range from 0V to VREF. Analog reference voltage input. VREF must be ≤ VDD. This pin should be connected to a quiet source (not directly to VDD) and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the VREF pin. Test Data Input to support IEEE 1149.1 features Test Data Ouput to support IEEE 1149.1 features Test Mode Select to support IEEE 1149.1 features Test Clock to support IEEE 1149.1 features Test Reset to support IEEE 1149.1 features Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin. Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the LLP package. The DAP is used as the primary GND connection to the device. It should be connected to the ground plane with at least 4 vias for optimal low-noise and thermal performance. Symbol Description DIGITAL I/O 6 5 7 8 4 POWER SUPPLY 1,3 VDD TDI TDO TMS TCK TRST (Note 1) GND Note 1: Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package. www.national.com 2 SCANSTA476 Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage VDD Voltage on Any Analog Pin to GND Voltage on Any Digital Pin to GND Input Current at Any Pin (Note 4) ESD Susceptibility Human Body Model Machine Model Soldering Temperature −0.3V to +6.5V −0.3V to VDD+0.3V -0.3V to VDD+0.3V Junction Temperature Storage Temperature Thermal Resistance, θJA Thermal Resistance, θJC +150˚C −65˚C to +150˚C 42˚C/W 14.3˚C/W ± 10 mA 8000V > 250V Refer to AN-1187 Recommended Operating Conditions Operating Temperature Range VDD Supply Voltage Digital Input Pins Voltage Range Analog Input Pins Voltage Range (Note 5) −40˚C ≤ TA ≤ +85˚C +2.7V to +5.5V +0V to VDD +0V to VREF SCANSTA476 Electrical Characteristics The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted. Symbol Parameter Conditions Typical Limits 2.7 5.5 3.5 5.0 5.0 27.5 Units V (min) V (max) mA mA (max) mW (max) POWER SUPPLY CHARACTERISTICS VDD Supply Voltage Normal Mode (Static) IDD Normal Mode (Operational) Power Consumption, Normal Mode (Operational) Analog Input Range Reference Voltage Range DC Leakage Current Analog Input Measurement Accuracy VDD = +2.7V VDD = +5.5V VDD = +2.7V to +3.6V VDD = +5.5V VDD = +5V ICL = -18mA VIN = 0V or VDD TRST, TDI, TMS only IOH = -100 µA, 2.7V ≤ VDD ≤ 5.5V VOH Output High Voltage IOH = -4 mA, 3.0V ≤ VDD ≤ 5.5V IOH = -4 mA, VDD = 2.7V VOL IOS IOZ Output Low Voltage Output Short Circuit Current TRI-STATE Leakage Current Output Coding IOL = 100 µA, 2.7V ≤ VDD ≤ 5.5V IOL = 4 mA, 2.7V ≤ VDD ≤ 5.5V VOUT = 0V, VDD = 5.5V -0.8 0.2 0.1 1 2 −40˚C ≤ TA ≤ 85˚C VDD = +2.7V to +5.5V, VDD = +2.7V to +5.5V, fTCK = 1 MSPS VDD = +5.5V, fTCK = 1 MSPS PD ANALOG INPUT CHARACTERISTICS (A0-A7) VIN VREF IDCL VMEAS VREF ≤ VDD 0 to VREF VDD V V µA (max) mV ± 10 7.5 15 2.0 2.1 0.8 -1.5 DIGITAL INPUT CHARACTERISTICS (TDI, TMS, TCK, TRST) VIH VIL VCL IIN IILR Input High Voltage Input Low Voltage Input Clamp Voltage Input Current Input Current V (min) V (max) V (max) µA (max) µA (max) V (min) V (min) V (min) V (max) V (max) mA (max) µA (max) ± 10 -300 VDD −0.2 2.4 2.2 0.2 0.4 -85 DIGITAL OUTPUT CHARACTERISTICS (TDO) ± 10 Straight (Natural) Binary 3 www.national.com SCANSTA476 SCANSTA476 Electrical Characteristics Symbol Parameter AC ELECTRICAL CHARACTERISTICS FMAX Throughput Rate TCK = 20MHz (Continued) The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted. Conditions Typical Limits Units MSPS (max) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) MHz (min) 1 INPUT TIMING CHARACTERISTICS tSET tHOLD tSET tHOLD tW tREC tW FMAX TDI to TCK (H/L) TDI to TCK (H/L) TMS to TCK (H/L) TMS to TCK (H/L) TCK Pulse Width (H/L) Recovery TIme TRST to TCK TRST Pulse Width (L) TCK (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) 2.0 1.5 2.0 2.0 10.0 2.0 2.5 20 Note 2: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may affect device reliability. Note 3: Data sheet min/max specification limits are guaranteed by design or statistical analysis. Note 4: Except power supply pins. Note 5: For valid measurements, the analog VIN < VREF ≤ VDD. Applications Information POWER-UP TIMING The SCANSTA476 typically requires 1 µs to power up , either after first applying VDD, or after an incomplete conversion shift. To return to normal, one "dummy" conversion must be fully completed. After this first dummy conversion, the SCANSTA476 will perform conversions properly. STARTUP MODE When the VDD supply is first applied, the SCANSTA476 requires one dummy conversion after start-up. www.national.com 4 Timing Diagrams Instruction Shift (Channel Select) SCANSTA476 5 20083532 Op-codes 40h to 47h select pins A0 to A7 respectively. Note the JTAG reset preamble places the JTAG TAP controller in a stable state (RTI). Both the instruction and data shifts start in - and return to - the RTI state. www.national.com SCANSTA476 (Continued) Data Shift (A/D Sample) www.national.com 20083533 Timing Diagrams 6 D11 through D0 correspond to the 12-bit sample from the ADC Core. Note that Data shifts can be run back-to-back for continous sampling of a single channel, or can be interleaved with instruction shifts for rippling through all 8 channels. SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor Physical Dimensions inches (millimeters) unless otherwise noted LLP, Plastic, Dual Order Number SCANSTA476TSD, NS Package Number SDA16A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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