TMS417409A

TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 D D D This data sheet is applicable to all TMS41x409As and TMS42x409As symbolized by Revision “B”, Revision “E”, and subsequent revisions as described in the device symbolization section. Organization . . . 4 194 304 × 4 Single Power Supply (5 V or 3.3 V) Performance Ranges: ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns EDO CYCLE tHPC MIN 20 ns 25 ns 30 ns 20 ns 25 ns 30 ns DJ/DGA PACKAGES ( TOP VIEW ) VCC DQ1 DQ2 W RAS A11† A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS D D D D D ’41x409A-50 ’41x409A-60 ’41x409A-70 ’42x409A-50 ’42x409A-60 ’42x409A-70 D Extended-Data-Out (EDO) Operation CAS-Before-RAS ( CBR) Refresh Low Power Dissipation 3-State Unlatched Output High-Reliability Plastic 24 / 26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 24/26-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix) Operating Free-Air Temperature Range 0°C to 70°C PIN NOMENCLATURE A0 – A11† DQ1 – DQ4 CAS NC OE RAS VCC VSS W Address Inputs Data In / Data Out Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe 5-V or 3.3-V Supply‡ Ground Write Enable † A11 is NC for TMS417409A and TMS427409A. ‡ See Available Options Table AVAILABLE OPTIONS description DEVICE The TMS41x409A and TMS42x409A series are 16 777 216-bit dynamic random-access memory (DRAM) devices organized as 4 194 304 words of four bits each. These devices feature maximum RAS access times of 50, 60, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. POWER SUPPLY 5V 5V 3.3 V 3.3 V SELF REFRESH, BATTERY BACKUP – – – – REFRESH CYCLES 4 096 in 64 ms 2 048 in 32 ms 4 096 in 64 ms 2 048 in 32 ms TMS416409A TMS417409A TMS426409A TMS427409A The TMS416409A and TMS417409A are offered in a 24 / 26-lead plastic surface-mount SOJ package (DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ package (DJ suffix) and a 24 / 26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 logic symbol (TMS416409A and TMS426409A)† A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 9 10 11 12 15 16 17 18 19 21 8 6 RAM 4096 K × 4 20D10/21D0 A 0 4 194 303 20D19/21D9 20D20 20D21 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 & 23,21D G25 A,22D 26 23C22 24,25 EN RAS 5 CAS W OE DQ1 DQ2 DQ3 DQ4 23 4 22 2 3 24 25 A,Z26 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 logic symbol (TMS417409A and TMS427409A)† A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 9 10 11 12 15 16 17 18 19 21 8 20D21/21D10 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 & 23,21D G25 A,22D 26 23C22 24,25 EN RAM 4096 K × 4 20D11/21D0 A 0 4 194 303 RAS 5 CAS W OE DQ1 DQ2 DQ3 DQ4 23 4 22 2 3 24 25 A,Z26 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 functional block diagram TMS416409A, TMS426409A RAS CAS W OE Timing and Control A0 A1 ColumnAddress Buffers† A11 10 Column Decode Sense Amplifiers R o w D e c o d e 12 256K Array 256K Array 4 64 I/O Buffers DataOut Reg. DQ1 – DQ4 4 DataIn Reg. 4 4 RowAddress Buffers 12 256K Array † Column addresses A10 and A11 are not used. TMS417409A, TMS427409A RAS CAS W OE Timing and Control A0 A1 ColumnAddress Buffers A10 11 Column Decode Sense Amplifiers 256K Array R 256K Array 256K Array o 256K Array w 32 D e c o d 256K Array e 256K Array 11 32 4 DataIn Reg. I/O Buffers DataOut Reg. DQ1 – DQ4 4 4 4 RowAddress Buffers 11 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 operation extended data out Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup and hold and for address multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the maximum RAS low time. Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO operation benefit. address: A0 – A11 ( TMS416409A and TMS426409A) and A0 – A10 (TMS417409A and TMS427409A) Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. output enable (OE) OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time. The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions on OE until CAS falls again (see Figure 8). write enable ( W ) The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high (see Figure 9). data in / data out (DQ1 – DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge. The DQs drive valid data after all access times are met and remain valid except in cases described in the W and OE sections. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 RAS-only refresh TMS416409A, TMS426409A A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. TMS417409A, TMS427409A A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS-before-RAS ( CBR) refresh CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh ( RAS-only or CBR ) cycle. test mode The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed. In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced by a factor of four for this series. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 test mode (continued) Exit Cycle Entry Cycle RAS Test Mode Cycle Normal Mode CAS W NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode. Figure 1. Test-Mode Cycle POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (TMS41x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Supply voltage range, VCC (TMS42x409A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Voltage range on any pin (TMS41x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (TMS42x409A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions TMS41x409A MIN VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage Low-level input voltage (see Note 2) 2.4 –1 4.5 NOM 5 0 6.5 0.8 2 – 0.3 MAX 5.5 MIN 3 TMS42x409A NOM 3.3 0 VCC + 0.3 0.8 MAX 3.6 UNIT V V V V TA Operating free-air temperature 0 70 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TMS416409A PARAMETER VOH VOL II IO ICC1‡§ High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS† CONDITIONS IOH = – 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle ’416409A - 50 MIN 2.4 0.4 ± 10 ± 10 100 MAX ’416409A - 60 MIN 2.4 0.4 ± 10 ± 10 80 MAX ’416409 A- 70 MIN 2.4 0.4 ± 10 ± 10 70 MAX UNIT V V µA µA mA ICC2 Average standby g y current VIH = 2.4 V ( TTL), After one memory cycle, RAS and CAS high VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tHPC = MIN, CAS cycling 2 2 2 mA 1 1 1 mA ICC3‡§ Average refresh current (RAS-only refresh or CBR) Average EDO current 100 80 70 mA ICC4‡¶ 100 90 80 mA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS417409A PARAMETER VOH VOL II IO ICC1‡§ High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS† CONDITIONS IOH = – 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle ’417409 A- 50 MIN 2.4 0.4 ± 10 ± 10 130 MAX ’417409A - 60 MIN 2.4 0.4 ± 10 ± 10 110 MAX ’417409A - 70 MIN 2.4 0.4 ± 10 ± 10 100 MAX UNIT V V µA µA mA ICC2 Average standby g y current VIH = 2.4 V ( TTL), After one memory cycle, RAS and CAS high VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tHPC = MIN, CAS cycling 2 2 2 mA 1 1 1 mA ICC3‡§ ICC4‡¶ Average refresh current (RAS-only refresh or CBR) Average EDO current 130 110 100 mA 110 90 80 mA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS426409A PARAMETER High-level output output voltage Low-level output output voltage Input current (leakage) Output current (leakage) Average read- or write- cycle current TEST CONDITIONS† CONDITIONS IOH = – 2 mA IOH = – 100 µA IOL = 2 mA IOL = 100 µA LVTTL LVCMOS LVTTL LVCMOS ’426409A - 50 MIN 2.4 VCC – 0.2 0.4 0.2 ± 10 ± 10 MAX ’426409A -60 MIN 2.4 VCC – 0.2 0.4 0.2 ± 10 ± 10 MAX ’426409A - 70 MIN 2.4 V VCC – 0.2 0.4 V 0.2 ± 10 ± 10 µA µA MAX UNIT VOH VOL II IO VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VCC = 3.6 V, CAS high VO = 0 V to VCC, ICC1‡§ VCC = 3.6 V, Minimum cycle 90 70 60 mA ICC2 Average standby standby current VIH = 2 V (LVTTL) After one memory cycle, RAS and CAS high VIH = VCC – 0.2 V (LVCMOS), After one memory cycle, RAS and CAS high VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) VCC = 3.6 V, RAS low, tHPC = MIN, CAS cycling 2 2 2 mA 1 1 1 mA ICC3‡§ Average refresh current (RAS-only refresh or CBR) Average EDO current 90 70 60 mA ICC4‡¶ 100 90 80 mA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS427409A PARAMETER High-level output output voltage Low-level output output voltage Input current (leakage) Output current (leakage) Average read- or write- cycle current TEST CONDITIONS† CONDITIONS IOH = – 2 mA IOH = – 100 µA IOL = 2 mA IOL = 100 µA LVTTL LVCMOS LVTTL LVCMOS ’427409A - 50 MIN 2.4 VCC – 0.2 0.4 0.2 ± 10 ± 10 MAX ’427409A -60 MIN 2.4 VCC – 0.2 0.4 0.2 ± 10 ± 10 MAX ’427409A - 70 MIN 2.4 V VCC – 0.2 0.4 V 0.2 ± 10 ± 10 µA µA MAX UNIT VOH VOL II IO VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VCC = 3.6 V, CAS high VO = 0 V to VCC, ICC1‡§ VCC = 3.6 V, Minimum cycle 120 100 90 mA ICC2 Average standby standby current VIH = 2 V (LVTTL) After one memory cycle, RAS and CAS high VIH = VCC – 0.2 V (LVCMOS), After one memory cycle, RAS and CAS high VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) VCC = 3.6 V, RAS low, tHPC = MIN, CAS cycling 2 2 2 mA 1 1 1 mA ICC3‡§ Average refresh current (RAS-only refresh or CBR) Average EDO current 120 100 90 mA ICC4‡¶ 110 90 80 mA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER Ci(A) Ci(OE) Ci(RC) Ci(W) Input capacitance, A0 – A11† Input capacitance, OE Input capacitance, CAS and RAS Input capacitance, W Output capacitance‡ MIN MAX 5 7 7 7 7 UNIT pF pF pF pF pF Co † A11 is NC (no internal connection) for TMS417409A and TMS427409A. ‡ CAS and OE = VIH to disable outputs NOTE 3: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4) PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tREZ tCEZ tOEZ tWEZ Access time from column address (see Note 5) Access time from CAS (see Note 5) Access time from CAS precharge (see Note 5) Access time from RAS (see Note 5) Access time from OE (see Note 5) Delay time, CAS to output in low impedance Output buffer turn off delay from RAS (see Note 6) Output buffer turn off delay from CAS (see Note 6) Output buffer turn off delay from OE (see Note 6) Output buffer turn off delay from W (see Note 6) 0 3 3 3 3 13 13 13 13 ’41x409A-50 ’42x409A-50 MIN MAX 25 13 28 50 13 0 3 3 3 3 15 15 15 15 ’41x409A-60 ’42x409A-60 MIN MAX 30 15 35 60 15 0 3 3 3 3 18 18 18 18 ’41x409A-70 ’42x409A-70 MIN MAX 35 18 40 70 18 ns ns ns ns ns ns ns ns ns ns UNIT NOTES: 4. With ac parameters, it is assumed that tT = 2 ns. 5. For TMS42x409A, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 6. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven. Data in should not be driven until one of the applicable maximum specifications is satisfied. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) ’41x409A-50 ’42x409A-50 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tOCH tCP tOEP Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RAS active to CAS precharge Hold time, OE from CAS Hold time, output from CAS Pulse duration, CAS active (see Note 7) Pulse duration, W active (output disable only) Setup time, OE before CAS Pulse duration, CAS precharge Precharge time, OE 20 57 40 7 5 8 7 8 8 5 10 000 MAX ’41x409A-60 ’42x409A-60 MIN 25 68 48 10 5 10 7 10 10 5 10 000 MAX ’41x409A-70 ’42x409A-70 MIN 30 78 58 10 5 12 7 10 10 5 10 000 MAX ns ns ns ns ns ns ns ns ns ns UNIT NOTES: 4: With ac parameters, it is assumed that tT = 2 ns. 7. In a read-write cycle, tCWD and tCWL must be observed. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) ’41x409A-50 ’42x409A-50 MIN tRC tRWC tRASP tRAS tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tWTS tCSR tCAH tDH tRAH tRCH tRRH tWCH tROH tWRH tWTH tCHR tOEH tRHCP Cycle time, random read or write Cycle time, read-write Pulse duration, RAS active, fast page mode (see Note 8) Pulse duration, RAS active, non-page mode (see Note 8) Pulse duration, RAS precharge Pulse duration, write command Setup time, column address Setup time, row address Setup time, data in (see Note 9) Setup time, read command Setup time, write command before CAS precharge Setup time, write command before RAS precharge Setup time, write command before CAS active (early-write only) Setup time, W high before RAS low (CBR refresh only) Setup time, W low before RAS low (test mode only) Setup time, CAS referenced to RAS ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 9) Hold time, row address Hold time, read command referenced to CAS (see Note 10) Hold time, read command referenced to RAS (see Note 10) Hold time, write command during CAS active ( early-write only ) Hold time, RAS referenced to OE Hold time, W high after RAS low (CBR refresh) Hold time, W low after RAS low (test mode only) Hold time, CAS referenced to RAS ( CBR refresh only ) Hold time, OE command Hold time, RAS active from CAS precharge With ac parameters, it is assumed that tT = 2 ns. In a read-write cycle, tRWD and tRWL must be observed. Referenced to the later of CAS or W in write operations Either tRRH or tRCH must be satisfied for a read cycle. 84 111 50 50 30 8 0 0 0 0 8 8 0 10 10 5 8 8 8 0 0 8 8 10 10 10 13 28 100 000 10 000 MAX ’41x409A-60 ’42x409A-60 MIN 104 135 60 60 40 10 0 0 0 0 10 10 0 10 10 5 10 10 10 0 0 10 10 10 10 10 15 35 100 000 10 000 MAX ’41x409A-70 ’42x409A-70 MIN 124 160 70 70 50 10 0 0 0 0 12 12 0 10 10 5 12 12 10 0 0 12 10 10 10 10 18 40 100 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT NOTES: 4. 8. 9. 10. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) (continued) ’41x409A-50 ’42x409A-50 MIN tAWD tCPW tCRP tCWD tOED tRAD tRAL tCAL tRCD tRPC tRSH tRWD tTAA tTCPA tTRAC tT tREF Delay time, column address to write command ( read-write only ) Delay time, W low after xCAS precharge (read-write only) Delay time, CAS precharge to RAS Delay time, CAS to write command ( read-write only ) Delay time, OE to data in Delay time, RAS to column address (see Note 11) Delay time, column address to RAS precharge Delay time, column address to CAS precharge Delay time, RAS to CAS ( see Note 11) Delay time, RAS precharge to CAS Delay time, CAS active to RAS precharge Delay time, RAS to write command (read-write only) Access time from address (test mode) Access time, from column precharge (test mode) Access time, from RAS (test mode) Transition time ’4x6409A Refresh time interval time interval ’4x7409A 32 32 32 ms 42 45 5 30 13 10 25 18 12 5 8 67 30 35 55 2 30 64 37 25 MAX ’41x409A-60 ’42x409A-60 MIN 49 54 5 34 15 12 30 20 14 5 10 79 35 40 65 2 30 64 45 30 MAX ’41x409A-70 ’42x409A-70 MIN 57 62 5 40 18 12 35 25 14 5 12 92 40 45 75 2 30 64 52 35 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms UNIT NOTES: 4. With ac parameters, it is assumed that tT = 2 ns. 11. The maximum value is specified only to ensure access time. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION VTH RL Output Under Test CL = 100 pF (see Note A) Output Under Test CL = 100 pF (see Note A) R2 VCC R1 (a) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. DEVICE ’41x409A ’42x409A VCC (V) 5 3.3 R1 (W) 828 1178 R2 (W) 295 868 (b) ALTERNATE LOAD CIRCUIT VTH (V) 1.31 1.4 RL (W) 218 500 Figure 2. Load Circuits for Timing Parameters POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tT tCSH tRCD tRSH tCRP CAS tASR tRAD tASC tRAH tCAL tRAL Column tRCS tCAH W Don’t Care tCAC tAA DQ1 – DQ4 Hi-Z See Note A tCLZ tRAC tOEA tROH OE Don’t Care Don’t Care tCEZ tREZ Valid Data Out tWEZ tWPE tOEZ Don’t Care tRRH tRCH Don’t Care tCAS tCP tRP Address Row NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 3. Read-Cycle Timing 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tT tRCD tCSH CAS tASR tASC tCAL tRAH tRAL tCAH tCAS tRSH tCRP tRP tCP Address Row tRAD Column tCWL tRWL tWCH tWCS Don’t Care W Don’t Care Don’t Care tDH tDS DQ1 – DQ4 Valid Data Don’t Care OE Don’t Care Figure 4. Early-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tRP tT tRCD tCAS tCSH CAS tASR tASC tRAL tRAH tCAL tCAH Address Row Column tCWL tRAD tDS tRWL Don’t Care Don’t Care tRSH tCRP tCP W Don’t Care tWP tCLZ DQ1 – DQ4 Invalid Data Out tOED tOEH OE Don’t Care Don’t Care Valid Data In tDH Don’t Care Figure 5. Write-Cycle Timing 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRWC RAS tT tRCD CAS tASR tRAH tRAD tCAH tASC Column tRCS tRWD W tAWD tCWD tCAC tAA tCLZ DQ1 – DQ4 Hi-Z See Note A tRAC tOEA tOED OE Don’t Care Data Out tOEZ tOEH Don’t Care Data In tDS tDH Don’t Care Don’t Care tCWL tRWL tWP Don’t Care tT tCAS tCP tCRP tRAS tRP Address Row NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRASP RAS tRHCP tRSH tCSH tHPC tCAS CAS tRAH tASC tASR tCAH tCAL tRAL tCP tCRP tRP tT tRCD Address Row Column #1 Column #2 Column #3 tRAD tOEA OE tRCH tRCS tCAC tDOH tRRH W tAA tRAC tCLZ DQ1 – DQ4 See Note A tCAC tAA tCPA tREZ Data #1 Data #2 Data #3 tCEZ See Note C NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. Access time is tCPA-, tAA-, or tCAC-dependent. C. Output is turned off by tCEZ if RAS goes high during CAS low. Figure 7. EDO Read Cycle 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRP RAS tCSH tRASP tRHCP tCP tRSH tHPC tCAS CAS tASR tRAH tASC tCAH tCAL tRAL Column #2 Column #3 Address tRAD Row Column #1 tOCH tCHO tOEP tOEP OE tOEA tRCS tOEA tCAC tRRH tRCH W tCLZ tCAC tAA tRAC DQ1 – DQ4 Data #1 tOEZ tDOH tOEZ tCPA tREZ tAA Data #1 Data #2 Data #3 tCEZ See Note A NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low. Figure 8. EDO Read-Cycle With OE Control POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION RAS tCSH tHPC tCAS CAS tASR tRAH tASC Address Row tRAD OE tOEA tRCS tWPE tCAC tRCH tRRH W tCAC tAA tCLZ tRAC DQ1 – DQ4 Data #1 tCPA tAA tWEZ tCAC Column #1 tCAH tCAL Column #2 tRAL tRASP tRP tCRP tRHCP tRSH tCP Column #3 tDOH tCPA tAA tCEZ tREZ Data #2 Data #3 Figure 9. EDO Read-Cycle With W Control 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRASP RAS tCSH tRCD tASC tRAH tCP tCAH tASR Address Row Column tCWL tRAD tWCH tWCS W Don’t Care Don’t Care tDH tDS DQ1 – DQ4 Data In Data In Don’t Care Don’t Care tRAL tCAL Column tCWL tRWL Don’t Care tCAS tRHCP tHPC tRSH tRP tCRP CAS OE Don’t Care NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 10. EDO Early-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tCSH tRCD tCAL CAS tRAH tASR Address Row tRAD tCAH Column tASC tCAS tCP tRAL Column tCWL tRWL Don’t Care tRHCP tHPC tRSH tCRP tCWL tDS tWP W Don’t Care Don’t Care Don’t Care tDH DQ1 – DQ4 Don’t Care Valid Data In Invalid Data out tOEH OE tOED Don’t Care tOEH tCLZ Valid In Don’t Care Don’t Care NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 11. EDO Write-Cycle Timing 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRP RAS tCSH tPRWC tRCD CAS tASR tASC tCAH tRAD Address tRAH tCWD tAWD tRWD W tRCS tAA tRAC tCAC DQ1 – DQ4 tCLZ tOEA Valid Out 1 tOEZ OE NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated. tOEH tDS Valid In 1 tCPA tDH Valid Out 2 (see Note A) Valid In 2 tOED tOEH tWP tCPW tRWL Row Column 1 Column 2 tCAS tCAL tRAL Don’t Care tCWL tCP tRASP tRSH tCRP Figure 12. EDO Read-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tCRP tT tRPC tRAH tASR tRP CAS Don’t Care Address Don’t Care Row Don’t Care Row W Don’t Care DQ1 – DQ4 Hi Z OE Don’t Care Figure 13. RAS-Only Refresh-Cycle Timing 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRP tRAS RAS tCSR tT tWRP W tWRH tRPC CAS tCHR Address Don’t Care OE Don’t Care DQ1 – DQ4 Hi-Z Figure 14. Automatic-CBR-Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION Refresh Cycle Memory Cycle tRP tRAS RAS tCHR tCAS CAS tCAH tASC tRAH tASR Address Row Col Don’t Care tWRH tRRH tRCS W tCAC tAA DQ1 – DQ4 tCLZ tOEA OE Valid Data Out tOEZ tRAC tWEZ tREZ tCEZ tWRP tWRH tWRP tWRP tWRH tRAS Refresh Cycle tRP Figure 15. Hidden-Refresh-Cycle (Read) Timing 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION Memory Cycle tRAS RAS tCHR tCAS CAS tCAH tASC tRAH tASR Address Row Col tWRH tWCS tWP W tWCH tDS DQ1 – DQ4 Valid Data tDH tWRP Don’t Care tRP Refresh Cycle Refresh Cycle tRAS tRP Don’t Care OE Don’t Care Figure 16. Hidden-Refresh-Cycle (Write) Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION tRC tRP RAS tRAS tCSR tRPC CAS tWTS W tT tWTH Don’t Care tCHR Address Don’t Care OE Don’t Care DQ1 – DQ4 Hi-Z Figure 17. Test-Mode-Entry-Cycle Timing tRC tRP RAS tCSR tRPC tCHR tT CAS tWRP tRAS W Don’t Care tWRH Don’t Care Address tREZ tCEZ DQ1 – DQ4 Don’t Care Don’t Care Hi-Z Figure 18. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 MECHANICAL DATA DJ (R-PDSO-J24/26) 0.680 (17,27) 0.670 (17,02) 26 21 19 14 PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 0.340 (8,64) 0.330 (8,38) 0.305 (7,75) 0.295 (7,49) 1 6 8 0.032 (0,81) 0.026 (0,66) 13 0.148 (3,76) 0.128 (3,25) 0.106 (2,69) TYP 0.008 (0,20) NOM Seating Plane 0.020 (0,51) 0.016 (0,41) 0.050 (1,27) 4040092-3 / B 02/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). 0.004 (0,10) 0.007 (0,18) M 0.275 (6,99) 0.260 (6,60) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 MECHANICAL DATA DGA (R-PDSO-G24/26) 0.020 (0,50) 0.012 (0,30) 14 PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 26 0.008 (0,21) M 0.371 (9,42) 0.355 (9,02) 0.304 (7,72) 0.296 (7,52) 0.006 (0,15) NOM 1 0.679 (17,24) 0.671 (17,04) 13 Gage Plane 0.010 (0,25) 0°– 5° 0.024 (0,60) 0.016 (0,40) Seating Plane 0.047 (1,19) MAX 0.002 (0,05) MIN 0.004 (0,10) 4040265-3 / C 11/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 device symbolization (TMS416409A illustrated) TI -SS Speed ( - 50, - 60, - 70) TMS416409A DJ Package Code W E Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS416409A, TMS417409A, TMS426409A, TMS427409A 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. 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