TP3040

TP3040 TP3040A PCM Monolithic Filter September 1994 TP3040 TP3040A PCM Monolithic Filter General Description The TP3040 TP3040A filter is a monolithic circuit containing both transmit and receive filters specifically designed for PCM CODEC filtering applications in 8 kHz sampled systems The filter is manufactured using microCMOS technology and switched capacitor integrators are used to simulate classical LC ladder filters which exhibit low component sensitivity TRANSMIT FILTER STAGE The transmit filter is a fifth order elliptic low pass filter in series with a fourth order Chebyshev high pass filter It provides a flat response in the passband and rejection of signals below 200 Hz and above 3 4 kHz RECEIVE FILTER STAGE The receive filter is a fifth order elliptic low pass filter designed to reconstruct the voice signal from the decoded demultiplexed signal which as a result of the sampling process is a stair-step signal having the inherent sin x x frequency response The receive filter approximates the function required to compensate for the degraded frequency response and restore the flat passband response Features Y Y Y Y Y Y Y Y Y Y Designed for D3 D4 and CCITT applications a 5V b 5V power supplies Low power consumption 45 mW (0 dBm0 into 600X) 30 mW (power amps disabled) Power down mode 0 5 mW 20 dB gain adjust range No external anti-aliasing components Sin x x correction in receive filter 50 60 Hz rejection in transmit filter TTL and CMOS compatible logic All inputs protected against static discharge due to handling Block Diagram TL H 6660 – 1 FIGURE 1 C1995 National Semiconductor Corporation TL H 6660 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltages Power Dissipation Input Voltage Voltage at Any Input or Output g 7V Output Short-Circuit Duration Operating Temperature Range Storage Temperature Lead Temperature (Soldering 10 seconds) ESD Rating to be determined Continuous b 25 C to a 125 C b 65 C to a 150 C 1 W Package g 7V VCC a 0 3V to VBBV b 0 3V 300 C DC Electrical Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e a 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e a 5 0V VBB e b5 0V TA e 25 C Clock frequency is 2 048 MHz Digital interface voltages measured with respect to digital ground GNDD Analog voltages measured with respect to analog ground GNDA Symbol POWER DISSIPATION ICC0 VCC Standby Current VCC e 5 25V VBB e b5 25V CLK0 and PWRI e b5 25V (Note 6) All other pins at GND (0V) TP3040 TP3040A VCC e 5 25V VBB e b5 25V CLK0 and PWRI e b5 25V (Note 6) All other pins at GND (0V) TP3040 TP3040A PWRI e VBB Power Amp Inactive PWRI e VBB Power Amp Inactive (Note 1) (Note 1) VBB s VIN s VCC VBB s VIN s VCC VBB s VIN s VCC b 0 5V b 10 b 100 b 10 b0 1 Parameter Conditions Min Typ Max Units 50 100 mA IBB0 VBB Standby Current 50 100 mA ICC1 IBB1 ICC2 IBB2 IINC IINP IIN0 VIL VIH VIL0 VII0 VIH0 IBxI RIxI VOSxI VCM CMRR PSRR ROL RL CL VOxI AVOL Fc VCC Operating Current VBB Operating Current VCC Operating Current VBB Operating Current Input Current CLK Input Current PDN Input Current CLK0 Input Low Voltage CLK PDN Input High Voltage CLK PDN Input Low Voltage CLK0 Input Intermediate Voltage CLK0 Input High Voltage CLK0 Input Leakage Current VFxI Input Resistance VFxI Input Offset Voltage VFxI Common-Mode Range VFxI Common-Mode Rejection Ratio Power Supply Rejection of VCC or VBB Open Loop Output Resistance GSx Minimum Load Resistance GSx Maximum Load Capacitance GSx Output Voltage Swing GSx Open Loop Voltage Gain GSx Open Loop Unity Gain Bandwidth GSx 30 30 46 46 40 40 64 64 mA mA mA mA mA mA mA V V V V V nA MX mV V dB dB DIGITAL INTERFACE 10 0 22 VBB b0 8 08 VCC VBB a 0 5 08 VCC 100 VCCb0 5 b 3 2V s VIN s a 3 2V b 100 TRANSMIT INPUT OP AMP VBB s VFxI s VCC b 2 5V s VIN s a 2 5V b 2 5V s VIN s 2 5V 10 b 20 b2 5 20 25 60 60 1 10 100 kX kX pF V VV RL t 10k RL t 10k g2 5 5 000 2 MHz 2 AC Electrical Characteristics Unless otherwise specified TA e 25 C All parameters are specified for a signal level of 0 dBm0 at 1 kHz The 0 dBm0 level is assumed to be 1 54 Vrms measured at the output of the transmit or receive filter Limits printed in BOLD characters are guaranteed for VCC e a 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e a 5 0V VBB e b5 0V TA e 25 C Symbol Parameter Conditions Min Typ Max Units TRANSMIT FILTER (Transmit filter input op amp set to the non-inverting unity gain mode with VFxI e 1 09 Vrms unless otherwise noted ) RLx CLx ROx PSRR1 PSRR2 GAx GRx Minimum Load Resistance VFxO Load Capacitance VFxO Output Resistance VFxO VCC Power Supply Rejection VFxO VBB Power Supply Rejection VFxO Absolute Gain Gain Relative to GAx f e 1 kHz VFxI a e 0 Vrms Same as Above f e 1 kHz (TP3040A) f e 1 kHz (TP3040) Below 50 Hz 50 Hz 60 Hz 200 Hz (TP3040A) 200 Hz (TP3040) 300 Hz to 3 kHz (TP3040A) 300 Hz to 3 kHz (TP3040) 3 3 kHz 3 4 kHz 4 0 kHz 4 6 kHz and Above 30 35 29 2 875 30 30 b 41 b 35 b1 5 b1 5 b 0 125 b 0 15 b 0 35 b 0 70 b 15 b 2 5V k VOUT k 2 5V b 3 2V k VOUT k 3 2V 3 10 100 1 3 kX kX pF X dB dB 31 3 125 b 35 b 35 b 30 dB dB dB dB dB dB dB dB dB dB dB dB dB ms ms dB dB dBrnc0 0 0 05 0 125 0 15 0 03 b0 1 b 14 b 32 250 60 b 48 DAx DDx DPx1 DPx2 NCx1 NCx2 Absolute Delay at 1 kHz Differential Envelope Delay from 1 kHz to 2 6 kHz Single Frequency Distortion Products Distortion at Maximum Signal Level Total C Message Noise at VFxO Total C Message Noise at VFxO 0 16 Vrms 1 kHz Signal Applied to VFxI a Gain e 20 dB RL e 10k TP3040 TP3040A Gain Setting Op Amp at 20 dB Non-Inverting (Note 3) TA e 0 C to 70 C TP3040 TP3040A 2 b 45 5 3 6 dBrnc0 GAxT GAxS CTRX Temperature Coefficient of 1 kHz Gain Supply Voltage Coefficient of 1 kHz Gain Crosstalk Receive to Transmit VFxO VFRO VCC e 5 0V g 5% VBB eb5 0V g 5% Receive Filter Output e 2 2 Vrms VFxI a e 0 Vrms f e 0 2 kHz to 3 4 kHz Measure VFxO Output Level e a 3 dBm0 a 2 dBm0 to b 40 dBm0 b 40 dBm0 to b 55 dBm0 b0 1 b 0 05 b0 1 0 0004 0 01 b 70 dB C dB V dB 20 log GRxL Gaintracking Relative to GAx 01 0 05 01 dB dB dB 3 AC Electrical Characteristics (Continued) Unless otherwise specified TA e 25 C All parameters are specified for a signal level of 0 dBm0 at 1 kHz The 0 dBm0 level is assumed to be 1 54 Vrms measured at the output of the transmit or receive filter Limits printed in BOLD characters are guaranteed for VCC e a 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e a 5 0V VBB e b5 0V TA e 25 C Symbol Parameter Conditions Min Typ Max Units RECEIVE FILTER (Unless otherwise noted the receive filter is preceded by a sin x x filter with an input signal level of 1 54 Vrms ) IBR RIR ROR CLR RLR PSRR3 VOSRO GAR GRR Input Leakage Current VFRI Input Resistance VFRI Output Resistance VFRO Load Capacitance VFRO Load Resistance VFRO Power Supply Rejection of VCC or VBB VFRO Output DC Offset VFRO Absolute Gain Gain Relative to Gain at 1 kHz VFRI Connected to GNDA f e 1 kHz VFRI Connected to GNDA f e 1 kHz (TP3040A) f e 1 kHz (TP3040) Below 300 Hz 300 Hz to 3 0 kHz (TP3040A) 300 Hz to 3 0 kHz (TP3040) 3 3 kHz 3 4 kHz 4 0 kHz 4 6 kHz and Above 10 35 b 200 b0 1 b 0 125 b 0 125 b 0 15 b 0 35 b0 7 b 3 2V s VIN s 3 2V b 100 100 nA MX 10 1 3 100 X pF kX dB 200 0 0 01 0 125 0 125 0 125 0 15 0 03 b0 1 b 14 b 32 140 100 mV dB dB dB dB dB dB dB dB dB ms ms dB dB dBrnc0 dB C dB V DAR DDR DPR1 DPR2 NCR GART GARS CTXR Absolute Delay at 1 kHz Differential Envelope Delay 1 kHz to 2 6 kHz Single Frequency Distortion Products Distortion at Maximum Signal Level Total C-Message Noise at VFRO Temperature Coefficient of 1 kHz Gain Supply Voltage Coefficient of 1 kHz Gain Crosstalk Transmit to Receive VFRO 20 log VFxO Gaintracking Relative to GAR Transmit Filter Output e 2 2 Vrms VFRI e 0 Vrms f e 0 3 kHz to 3 4 kHz Measure VFRO Output Level e a 3 dBm0 a 2 dBm0 to b 40 dBm0 b 40 dBm0 to b 55 dBm0 (Note 5) b0 1 b 0 05 b0 1 f e 1 kHz 2 2 Vrms Input to Sin x x Filter f e 1 kHz RL e 10k TP3040 TP3040A 3 0 0004 0 01 b 48 b 45 5 b 70 dB GRRL 01 0 05 01 dB dB dB 4 AC Electrical Characteristics (Continued) Unless otherwise specified TA e 25 C All parameters are specified for a signal level of 0 dBm0 at 1 kHz The 0 dBm0 level is assumed to be 1 54 Vrms measured at the output of the transmit or receive filter Limits printed in BOLD characters are guaranteed for VCC e a 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e a 5 0V VBB e b5 0V TA e 25 C Symbol Parameter Conditions Min Typ Max Units RECEIVE OUTPUT POWER AMPLIFIER IBP RIP ROP1 CLP GAp a GApb GRpL S Dp VOSP PSRR5 Input Leakage Current PWRI Input Resistance PWRI Output Resistance PWRO a PWROb Load Capacitance PWRO a PWROb Gain PWRI to PWRO a Gain PWRI to PWROb Gaintracking Relative to 0 dBm0 Output Level Including Receive Filter Signal Distortion Output DC Offset PWRO a PWROb Power Supply Rejection of VCC or VBB RL e 600X Connected Between PWRO a and PWROb Input Level e 0 dBm0 (Note 4) V e 2 05 Vrms RL e 600X (Notes 4 5) V e 1 75 Vrms RL e 300X V e 2 05 Vrms RL e 600X (Notes 4 5) V e 1 75 Vrms RL e 300X PWRI Connected to GNDA PWRI Connected to GNDA b 50 b0 1 b0 1 b 3 2V s VIN s 3 2V 01 10 3 mA MX Amplifiers Active 1 500 1 b1 X pF VV VV 01 01 b 45 b 45 dB dB dB dB mV dB 50 45 Note 1 Maximum power consumption will depend on the load impedance connected to the power amplifier This specification listed assumes 0 dBm is delivered to 600X connected from PWRO a to PWRO b Note 2 Voltage input to receive filter at 0V VFRO connected to PWRI 600X from PWRO a to PWRO b Output measured from PWRO a to PWRO b Note 3 The 0 dBm0 level for the filter is assumed to be 1 54 Vrms measured at the output of the XMT or RCV filter Note 4 The 0 dBm0 level for the power amplifiers is load dependent For RL e 600X to GNDA the 0 dBm0 level is 1 43 Vrms measured at the amplifier output For RL e 300X the 0 dBm0 level is 1 22 Vrms Note 5 VFRO connected to PWRI input signal applied to VFRI Note 6 Previous revisions of the datasheet did not clearly indicate this specification requires power amps in powerdown (PWRI e b 5 25V) Typical Application TL H 6660 – 2 Note 1 Transmit voltage gain e R1 a R2 c 02 (The filter itself introduces a 3 dB gain) (R1 a R2 t 10k) R2 Note 2 Receive gain e (R3 a R4 t 10k) R4 R3 a R4 Note In the configuration shown the receive filter power amplifiers will drive a 600X T to R termination to a maximum signal level of 8 5 dBm An alternative arrangement using a transformer winding ratio equivalent to 1 414 1 and 300X resistor RS will provide a maximum signal level of 10 1 dBm across a 600X termination impedance FIGURE 2 5 Connection Diagrams Dual-In-Line Package Plastic Lead Chip Carrier TL H 6660–3 Top View Order Number TP3040J or TP3040AJ See NS Package J16A or TP3040N or TP3040AN See NS Package N16A TL H 6660 – 4 Order Number TP3040V or TP3040AV See NS Package V20A Description of Pin Functions Symbol Function The non-inverting input to the transmit filter VFxI a stage VFxIb The inverting input to the transmit filter stage GSx The output used for gain adjustments of the transmit filter VFRO The low power receive filter output This pin can directly drive the receive port of an electronic hybrid PWRI The input to the receive filter differential power amplifier PWRO a The non-inverting output of the receive filter power amplifier This output can directly interface conventional transformer hybrids PWROb The inverting output of the receive filter power amplifier This output can be used with PWRO a to differentially drive a transformer hybrid VBB The negative power supply pin Recommended input is b5V VCC The positive power supply pin The recommended input is 5V VFRI The input pin for the receive filter stage Symbol Function GNDD Digital ground input pin All digital signals are referenced to this pin CLK Master input clock Input frequency can be selected as 2 048 MHz 1 544 MHz or 1 536 MHz PDN The input pin used to power down the TP3040 TP3040A during idle periods Logic 1 (VCC) input voltage causes a power down condition An internal pull-up is provided CLK0 This input pin selects internal counters in accordance with the CLK input clock frequency CLK Connect CLK0 to 2048 kHz VCC 1544 kHz GNDD 1536 kHz VBB An internal pull-up is provided Analog ground input pin All analog signals are referenced to this pin Not internally connected to GNDD The output of the transmit filter stage GNDA VFxO 6 Functional Description The TP3040 TP3040A monolithic filter contains four main sections Transmit Filter Receive Filter Receive Filter Power Amplifier and Frequency Divider Select Logic (Figure 1 ) A brief description of the circuit operation for each section is provided below TRANSMIT FILTER The input stage of the transmit filter is a CMOS operational amplifier which provides an input resistance of greater than 10 MX a voltage gain of greater than 5 000 low power consumption (less than 3 mW) high power supply rejection and is capable of driving a 10 kX load in parallel with up to 25 pF The inputs and output of the amplifier are accessible for added flexibility Non-inverting mode inverting mode or differential amplifier mode operation can be implemented with external resistors It can also be connected to provide a gain of up to 20 dB without degrading the overall filter performance The input stage is followed by a prefilter which is a two-pole RC active low pass filter designed to attenuate high frequency noise before the input signal enters the switched-capacitor high pass and low pass filters A high pass filter is provided to reject 200 Hz or lower noise which may exist in the signal path The low pass portion of the switched-capacitor filter provides stopband attenuation which exceeds the D3 and D4 specifications as well as the CCITT G712 recommendations (Figure 3) The output stage of the transmit filter the postfilter is also a two-pole RC active low pass filter which attenuates clock frequency noise by at least 40 dB The output of the transmit filter is capable of driving a g 3 2V peak to peak signal into a 10 kX load in parallel with up to 25 pF RECEIVE FILTER The input stage of the receive filter is a prefilter which is similar to the transmit prefilter The prefilter attenuates high frequency noise that may be present on the receive input signal A switched capacitor low pass filter follows the prefilter to provide the necessary passband flatness stopband rejection and sin x x gain correction A postfilter which is similar to the transmit postfilter follows the low pass stage It attenuates clock frequency noise and provides a low output impedance capable of directly driving an electronic subscriber-line-interface circuit (Figure 3) RECEIVE FILTER POWER AMPLIFIERS Two power amplifiers are also provided to interface to transformer coupled line circuits These two amplifiers are driven by the output of the receive postfilter through gain setting resistors R3 R4 (Figure 2 ) The power amplifiers can be deactivated when not required by connecting the power amplifier input (pin 5) to the negative power supply VBB This reduces the total filter power consumption by approximately 10 mW–20 mW depending on output signal amplitude POWER DOWN CONTROL A power down mode is also provided A logic 1 power down command applied on the PDN pin (pin 13) will reduce the total filter power consumption to less than 1 mW Connect PDN to GNDD for normal operation FREQUENCY DIVIDER AND SELECT LOGIC CIRCUIT This circuit divides the external clock frequency down to the switching frequency of the low pass and high pass switched capacitor filters The divider also contains a TTL-CMOS interface circuit which converts the external TTL clock level to the CMOS logic level required for the divider logic This interface circuit can also be directly driven by CMOS logic A frequency select circuit is provided to allow the filter to operate with 2 048 MHz 1 544 MHz or 1 536 MHz clock frequencies By connecting the frequency select pin CLK0 (pin 14) to VCC a 2 048 MHz clock input frequency is selected Digital ground selects 1 544 MHz and VBB selects 1 536 MHz Applications Information GAIN ADJUST Figure 2 shows the signal path interconnections between the TP3040 TP3040A and the TP3020 signal-channel CODEC The transmit RC coupling components have been chosen both for minimum passband droop and to present the correct impedance to the CODEC during sampling Optimum noise and distortion performance will be obtained from the TP3040 TP3040A filter when operated with system peak overload voltages of g 2 5V to g 3 2V at VFxO and VFRO When interfacing to a PCM CODEC with a peak overload voltage outside this range further gain or attenuation may be required BOARD LAYOUT Care must be taken in PCB layout to minimize power supply and ground noise Analog ground (GNDA) of each filter should be connected to digital ground (GNDD) at a single point which should be bypassed to both power supplies Further power supply decoupling adjacent to each filter and CODEC is recommended Ground loops should be avoided both between GNDA and GNDD and between the GNDA traces of adjacent filters and CODECs 7 Typical Performance Characteristics Transmit Filter Stage Receive Filter Stage TL H 6660 – 5 TL H 6660 – 6 FIGURE 3 8 Physical Dimensions Ceramic Dual-In-Line Package (J) Order Number TP3040J or TP3040AJ NS Package Number J16A Molded Dual-In-Line Package (M) Order Number TP3040N or TP3040AN NS Package Number N16A 9 TP3040 TP3040A PCM Monolithic Filter Physical Dimensions (Continued) Lit 113919 20-Lead Plastic Chip Carrier Order Number TP3040V or TP3040AV NS Package Number V20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications