TP3057V-X

TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family March 2005 TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO ® Family General Description The TP3054, TP3057 family consists of µ-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS). The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded µ-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded µ-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats. Features n −40˚C to +85˚C operation n Complete CODEC and filtering system (COMBO) including: — Transmit high-pass and low-pass filtering — Receive low-pass filter with sin x/x correction — Active RC noise filters — µ-law or A-law compatible COder and DECoder — Internal precision voltage reference — Serial I/O interface — Internal auto-zero circuitry n µ-law, 16-pin — TP3054 n A-law, 16-pin — TP3057 n Designed for D3/D4 and CCITT applications n ± 5V operation n Low operating power — typically 50 mW n Power-down standby mode — typically 3 mW n Automatic power-down n TTL or CMOS compatible digital interfaces n Maximizes line interface card circuit density n Dual-In-Line or PCC surface mount packages n See also AN-370, “Techniques for Designing with CODEC/Filter COMBO Circuits” Connection Diagrams Plastic Chip Carriers Dual-In-Line Package 00867401 00867408 Top View Order Number TP3057V-X NS Package Number V20A Top View Order Number TP3054N-X NS Package Number N16E Order Number TP3054WM-X NS Package Number M16B COMBO ® and TRI-STATE ® are registered trademarks of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS008674 www.national.com TP3054-X, TP3057-X Block Diagram 00867402 FIGURE 1. Pin Descriptions Symbol VBB GNDA VFRO VCC FSR Function Negative power supply pin. VBB = −5V ± 5%. Analog ground. All signals are referenced to this pin. Analog output of the receive power amplifier. Positive power supply pin. VCC = +5V ± 5%. Receive frame sync pulse which enables BCLKR to shift PCM data into DR. FSR is an 8 kHz pulse train. See Figure 2 and Figure 3 for timing details. Receive data input. PCM data is shifted into DR following the FSR leading edge. Symbol Function BCLKR/CLKSEL The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see Table 1). MCLKR/PDN Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. DR www.national.com 2 TP3054-X, TP3057-X Pin Descriptions Symbol MCLKX (Continued) Function Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKR. Best performance is realized from synchronous operation. Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX. FSX is an 8 kHz pulse train, see Figure 2 and Figure 3 for timing details. The bit clock which shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. The TRI-STATE ® PCM data output which is enabled by FSX. Open drain output which pulses low during the encoder time slot. Analog output of the transmit input amplifier. Used to externally set gain. FSX With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/ CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R. TABLE 1. Selection of Master Clock Frequencies Master Clock BCLKR/CLKSEL Clocked 0 1 Frequency Selected TP3057 2.048 MHz 1.536 MHz or 1.544 MHz 2.048 MHz 1.536 MHz or 1.544 MHz ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in Figure 2. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. TP3054 1.536 MHz or 1.544 MHz 2.048 MHz BCLKX DX TSX GSX VFXI − Inverting input of the transmit input amplifier. Non-inverting input of the transmit input amplifier. VFXI+ Functional Description POWER-UP When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high; the alternative is to hold both FSX and FSR inputs continuously low — the device will power-down approximately 1 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. 3 www.national.com TP3054-X, TP3057-X Functional Description LONG FRAME SYNC OPERATION (Continued) To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. In applications where the LSB bit is used for signalling, with FSR two bit clock periods long, the decoder will interpret the lost LSB as “1⁄2” to minimize noise and distortion. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to µ-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successiveapproximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 µs (due to the transmit filter) plus 125 µs (due to encoding delay), which totals 290 µs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or µ-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 µs later the decoder DAC output is updated. The total decoder delay is ∼10 µs (decoder update) plus 110 µs (filter delay) plus 62.5 µs (1⁄2 frame), which gives approximately 180 µs. www.national.com 4 TP3054-X, TP3057-X Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to GNDA VBB to GNDA Voltage at any Analog Input or Output 7V −7V VCC+0.3V to VBB−0.3V Voltage at any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 300˚C VCC+0.3V to GNDA−0.3V −55˚C to + 125˚C −65˚C to +150˚C Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ± 5%, VBB = −5.0V ± 5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C. Symbol DIGITAL INTERFACE VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage DX, IL=3.2 mA SIGR, IL=1.0 mA TSX, IL=3.2 mA, Open Drain VOH IIL IIH IOZ Output High Voltage Input Low Current Input High Current Output Current in High Impedance State (TRI-STATE) ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA RIXA ROXA RLXA CLXA VOXA AVXA FUXA VOSXA VCMXA PSRRXA RORF RLRF CLRF VOSRO ICC0 IBB0 ICC1 IBB1 Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth Offset Voltage Common-Mode Voltage Power Supply Rejection Ratio Output Resistance Load Resistance Load Capacitance Output DC Offset Voltage Power-Down Current Power-Down Current Power-Up (Active) Current Power-Up (Active) Current No Load (Note 2) No Load (Note 2) No Load( –40˚C to 85˚C) No Load ( –40˚C to 85˚C) −200 0.65 0.01 5.0 5.0 CMRRXA > 60 dB DC Test DC Test Pin VFRO VFRO= ± 2.5V 600 500 200 2.0 0.33 11.0 11.0 −2.5V≤V≤+2.5V, VFXI+ or VFXI− −2.5V≤V≤+2.5V, VFXI+ or VFXI− Closed Loop, Unity Gain GSX GSX GSX, RL ≥ 10 kΩ VFXI+ to GSX −2.8 5000 1 −20 −2.5 60 60 1 3 2 20 2.5 10 50 2.8 −200 10 1 3 200 nA MΩ Ω kΩ pF V V/V MHz mV V dB dB Ω Ω pF mV mA mA mA mA DX, IH=−3.2 mA SIGR, IH=−1.0 mA GNDA≤VIN≤VIL, All Digital Inputs VIH≤VIN≤VCC DX, GNDA≤VO≤VCC 2.4 2.4 −10 −10 −10 10 10 10 2.2 0.4 0.4 0.4 0.6 V V V V V V V µA µA µA Parameter Conditions Min Typ Max Units CMRRXA Common-Mode Rejection Ratio ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) POWER DISSIPATION (ALL DEVICES) Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 2: ICC0 and IBB0 are measured after first achieving a power-up state. 5 www.national.com TP3054-X, TP3057-X Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ± 5%, VBB = −5.0V ± 5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB = –5.0V, TA = 25˚C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol 1/tPM Parameter Frequency of Master Clocks Conditions Depends on the Device Used and the BCLKR/CLKSEL Pin. MCLKX and MCLKR tRM tFM tPB tRB tFB tWMH tWML tSBFM Rise Time of Master Clock Fall Time of Master Clock Period of Bit Clock Rise Time of Bit Clock Fall Time of Bit Clock Width of Master Clock High Width of Master Clock Low Set-Up Time from BCLKX High to MCLKX Falling Edge tSFFM tWBH tWBL tHBFL tHBFS tSFB tDBD tDBTS tDZC tDZF Setup Time from FSX High to MCLKX Falling Edge Width of Bit Clock High Width of Bit Clock Low Holding Time from Bit Clock Low to Frame Sync Holding Time from Bit Clock High to Frame Sync Set-Up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid Delay Time to TSX Low Delay Time from BCLKX Low to Data Output Disabled Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later tSDB tHBD tSF tHF tHBFl Set-Up Time from DR Valid to BCLKR/X Low Hold Time from BCLKR/X Low to DR Invalid Set-Up Time from FSX/R to BCLKX/R Low Hold Time from BCLKX/R Low to FSX/R Low Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) tWFL Minimum Width of the Frame Sync Pulse (Low Level) 64k Bit/s Operating Mode 160 ns Short Frame Sync Pulse (1 Bit Clock Period Long) Short Frame Sync Pulse (1 Bit Clock Period Long) Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods Long) 100 ns 100 ns 50 ns 50 ns 50 ns CL=0 pF to 150 pF 20 165 ns Load=150 pF plus 2 LSTTL Loads CL=0 pF to 150 pF 50 140 165 ns ns Load=150 pF plus 2 LSTTL Loads 0 140 ns Long Frame Only 115 ns Short Frame Only 0 ns BCLKX and BCLKR BCLKX and BCLKR MCLKX and MCLKR MCLKX and MCLKR First Bit Clock after the Leading Edge of FSX Long Frame Only VIH=2.2V VIL=0.6V Long Frame Only Long Frame 125 100 160 160 0 ns ns ns ns Short Frame 160 160 100 MCLKX and MCLKR MCLKX and MCLKR 485 488 Min Typ 1.536 1.544 2.048 50 50 15725 50 50 Max Units MHz MHz MHz ns ns ns ns ns ns ns ns www.national.com 6 Timing Diagrams TP3054-X, TP3057-X 7 00867403 FIGURE 2. Short Frame Sync Timing www.national.com TP3054-X, TP3057-X (Continued) www.national.com 00867409 Timing Diagrams 8 FIGURE 3. Long Frame Sync Timing TP3054-X, TP3057-X Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ± 5%, VBB = −5.0V ± 5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C. Symbol Parameter Absolute Levels (Definition of nominal gain) tMAX Conditions Nominal 0 dBm0 Level is 4 dBm (600Ω) 0 dBm0 Max Overload Level TP3054 (3.17 dBm0) TP3057 (3.14 dBm0) GXA GXR Transmit Gain, Absolute Transmit Gain, Relative to GXA TA=25˚C, VCC=5V, VBB=−5V Input at GSx=0 dBm0 at 1020 Hz f=16 Hz f=50 Hz f=60 Hz f=200 Hz f=300 Hz–3000 Hz f=3152 Hz f=3300 Hz f=3400 Hz f=4000 Hz f=4600 Hz and Up, Measure Response from 0 Hz to 4000 Hz GXAT GXAV GXRL Absolute Transmit Gain Variation with Temperature Absolute Transmit Gain Variation with Supply Voltage Transmit Gain Variations with Level Sinusoidal Test Method Reference Level=−10 dBm0 VFXI+=−40 dBm0 to +3 dBm0 VFXI =−50 dBm0 to −40 dBm0 VFXI+=−55 dBm0 to −50 dBm0 GRA Receive Gain, Absolute TA=25˚C, VCC=5V, VBB=−5V Input=Digital Code Sequence for 0 dBm0 Signal at 1020 Hz GRR Receive Gain, Relative to GRA f=0 Hz to 3000 Hz f=3300 Hz f=3400 Hz f=4000 Hz GRAT GRAV GRRL Absolute Receive Gain Variation with Temperature Absolute Receive Gain Variation with Supply Voltage Receive Gain Variations with Level Sinusoidal Test Method; Reference Input PCM Code Corresponds to an Ideally Encoded PCM Level =−40 dBm0 to +3 dBm0 PCM Level =−50 dBm0 to −40 dBm0 PCM Level =−55 dBm0 to −50 dBm0 −0.2 −0.4 −1.2 0.2 0.4 1.2 dB dB dB Relative to GRA −0.05 0.05 dB Relative to GRA −0.15 −0.20 −0.15 −0.35 −0.7 0.20 0.15 0.1 0 −14 0.15 dB dB dB dB dB dB + Min Typ Max Units AMPLITUDE RESPONSE 1.2276 2.501 2.492 −0.15 0.15 −40 −30 −26 −1.8 −0.15 −0.15 −0.35 −0.7 −0.1 0.15 0.20 0.1 0 −14 −32 −0.15 −0.05 0.15 0.05 Vrms VPK VPK dB dB dB dB dB dB dB dB dB dB dB dB dB Relative to GXA Relative to GXA −0.2 −0.4 −1.2 0.2 0.4 1.2 dB dB dB 9 www.national.com TP3054-X, TP3057-X Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ± 5%, VBB = −5.0V ± 5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C. Parameter Receive Output Drive Level Transmit Delay, Absolute Transmit Delay, Relative to DXA RL=600Ω f=1600 Hz f=500 Hz−600 Hz f=600 Hz−800 Hz f=800 Hz−1000 Hz f=1000 Hz−1600 Hz f=1600 Hz−2600 Hz f=2600 Hz−2800 Hz f=2800 Hz−3000 Hz Conditions Min −2.5 290 195 120 50 20 55 80 130 180 −40 −30 −25 −20 70 100 145 12 −74 90 125 175 16 −67 Typ Max 2.5 315 220 145 75 40 75 105 155 200 Units V µs µs µs µs µs µs µs µs µs µs µs µs µs µs dBrnC0 dBm0p Symbol VRO DXA DXR AMPLITUDE RESPONSE ENVELOPE DELAY DISTORTION WITH FREQUENCY DRA DRR Receive Delay, Absolute Receive Delay, Relative to DRA f=1600 Hz f=500 Hz−1000 Hz f=1000 Hz−1600 Hz f=1600 Hz−2600 Hz f=2600 Hz−2800 Hz f=2800 Hz−3000 Hz NOISE NXC NXP NRC NRP NRS PPSRX NPSRX PPSRR Transmit Noise, C Message Weighted Transmit Noise, P Message Weighted Receive Noise, C Message Weighted Receive Noise, P Message Weighted Noise, Single Frequency Positive Power Supply Rejection, Transmit Negative Power Supply Rejection, Transmit Positive Power Supply Rejection, Receive TP3054 (Note 3) TP3057 (Note 3) PCM Code is Alternating Positive and Negative Zero — TP3054 TP3057 PCM Code Equals Positive Zero — f=0 kHz to 100 kHz, Loop Around Measurement, VFXI+=0 Vrms VCC=5.0 VDC+100 mVrms f=0 kHz−50 kHz (Note 4) VBB=−5.0 VDC+ 100 mVrms f=0 kHz−50 kHz (Note 4) PCM Code Equals Positive Zero VCC=5.0 VDC+100 mVrms Measure VFR0 f=0 Hz−4000 Hz f=4 kHz−25 kHz f=25 kHz−50 kHz NPSRR Negative Power Supply Rejection, Receive PCM Code Equals Positive Zero VBB=−5.0 VDC+100 mVrms Measure VFR0 f=0 Hz−4000 Hz f=4 kHz−25 kHz f=25 kHz−50 kHz 38 38 35 dBC dB dB 38 38 35 dBC dB dB 40 dBC 40 dBC −82 −79 −53 dBm0p dBm0 8 11 dBrnC0 www.national.com 10 TP3054-X, TP3057-X Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ± 5%, VBB = −5.0V ± 5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C. Parameter Spurious Out-of-Band Signals at the Channel Output Conditions Loop Around Measurement, 0 dBm0, 300 Hz to 3400 Hz Input PCM Code Applied at DR. 4600 Hz–7600 Hz 7600 Hz–8400 Hz 8400 Hz–100,000 Hz −30 −40 −30 dB dB dB Min Typ Max −30 Units dB Symbol NOISE SOS DISTORTION STDX, STDR Signal to Total Distortion Transmit or Receive Half-Channel Sinusoidal Test Method (Note 6) Level=3.0 dBm0 =0 dBm0 to −30 dBm0 =−40 dBm0 =−55 dBm0 SFDX SFDR IMD Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion Loop Around Measurement, VFXI+=−4 dBm0 to −21 dBm0, Two Frequencies in the Range 300 Hz−3400 Hz CROSSTALK CTX-R CTR-X Transmit to Receive Crosstalk, 0 dBm0 Transmit Level Receive to Transmit Crosstalk, 0 dBm0 Receive Level f=300 Hz−3400 Hz DR=Quiet PCM Code (Note 6) f=300 Hz−3400 Hz, VFXI=Multitone (Note 4) −90 −70 dB −90 −70 dB −41 dB −43 dB XMT RCV XMT RCV 33 36 28 29 13 14 −43 dBC dBC dBC dBC dBC dBC dB ENCODING FORMAT AT DX OUTPUT TP3054 µ-Law VIN (at GSX)=+Full-Scale VIN (at GSX)=0V VIN (at GSX)=−Full-Scale 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 1 TP3057 A-Law (Includes Even Bit Inversion) 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 Note 3: Measured by extrapolation from the distortion test result at −50 dBm0. Note 4: PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+. Note 5: TP3054/57 are measured using C message weighted filter for µ-law and psophometric weighted filter for A-law. Note 6: CTX–R @ 1.544 MHz MCLKX freq. is −70 dB max. 50% ± 5% BCLKX duty cycle. 11 www.national.com TP3054-X, TP3057-X Applications Information POWER SUPPLIES While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a “hot” socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 µF supply decoupling capacitors should be connected from this common ground point to VCC and VBB, as close to device pins as possible. For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus. T-Pad Attenuator This common ground point should be decoupled to VCC and VBB with 10 µF capacitors. RECEIVE GAIN ADJUSTMENT For applications where a TP3050 family CODEC/filter receive output must drive a 600Ω load, but a peak swing lower than ± 2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or π-pad at the output. Table 2 lists the required resistor values for 600Ω terminations. As these are generally non-standard values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600Ω is obtained if the output impedance of the attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer). 00867411 www.national.com 12 TP3054-X, TP3057-X Applications Information π-Pad Attenuator (Continued) 00867412 Note: See Application Note 370 for further details. TABLE 2. Attentuator Tables for Z1=Z2=300Ω (All Values in Ω) dB 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 R1 1.7 3.5 5.2 6.9 8.5 10.4 12.1 13.8 15.5 17.3 34.4 51.3 68 84 100 115 379 143 156 168 180 190 200 210 218 233 246 R2 26k 13k 8.7k 6.5k 5.2k 4.4k 3.7k 3.3k 2.9k 2.6l 1.3k 850 650 494 402 380 284 244 211 184 161 142 125 110 98 77 61 R3 3.5 6.9 10.4 13.8 17.3 21.3 24.2 27.7 31.1 34.6 70 107 144 183 224 269 317 370 427 490 550 635 720 816 924 1.17k 1.5k R4 52k 26k 17.4k 13k 10.5k 8.7k 7.5k 6.5k 5.8k 5.2k 2.6k 1.8k 1.3k 1.1k 900 785 698 630 527 535 500 473 450 430 413 386 366 13 www.national.com TP3054-X, TP3057-X Typical Synchronous Application 00867406 FIGURE 4. www.national.com 14 TP3054-X, TP3057-X Physical Dimensions unless otherwise noted inches (millimeters) Dual-In-Line Package (M) Order Number TP3054WM-X NS Package Number M16B Molded Dual-In-Line Package (N) Order Number TP3054N-X NS Package Number N16E 15 www.national.com TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Cavity Dual-In-Line Package (V) Order Number TP3057V-X NS Package Number V20A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.