TP3070J

TP3070, TP3071, TP3070-X COMBO II Programmable PCM CODEC/Filter April 1994 TP3070, TP3071, TP3070-X COMBO ® II Programmable PCM CODEC/Filter General Description The TP3070 and TP3071 are second-generation combined PCM CODEC and Filter devices optimized for digital switching applications on subscriber line and trunk cards. Using advanced switched capacitor techniques, COMBO II combines transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional serial PCM interface capable of being clocked up to 4.096 MHz. A number of programmable functions may be controlled via a serial control port. Channel gains are programmable over a 25.4 dB range in each direction, and a programmable filter is included to enable Hybrid Balancing to be adjusted to suit a wide range of loop impedance conditions. Both transformer and active SLIC interface circuits with real or complex termination impedances can be balanced by this filter, with cancellation in excess of 30 dB being readily achievable when measured across the passband against standard test termination networks. To enable COMBO II to interface to the SLIC control leads, a number of programmable latches are included; each may be configured as either an input or an output. The TP3070 provides 6 latches and the TP3071 5 latches. Features n Complete CODEC and FILTER system including: — Transmit and receive PCM channel filters — µ-law or A-law companding encoder and decoder — Receive power amplifier drives 300Ω — 4.096 MHz serial PCM data (max) n Programmable Functions: — Transmit gain: 25.4 dB range, 0.1 dB steps — Receive gain: 25.4 dB range, 0.1 dB steps — Hybrid balance cancellation filter — Time-slot assignment; up to 64 slots/frame — 2 port assignment (TP3070) — 6 interface latches (TP3070) — A or µ-law — Analog loopback — Digital loopback n Direct interface to solid-state SLICs n Simplifies transformer SLIC; single winding secondary n Standard serial control interface n 80 mW operating power (typ) n 1.5 mW standby power (typ) n Designed for CCITT and LSSGR applications n TTL and CMOS compatible digital interfaces n Extended temperature versions available for −40˚C to +85˚C (TP3070V-X) Note: See also AN-614, COMBO II application guide. COMBO ® and TRI-STATE ® are registered trademarks of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS008635 www.national.com Block Diagram DS008635-1 FIGURE 1. Connection Diagrams DS008635-2 DS008635-4 Order Number TP3070V (0˚C to +70˚C) Order Number TP3070V-X (−40˚C to +85˚C) See NS Package Number V28A Order Number TP3071J See NS Package Number J20A Order Number TP3071N See NS Package Number N20A Pin Descriptions Pin VCC VBB GND FSX Description +5V ± 5% power supply. −5V ± 5% power supply. Ground. All analog and digital signals are referenced to this pin. Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (non-delayed data timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot assignment counter). www.national.com 2 Pin Descriptions Pin FSR (Continued) Description Pin CI/O Description This is the Control Data I/O pin which is provided on the TP3071. Serial control information is shifted to or read from COMBO II on this pin when CS is low. The direction of the data is determined by the current instruction as defined in Table 1. This is a separate Control Input, available only on the TP3070. It can be connected to CO if required. This is a separate Control Output, available only on the TP3070. It can be connected to CI if required. Chip Select input. When this pin is low, control information can be written to or read from COMBO II via the CI/O pin (or CI and CO). IL5 through IL0 are available on the TP3070. IL4 through IL0 are available on the TP3071. Each Interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO (or CI/O) pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. This logic input must be pulled low for normal operation of COMBO II. When pulled momentarily high (at least 1 µsec.), all programmable registers in the device are reset to the states specified under “Power-On Initialization”. No Connection. Do not connect to this pin. Do not route traces through this pin. Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter). Bit clock input used to shift PCM data into and out of the DR and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK. Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. The Transmit analog high-impedance input. Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected DX pin. The Receive analog power amplifier output, capable of driving load impedances as low as 300Ω (depending on the peak overload level required). PCM data received on the assigned DR pin is decoded and appears at this output as voice frequency signals. DX1 is available on the TP3070 only; DX0 is available on all devices. These Transmit Data TRI-STATE ® outputs remain in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TSX1 is available on the TP3070 only; TSX0 is available on all devices. Normally these open-drain outputs are floating in a high impedance state except when a time-slot is active on one of the DX outputs, when the appropriate TSX output pulls low to enable a backplane line-driver. DR1 is available on the TP3070 only; DR0 is available on all devices. These receive data inputs are inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. Control Clock input. This clock shifts serial control information into or out from CI/O or CI and CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. CI BCLK CO CS MCLK IL5–IL0 VFXI VFRO MR DX0 DX1 NC TSX0 TSX1 Functional Description POWER-ON INITIALIZATION When power is first applied, power-on reset circuitry initializes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed to OFF (00000000), the hybrid balance circuit is turned off, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Direction Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high impedance state. The CI/O pin is set as an input ready for the first control byte of the initialization sequence. Other initial states in the Control Register are indicated in Section 2.0. A reset to these same initial conditions may also be forced by driving the MR pin momentarily high. This may be done either when powered-up or down. For normal operation this pin must be pulled low. If not used, MR should be hard-wired to ground. The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command. DR0 DR1 CCLK 3 www.national.com Functional Description POWER-DOWN STATE (Continued) Following a period of activity in the powered-up state the power-down state may be re-entered by writing any of the control instructions into the serial control port with the “P” bit set to “1” as indicated in Table 1. It is recommended that the chip be powered down before writing any additional instructions. In the power-down state, all non-essential circuitry is de-activated and the DX0 (and DX1) outputs are in the high impedance TRI-STATE condition. The coefficients stored in the Hybrid Balance circuit and the Gain Control registers, the data in the LDR and ILR, and all control bits remain unchanged in the power-down state unless changed by writing new data via the serial control port, which remains active. The outputs of the Interface Latches also remain active, maintaining the ability to monitor and control the SLIC. TRANSMIT FILTER AND ENCODER The Transmit section input, VFXI, is a high impedance summing input which is used as the differencing point for the internal hybrid balance cancellation signal. No external components are necessary to set the gain. Following this circuit is a programmable gain/attenuation amplifier which is controlled by the contents of the Transmit Gain Register (see Programmable Functions section). An active pre-filter then precedes the 3rd order high-pass and 5th order low-pass switched capacitor filters. The A/D converter has a compressing characteristic according to the standard CCITT A or µ255 coding laws, which must be selected by a control instruction during initialization (see Table 1 and Table 2). A precision on-chip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is canceled by an internal auto-zero circuit. Each encode cycle begins immediately following the assigned Transmit time-slot. The total signal delay referenced to the start of the time-slot is approximately 165 µs (due to the Transmit Filter) plus 125 µs (due to encoding delay), which totals 290 µs. Data is shifted out on DX0 or DX1 during the selected time slot on eight rising edges of BCLK. DECODER AND RECEIVE FILTER PCM data is shifted into the Decoder’s Receive PCM Register via the DR0 or DR1 pin during the selected time-slot on the 8 falling edges of BCLK. The Decoder consists of an expanding DAC with either A or µ255 law decoding characteristic, which is selected by the same control instruction used to select the Encode law during initialization. Following the Decoder is a 5th order low-pass switched capacitor filter with integral Sin x/x correction for the 8 kHz sample and hold. A programmable gain amplifier, which must be set by writing to the Receive Gain Register, is included, and finally a Power Amplifier capable of driving a 300Ω load to ± 3.5V, a 600Ω load to ± 3.8V or a 15 kΩ load to ± 4.0V at peak overload. A decode cycle begins immediately after the assigned receive time-slot, and 10 µs later the Decoder DAC output is updated. The total signal delay is 10 µs plus 120 µs (filter delay) plus 62.5 µs (1⁄2 frame) which gives approximately 190 µs. PCM INTERFACE The FSX and FSR frame sync inputs determine the beginning of the 8-bit transmit and receive time-slots respectively. They may have any duration from a single cycle of BCLK HIGH to one MCLK period LOW. Two different relationships may be established between the frame sync inputs and the actual time-slots on the PCM busses by setting bit 3 in the Control Register (see Table 2). Non-delayed data mode is similar to long-frame timing on the TP3050/60 series of devices (COMBO); time-slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode, which is similar to short-frame sync timing on COMBO, in which each FS input must be high at least a half-cycle of BCLK earlier than the time-slot. The Time-Slot Assignment circuit on the device can only be used with Delayed Data timing. When using Time-Slot Assignment, the beginning of the first time-slot in a frame is identified by the appropriate FS input. The actual transmit and receive time-slots are then determined by the internal Time-Slot Assignment counters. Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned Transmit time-slot, the selected DX0/1 output shifts data out from the PCM register on the rising edges of BCLK. TSX0 (or TSX1 as appropriate) also pulls low for the first 71⁄2 bit times of the time-slot to control the TRI-STATE Enable of a backplane line-driver. Serial PCM data is shifted into the selected DR0/1 input during each assigned Receive time-slot on the falling edges of BCLK. DX0 or DX1 and DR0 or DR1 are selectable on the TP3070 only, see Section 6. www.national.com 4 Functional Description Function (Continued) TABLE 1. Programmable Register Instructions Byte 1 (Note 1) 7 6 X 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 5 X 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 4 X 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 3 X 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 2 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X X X X X X X X X X X X X X X X X X X X Derive from Optimization Routine in TP3077SW Program 7 6 P P P P P P P P P P P P P P P P P P P P P Byte 2 (Note 1) 5 4 3 2 1 0 None See Table 2 See Table 2 See Table 4 See Table 4 See Table 3 See Table 3 See Table 8 See Table 8 See Table 7 See Table 7 See Table 6 See Table 6 See Table 6 See Table 6 Single Byte Power-Up/Down Write Control Register Read-Back Control Register Write to Interface Latch Register Read Interface Latch Register Write Latch Direction Register Read Latch Direction Register Write Receive Gain Register Read Receive Gain Register Write Transmit Gain Register Read Transmit Gain Register Write Receive Time-Slot/Port Read-Back Receive Time-Slot/Port Write Transmit Time-Slot/Port Read-Back Transmit Time-Slot/Port Write Hybrid Balance Register 1 Read Hybrid Balance Register 1 Write Hybrid Balance Register 2 Read Hybrid Balance Register 2 Write Hybrid Balance Register 3 Read Hybrid Balance Register 3 Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CI/O pin. X = don’t care. Note 2: “P” is the power-up/down control bit, see “Power-Up/Down Control” section. (“0” = Power Up, “1” = Power Down) Note 3: Other register address codes are invalid and should not be used. SERIAL CONTROL PORT Control information and data are written into or read-back from COMBO II via the serial control port consisting of the control clock CCLK, the serial data input/output CI/O, (or separate input, CI, and output, CO, on the TP3070 only), and the Chip Select input, CS. All control instructions require 2 bytes, as listed in Table 1, with the exception of a single byte power-up/down command. The byte 1 bits are used as follows: bit 7 specifies power up or power down; bits 6, 5, 4 and 3 specify the register address; bit 2 specifies whether the instruction is read or write; bit 1 specifies a one or two byte instruction; and bit 0 is not used. To shift control data into COMBO II, CCLK must be pulsed 8 times while CS is low. Data on the CI/O (or CI) input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CS pulse or may follow the first contiguously, i.e. it is not mandatory for CS to return high between the first and second control bytes. At the end of CCLK8 in the 2nd control byte the data is loaded into the appropriate programmable register. CS may remain low continuously when programming successive registers, if desired. However, CS should be set high when no data transfers are in progress. To readback Interface Latch data or status information from COMBO II, the first byte of the appropriate instruction is 5 strobed in while CS is low, as defined in Table 1. CS must be kept low, or be taken low again for a further 8 CCLK cycles, during which the data is shifted onto the CO or CI/O pin on the rising edges of CCLK. When CS is high the CO or CI/O pin is in the high-impedance TRI-STATE, enabling the CI/O pins of many devices to be multiplexed together. If CS returns high during either byte 1 or byte 2 before all eight CCLK pulses of that byte occur, both the bit count and byte count are reset and register contents are not affected. This prevents loss of synchronization in the control interface as well as corruption of register data due to processor interrupt or other problem. When CS returns low again, the device will be ready to accept bit 1 of byte 1 of a new instruction. Programmable Functions 1.0 POWER-UP/DOWN CONTROL Following power-on initialization, power-up and power-down control may be accomplished by writing any of the control instructions listed in Table 1 into COMBO II with the “P” bit set to “0” for power-up or “1” for power-down. Normally it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or the separate single-byte instruction. Any of the programmable registers may also be modified while the de- www.national.com Programmable Functions (Continued) vice is powered-up or down by setting the “P” bit as indicated. When the power-up or down control is entered as a single byte instruction, bit one (1) must be reset to a 0. When a power-up command is given, all de-activated circuits are activated, but the TRI-STATE PCM output(s), DX0 (and DX1), will remain in the high impedance state until the second FSX pulse after power-up. 2.0 CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in Table 1. The second byte has the following bit functions: TABLE 2. Control Register Byte 2 Functions Bit Number and Name 7 F1 0 0 1 1 6 F0 0 1 0 1 0 1 X 0 5 MA 4 IA 3 DN 2 DL 1 AL 0 PP MCLK = 512 kHz MCLK = 1.536 or 1.544 MHz MCLK = 2.048 MHz (Note 4) MCLK = 4.096 MHz Select µ-255 law (Note 4) A-law, Including Even Bit Inversion 1 1 0 1 0 1 0 0 X 1 0 1 A-law, No Even Bit Inversion Delayed Data Timing Non-Delayed Data Timing (Note 4) Normal Operation (Note 4) Digital Loopback Analog Loopback Power Amp Enabled in PDN Power Amp Disabled in PDN (Note 4) Function gains remain unchanged, thus care must be taken to ensure that overload levels are not exceeded anywhere in the loop. Hybrid balance must be disabled for meaningful analog loopback function. 2.4 Digital Loopback Digital Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2. This mode provides another stage of path verification by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at DX0/1. In digital loopback, the decoder will remain functional and output a signal at VFRO. If this is undesirable, the receive output can be turned off by programming the receive gain register to all zeros. 3.0 INTERFACE LATCH DIRECTIONS Immediately following power-on, all Interface Latches assume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually programmed as a logic input or output by writing the appropriate instruction to the LDR, see Table 1 and Table 3. For minimum power dissipation, unconnected latch pins should be programmed as outputs. For the TP3071, L5 should always be programmed as an output. Bits L5–L0 must be set by writing the specified instruction to the LDR with the L bits in the second byte set as follows: TABLE 3. Byte 2 Functions of Latch Direction Register Byte 2 Bit Number 7 L0 6 L1 Ln Bit 0 1 X = don’t care 5 L2 4 L3 3 L4 2 L5 1 X 0 X IL Direction Input Output Note 4: State at power-on initialization. (Bit 4 = 0) 2.1 Master Clock Frequency Selection A Master clock must be provided to COMBO II for operation of the filter and coding/decoding functions. The MCLK frequency must be either 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F1 and F0 (see Table 2) must be set during initialization to select the correct internal divider. 2.2 Coding Law Selection Bits “MA” and “IA” in Table 2 permit the selection of µ255 coding or A-law coding, with or without even bit inversion. 2.3 Analog Loopback Analog Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in Table 2. In the analog loopback mode, the Transmit input VFXI is isolated from the input pin and internally connected to the VFRO output, forming a loop from the Receive PCM Register back to the Transmit PCM Register. The VFRO pin remains active, and the programmed settings of the Transmit and Receive INTERFACE LATCH STATES Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the Interface Latch Register (ILR) as shown in Table 1 and Table 4. Latches configured as inputs will sense the state applied by an external source, such as the Off-Hook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR. It is recommended that during initialization, the state of IL pins to be configured as outputs should be programmed first, followed immediately by the Latch Direction Register. TABLE 4. Interface Latch Data Bit Order Bit Number 7 D0 6 D1 5 D2 4 D3 3 D4 2 D5 1 X 0 X www.national.com 6 Programmable Functions (Continued) TABLE 5. Coding Law Conventions µ255 law MSB VIN = +Full Scale VIN = 0V VIN = −Full Scale LSB True A-law with even bit inversion MSB LSB 10101010 11010101 01010101 00101010 A-law without even bit inversion MSB LSB 11111111 10000000 00000000 01111111 10000000 11111111 01111111 00000000 Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II. TABLE 6. Time-Slot and Port Assignment Instruction Bit Number and Name 7 EN 0 0 1 1 6 PS (Note 6) 0 1 0 1 5 T5 (Note 7) X X X X X X X X X X X X Disable DX0 Output (Transmit Instruction) Disable DR0 Input (Receive Instruction) Disable DX1 Output (Transmit Instruction) Disable DR1 Input (Receive Instruction) Assign One Binary Coded Time-Slot from 0–63 Assign One Binary Coded Time-Slot from 0–63 Assign One Binary Coded Time-Slot from 0–63 Assign One Binary Coded Time-Slot from 0–63 Note 6: The “PS” bit MUST always be set to 0 for the TP3071. Note 7: T5 is the MSB of the Time-slot assignment bit field. Time slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data timing mode. Function 2 T2 1 T1 0 T0 4 T4 3 T3 Enable DX0 Output (Transmit Instruction) Enable DR0 Input (Receive Instruction) Enable DX1 Output (Transmit Instruction) Enable DR1 Input (Receive Instruction) 5.0 TIME-SLOT ASSIGNMENT COMBO II can operate in either fixed time-slot or time-slot assignment mode for selecting the Transmit and Receive PCM time-slots. Following power-on, the device is automatically in Non-Delayed Timing mode, in which the time-slot always begins with the leading (rising) edge of frame sync inputs FSX and FSR. Time-Slot Assignment may only be used with Delayed Data timing; see Figure 5. FSX and FSR may have any phase relationship with each other in BCLK period increments. Alternatively, the internal time-slot assignment counters and comparators can be used to access any time-slot in a frame, using the frame sync inputs as marker pulses for the beginning of transmit and receive time-slot 0. In this mode, a frame may consist of up to 64 time-slots of 8 bits each. A time-slot is assigned by a 2-byte instruction as shown in Table 1 and Table 6. The last 6 bits of the second byte indicate the selected time-slot from 0–63 using straight binary notation. When writing a timeslot and port assignment register, if the PCM interface is currently active, it is immediately deactivated to prevent possible bus clashes. A new assignment becomes active on the second frame following the end of the Chip-Select for the second control byte. Rewriting of register contents should not be performed during the talking period of a connection to prevent waveform distortion caused by loss of a sample which will occur with each register write. The “EN” bit allows the PCM inputs, DR0/1, or outputs, DX0/1, as appropriate, to be enabled or disabled. Time-Slot Assignment mode requires that the FSX and FSR pulses must conform to the delayed data timing format shown in Figure 5. 6.0 PORT SELECTION On the TP3070 only, an additional capability is available; 2 Transmit serial PCM ports, DX0 and DX1, and 2 Receive serial PCM ports, DR0 and DR1, are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the “PS” bit in the second byte. The PS bit selects either Port 0 or Port 1. Both ports cannot be active at the same time. On the TP3071, only ports DX0 and DR0 are available, therefore the “PS” bit MUST always be set to 0 for these devices. Table 6 shows the format for the second byte of both transmit and receive time-slot and port assignment instructions. 7.0 TRANSMIT GAIN INSTRUCTION BYTE 2 The transmit gain can be programmed in 0.1 dB steps by writing to the Transmit Gain Register as defined in Table 1 and Table 7. This corresponds to a range of 0 dBm0 levels at VFXI between 1.619 Vrms and 0.087 Vrms (equivalent to +6.4 dBm to −19.0 dBm in 600Ω). To calculate the binary code for byte 2 of this instruction for any desired input 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by: 200 x log10 (V/0.08595) 7 www.national.com Programmable Functions (Continued) and convert to the binary equivalent. Some examples are given in Table 7 and a complete tabulation is given in Appendix I of AN-614. It should be noted that the Transmit (idle channel) Noise and Transmit Signal to Total Distortion are both specified with transmit gain set to 0 dB (Gain Register set to all ones). At high transmit gains there will be some degradation in noise performance for these parameters. See Application Note AN-614 for more information on this subject. TABLE 7. Byte 2 of Transmit Gain Instruction Bit Number 76543210 00000000 00000001 00000010 — 11111110 11111111 0 dBm0 Test Level (Vrms) at VFXI No Output (Note 8) 0.087 0.088 — 1.600 1.619 ator. Either of the filter sections can be bypassed if only one is required to achieve good cancellation. A selectable 180 degree inverting stage is included to compensate for interface circuits which also invert the transmit input relative to the receive output signal. The 2nd order section is intended mainly to balance low frequency signals across a transformer SLIC, and the first order section to balance midrange to higher audio frequency signals. As a 2nd order section, Hybal1 has a pair of low frequency zeroes and a pair of complex conjugate poles. When configuring Hybal1, matching the phase of the hybrid at low to mid-band frequencies is most critical. Once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable attenuator. The 2nd order mode of Hybal1 is most suitable for balancing interfaces with transformers having high inductance of 1.5 Henries or more. An alternative configuration for smaller transformers is available by converting Hybal1 to a simple first-order section with a single real low-frequency pole and zero. In this mode, the pole/zero frequency may be programmed. Many line interfaces can be adequately balanced by use of the Hybal1 section only, in which case the Hybal2 filter should be de-selected to bypass it. Hybal2, the higher frequency first-order section, is provided for balancing an electronic SLIC, and is also helpful with a transformer SLIC in providing additional phase correction for mid and high-band frequencies, typically 1 kHz to 3.4 kHz. Such a correction is particularly useful if the test balance impedance includes a capacitor of 100 nF or less, such as the loaded and non-loaded loop test networks in the United States. Independent placement of the pole and zero location is provided. Note 8: Analog signal path is cut off, but DX remains active and will output codes representing idle noise. 8.0 RECEIVE GAIN INSTRUCTION BYTE 2 The receive gain can be programmed in 0.1 dB steps by writing to the Receive Gain Register as defined in Table 1 and Table 8. Note the following restrictions on output drive capability: a) 0 dBm0 levels ≤ 1.96 Vrms at VFRO may be driven into a load of ≥ 15 kΩ to GND; receive gain set to 0 dB (Gain Register set to all ones) b) 0 dBm0 levels ≤ 1.85 Vrms at VFRO may be driven into a load of ≥ 600Ω to GND; receive gain set to −0.5 dB c) 0 dBm0 levels ≤ 1.71 Vrms at VFRO may be driven into a load of ≥ 300Ω to GND; receive gain set to −1.2 dB To calculate the binary code for byte 2 of this instruction for any desired output 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by: 200 x log10 (V/0.1043) and convert to the binary equivalent. Some examples are given in Table 8 and a complete tabulation is given in Appendix I of AN-614. TABLE 8. Byte 2 of Receive Gain Instruction Bit Number 76543210 00000000 00000001 00000010 — 11111110 11111111 9.0 HYBRID BALANCE FILTER The Hybrid Balance Filter on COMBO II is a programmable filter consisting of a second-order section, Hybal1, followed by a first-order section, Hybal2, and a programmable attenuwww.national.com 8 Figure 2 shows a simplified diagram of the local echo path for a typical application with a transformer interface. The magnitude and phase of the local echo signal, measured at VFXI, are a function of the termination impedance ZT, the line transformer and the impedance of the 2W loop, ZL. If the impedance reflected back into the transformer primary is expressed as ZL' then the echo path transfer function from VFRO to VFXI is: (1) H(w) = ZL'/(ZT + ZL') 9.1 PROGRAMMING THE FILTER On initial power-up, the Hybrid Balance filter is disabled. Before the hybrid balance filter can be programmed it is necessary to design the transformer and termination impedance in order to meet system 2W input return loss specifications, which are normally measured against a fixed test impedance (600 or 900Ω in most countries). Only then can the echo path be modeled and the hybrid balance filter programmed. Hybrid balancing is also measured against a fixed test impedance, specified by each national Telecom administration to provide adequate control of talker and listener echo over the majority of their network connections. This test impedance is ZL in Figure 2. The echo signal and the degree of transhybrid loss obtained by the programmable filter must be measured from the PCM digital input, DR0, to the PCM digital output, DX0, either by digital test signal analysis or by conversion back to analog by a PCM CODEC/Filter. 0 dBm0 Test Level (Vrms) at VFRO No Output (Low Z to GND) 0.105 0.107 — 1.941 1.964 Programmable Functions (Continued) DS008635-5 FIGURE 2. Simplified Diagram of Hybrid Balance Circuit Three registers must be programmed in COMBO II to fully configure the Hybrid Balance Filter as follows: Register 1: select/de-select Hybrid Balance Filter; invert/non-invert cancellation signal; select/de-select Hybal2 filter section; attenuator setting. Register 2: select/de-select Hybal1 filter; set Hybal1 to 2nd order or 1st order; pole and zero frequency selection. Register 3: program pole frequency in Hybal2 filter; program zero frequency in Hybal2 filter. Standard filter design techniques may be used to model the echo path (see Equation (1)) and design a matching hybrid balance filter configuration. Alternatively, the frequency response of the echo path can be measured and the hybrid balance filter designed to replicate it. A Hybrid Balance filter design guide and software optimization program are available under license from National Semiconductor Corporation; order TP3077SW. POWER SUPPLIES While the pins of the TP3070 COMBO II devices are well protected against electrical misuse, it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, extra long pins on the connector should be used for ground and VBB. In addition, a Schottky diode should be connected between VBB and ground. To minimize noise sources, all ground connections to each device should meet at a common point as close as possible to the device GND pin in order to prevent the interaction of ground return currents flowing through a common bus impedance. Power supply decoupling capacitors of 0.1 µF should be connected from this common device ground point to VCC and VBB as close to the device pins as possible. VCC and VBB should also be decoupled with Low Effective Series Resistance Capacitors of at least 10 µF located near the card edge connector. Further guidelines on PCB layout techniques are provided in Application Note AN-614, “ COMBO II™ Programmable PCM CODEC/Filter Family Application Guide”. Applications Information Figure 3 shows a typical application of the TP3071 together with a typical monolithic SLIC. Four of the IL latches are configured as outputs to control the relay drivers on the SLIC, while IL4 is an input for the Supervision signal. 9 www.national.com Applications Information (Continued) DS008635-7 FIGURE 3. Typical Application with Monolithic SLIC www.national.com 10 Absolute Maximum Ratings (Note 9) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to GND Voltage at VFXI Voltage at any Digital Input 7V VCC + 0.5V to VBB − 0.5V VCC + 0.5V to GND − 0.5V Storage Temperature Range VBB to GND Current at VFR0 Current at any Digital Output Lead Temperature (Soldering, 10 sec.) −65˚C to + 150˚C −7V ± 100 mA ± 50 mA 300˚C Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol VIL VIH VOL VOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Conditions All Digital Inputs (DC Meas.) (Note 10) All Digital Inputs (DC Meas.) (Note 10) DX0, DX1, TSX0, TSX1 and CO, IL = 3.2 mA, All Other Digital Outputs, IL = 1 mA DX0, DX1 and CO, IL = −3.2 mA, All Other Digital Outputs (except TSX), IL = −1 mA All Digital Outputs, IL = −100 µA Any Digital Input, GND < VIN < VIL Any Digital Input except MR, VIH < VIN < VCC MR Only IOZ Output Current in High Impedance State (TRI-STATE) ANALOG INTERFACES IVFXI RVFXI VOSX RLVFRO Input Current, VFXI Input Resistance Input Offset Voltage Applied at VFXI Load Resistance −3.3V < VFXI < 3.3V −3.3V < VFXI < 3.3V Transmit Gain = 0 dB Transmit Gain = 25.4 dB Receive Gain = 0 dB Receive Gain = −0.5 dB Receive Gain = −1.2 dB RLVFRO ≥ 300Ω CLVFRO from VFRO to GND ROVFRO VOSR Output Resistance Output Offset Voltage at VFRO POWER DISSIPATION ICC0 Power Down Current CCLK, CI/O, CI, CO, = 0.4V, CS = 2.4V Interface Latches Set as Outputs with No Load, All Other Inputs Active, Power Amp Disabled IBB0 ICC1 Power Down Current Power Up Current As Above −40˚C to +85˚C (TP3070-X) CCLK, CI/O, CI, CO = 0.4V, CS = 2.4V No Load on Power Amp Interface Latches Set as Outputs with No Load −40˚C to +85˚C (TP3070-X) 13.0 mA 8.0 −0.1 −0.3 −0.4 11.0 mA mA mA 0.1 0.6 mA Steady Zero PCM Code Applied to DR0 or DR1 Alternating ± Zero PCM Code Applied to DR0 or DR1, Maximum Receive Gain −200 200 mV 1.0 3.0 Ω −10.0 390 620 200 10 15k 600 300 200 pF Ω 10.0 µA kΩ mV mV DX0, DX1, TSX0, TSX1, CO and CI/O (as an Output) IL5–IL0 When Selected as Inputs GND < VOUT < VCC −40˚C to +85˚C (TP3070-X) −30 30 µA −10 10 µA 2.0 0.4 2.4 VCC − 0.5 −10 −10 −10 10 10 100 Min Typ Max 0.7 Units V V V V V µA µA µA DIGITAL INTERFACES IIL IIH Input Low Current Input High Current CLVFRO Load Capacitance 11 www.national.com Electrical Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol IBB1 ICC2 IBB2 Parameter Power Up Current Power Down Current Power Down Current As Above −40˚C to +85˚C (TP3070-X) Power Amp Enabled −40˚C to +85˚C (TP3070-X) Power Amp Enabled −40˚C to +85˚C (TP3070-X) −2.0 2.0 Conditions Min Typ −8.0 Max −11.0 −13.0 3.0 4.0 −3.0 −4.0 Units mA mA mA mA mA mA POWER DISSIPATION Note 9: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 10: See definitions and timing conventions section. Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%; VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol fMCLK Parameter Frequency of MCLK Conditions Selection of Frequency is Programmable (See Table 5) Min Typ 512 1536 1544 2048 4096 tWMH tWML tRM tFM tHBM tWFL fBCLK tWBH tWBL tRB tFB tHBF tSFB tDBD Period of MCLK High Period of MCLK Low Rise Time of MCLK Fall Time of MCLK HOLD Time, BCLK LOW to MCLK HIGH Period of FSX or FSR Low Frequency of BCLK Period of BCLK High Period of BCLK Low Rise Time of BCLK Fall Time of BCLK Hold Time, BCLK Low to FSX/R High or Low Setup Time, FSX/R High to BCLK Low Delay Time, BCLK High to Data Valid Load = 100 pF Plus 2 LSTTL Loads −40˚C to +85˚C (TP3070-X) 80 90 ns ns 30 ns Measured from VIL to VIL May Vary from 64 kHz to 4096 kHz in 8 kHz Increments Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 30 80 80 30 30 ns ns ns ns ns 1 64 4096 MCLK Period kHz PCM INTERFACE TIMING Measured from VIH to VIH (Note 11) Measured from VIL to VIL (Note 11) Measured from VIL to VIH Measured from VIH to VIL TP3070 Only 50 80 80 30 30 Max Units kHz kHz kHz kHz kHz ns ns ns ns ns MASTER CLOCK TIMING www.national.com 12 Timing Specifications (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%; VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol tDBZ Parameter Delay Time, BCLK Low to DX0/1 Disabled if FSX Low, FSX Low to DX0/1 disabled if 8th BCLK Low, or BCLK High to DX0/1 Disabled if FSX High tDBT Delay Time, BCLK High to TSX Low if FSX High, or FSX High to TSX Low if BCLK High (Non Delayed Mode); BCLK High to TSX Low (Delayed Data Mode) TRI-STATE Time, BCLK Low to TSX High if FSX Low, FSX Low to TSX High if 8th BCLK Low, or BCLK High to TSX High if FSX High Delay Time, FSX/R High to Data Valid Load = 100 pF Plus 2 LSTTL Loads, Applies if FSX/R Rises Later than BCLK Rising Edge in Non-Delayed Data Mode Only −40˚C to +85˚C (TP3070-X) tSDB tHBD Setup Time, DR0/1 Valid to BCLK Low Hold Time, BCLK Low to DR0/1 Invalid SERIAL CONTROL PORT TIMING fCCLK tWCH tWCL tRC tFC tHCS tHSC tSSC tSSCO tSDC tHCD tDCD Frequency of CCLK Period of CCLK High Period of CCLK Low Rise Time of CCLK Fall Time of CCLK Hold Time, CCLK Low to CS Low Hold Time, CCLK Low to CS High Setup Time, CS Transition to CCLK Low Setup Time, CS Transition to CCLK High Setup Time, CI (CI/O) Data In to CCLK Low Hold Time, CCLK Low to CI/O Invalid Delay Time, CCLK High to CI/O Data Out Valid Load = 100 pF plus 2 LSTTL Loads −40˚C to +85˚C (TP3070-X) 80 100 ns ns 50 ns 50 ns 50 ns 60 ns CCLK 8 100 ns Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL CCLK1 10 160 160 50 50 2048 kHz ns ns ns ns ns −40˚C to +85˚C (TP3070-X) 15 15 ns ns 30 90 ns ns 80 ns −40˚C to +85˚C (TP3070-X) Load = 100 pF Plus 2 LSTTL Loads 15 100 60 ns ns Conditions DX0/1 Disabled is measured at VOL or VOH according to Figure 4 or Figure 5 Min Typ Max Units PCM INTERFACE TIMING 15 80 ns tZBT 15 60 ns tDFD 13 www.national.com Timing Specifications (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%; VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol tDSD Parameter Delay Time, CS Low to CO (CI/O) Valid tDDZ Delay Time, CS or 9th CCLK High to CO (CI/O) High Impedance Setup Time, IL to CCLK 8 of Byte 1 tHCL tDCL Hold Time, IL Valid from 8th CCLK Low (Byte 1) Delay Time CCLK 8 of Byte 2 to IL MASTER RESET PIN tWMR Duration of Master Reset High Note 11: Applies only to MCLK Frequencies ≥ 1.536 MHz. At 512 kHz a 50:50 ± 2% Duty Cycle must be used. Conditions Applies Only if Separate CS used for Byte 2 −40˚C to +85˚C (TP3070-X) Applies to Earlier of CS High or 9th CCLK High Min Typ Max 80 100 Units ns ns ns SERIAL CONTROL PORT TIMING 15 80 INTERFACE LATCH TIMING tSLC Interface Latch Inputs Only 100 50 Interface Latch Outputs Only CL = 50 pF 1 200 ns ns ns µs Timing Diagrams DS008635-8 FIGURE 4. Non Delayed Data Timing Mode www.national.com 14 Timing Diagrams (Continued) DS008635-9 FIGURE 5. Delayed Data Timing Mode (Time Slot Zero Only) 15 www.national.com Timing Diagrams (Continued) DS008635-10 www.national.com 16 FIGURE 6. Control Port Timing Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Absolute Levels Conditions The Maximum 0 dBm0 Levels are: VFXI VFRO (15 kΩ Load) The Minimum 0 dBm0 Levels are: VFXI VFRO (Any Load ≥ 300Ω) Overload Levels are 3.17 dBm0 (µLaw) and 3.14 dBm0 (A-Law) GXA Transmit Gain Absolute Accuracy Transmit Gain Programmed for Maximum 0 dBm0 Test Level. (All 1’s in gain register) Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code at DX0/1. TA = 25˚C TA = 25˚C, VCC = 5V, VBB = 5V Programmed Gain from 0 dB to 19 dB (0 dBm0 Levels of 1.619 Vrms to 0.182 Vrms) Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.180 Vrms to 0.087 Vrms) Note: ± 0.1 dB min/max is available as a selected part. Min Typ Max Units AMPLITUDE RESPONSE 1.619 1.964 87.0 105.0 Vrms Vrms mVrms mVrms −0.15 0.15 dB GXAG Transmit Gain Variation with Programmed Gain −0.1 0.1 dB −0.3 0.3 dB GXAF Transmit Gain Variation with Frequency Relative to 1015.625 Hz, (Note 15) Minimum Gain < GX < Maximum Gain f = 60 Hz f = 200 Hz f = 300 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f ≥ 4600 Hz. Measure Response at Alias Frequency from 0 kHz to 4 kHz. GX = 0 dB, VFXI = 1.619 Vrms Relative to 1015.625 Hz f = 62.5 Hz f = 203.125 Hz f = 343.75 Hz f = 515.625 Hz f = 2140.625 Hz f = 3156.25 Hz f = 3406.250 Hz f = 3984.375 Hz Relative to 1062.5 Hz (Note 15) f = 5250 Hz, Measure 2750 Hz f = 11750 Hz, Measure 3750 Hz f = 49750 Hz, Measure 1750 Hz −1.7 −0.15 −0.15 −0.15 −0.15 −0.74 −24.9 −0.1 0.15 0.15 0.15 0.15 0.0 −13.5 −32 −32 −32 dB dB dB dB dB dB dB dB dB dB dB −26 −1.8 −0.15 −0.7 −0.1 0.15 0.0 −14 −32 dB dB dB dB dB dB 17 www.national.com Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol GXAT Parameter Transmit Gain Variation with Temperature GXAL Transmit Gain Variation with Signal Level Conditions Measured Relative to GXA, VCC = 5V, VBB = −5V, Minimum gain < GX < Maximum Gain −40˚C to +85˚C (TP3070-X) Sinusoidal Test Method. Reference Level = 0 dBm0. VFXI = −40 dBm0 to +3 dBm0 VFXI = −50 dBm0 to −40 dBm0 VFXI = −55 dBm0 to −50 dBm0 Receive Gain Programmed for Maximum 0 dBm0 Test Level (All 1’s in Gain Register). Apply 0 dBm0 PCM Code to DR0 or DR1. Measure VFRO. TA = 25˚C TA = 25˚C, VCC = 5V, VBB = −5V Programmed Gain from 0 dB to 19 dB (0 dBm0 Levels of 1.964 Vrms to 0.220 Vrms) Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.218 Vrms to 0.105 Vrms) Note: ± 0.1 dB min/max is available as a selected part. Min Typ Max Units AMPLITUDE RESPONSE −0.1 −0.15 0.1 0.15 dB dB −0.2 −0.4 −1.2 0.2 0.4 1.2 dB dB dB GRA Receive Gain Absolute Accuracy −0.15 0.15 dB GRAG Receive Gain Variation with Programmed Gain −0.1 0.1 dB −0.3 0.3 dB GRAT Receive Gain Variation with Temperature Measured Relative to GRA. VCC = 5V, VBB = −5V. Minimum Gain < GR < Maximum Gain −40˚C to +85˚C (TP3070-X) −0.1 −0.15 0.1 0.15 dB dB GRAF Receive Gain Variation with Frequency Relative to 1015.625 Hz, (Note 15) DR0 or DR1 = 0 dBm0 code. Minimum Gain < GR < Maximum Gain f = 200 Hz f = 300 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz GR = 0 dB, DR0 = 0 dBm0 Code, GX = 0 dB (Note 15) f = 296.875 Hz f = 1875.00 Hz f = 2906.25 Hz f = 2984.375 Hz f = 3406.250 Hz f = 3984.375 Hz −0.25 −0.15 −0.7 0.15 0.15 0.0 −14 dB dB dB dB −0.15 −0.15 −0.15 −0.15 −0.74 0.15 0.15 0.15 0.15 0.0 −13.5 dB dB dB dB dB dB www.national.com 18 Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol GRAL Parameter Receive Gain Variation with Signal Level Conditions Sinusoidal Test Method. Reference Level = 0 dBm0. DR0 = −40 dBm0 to +3 dBm0 DR0 = −50 dBm0 to −40 dBm0 DR0 = −55 dBm0 to − 50 dBm0 DR0 = 3.1 dBm0 RL = 600Ω, GR = −0.5 dB RL = 300Ω, GR = −1.2 dB ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA Tx Delay, Absolute f = 1600 Hz DXR Tx Delay, Relative to DXA f = 500–600 Hz f = 600–800 Hz f = 800–1000 Hz f = 1000–1600 Hz f = 1600–2600 Hz f = 2600–2800 Hz DRA DRR Rx Delay, Absolute Rx Delay, Relative to DRA f = 2800–3000 Hz f = 1600 Hz f = 500–1000 Hz f = 1000–1600 Hz f = 1600–2600 Hz f = 2600–2800 Hz f = 2800–3000 Hz NOISE NXC NXP NRC NRP NRS PPSRX Transmit Noise, C Message Weighted, µ-law Selected Transmit Noise, P Message Weighted, A-law Selected Receive Noise, C Message Weighted, µ-law Selected Receive Noise, P Message Weighted, A-law Selected Noise, Single Frequency Positive Power Supply Rejection, Transmit NPSRX Negative Power Supply Rejection, Transmit f = 0 kHz to 100 kHz, Loop Around Measurement, VFXI = 0 Vrms VCC = 5.0 VDC + 100 mVrms f = 0 kHz–4 kHz (Note 13) f = 4 kHz–50 kHz VBB = −5.0 VDC + 100 mVrms f = 0 kHz–4 kHz (Note 13) f = 4 kHz–50 kHz 36 30 36 30 −53 dBm0 (Note 12) All ‘1’s in Gain Register (Note 12) All ‘1’s in Gain Register PCM Code is Alternating Positive and Negative Zero PCM Code Equals Positive Zero −82 −79 dBm0p 8 11 dBrnC0 −74 −67 dBm0p 12 15 dBrnC0 −40 −30 90 125 175 −0.2 −0.4 −1.2 −0.2 −0.2 0.2 0.4 1.2 0.2 0.2 315 220 145 75 40 75 105 155 200 dB dB dB dB dB µs µs µs µs µs µs µs µs µs µs µs µs µs µs Min Typ Max Units AMPLITUDE RESPONSE dBC dBC dBC dBC 19 www.national.com Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol NOISE PPSRR Positive Power Supply Rejection, Receive PCM Code Equals Positive Zero VCC = 5.0 VDC + 100 mVrms Measure VFRO f = 0 Hz–4000 Hz f = 4 kHz–25 kHz f = 25 kHz–50 kHz NPSRR Negative Power Supply Rejection, Receive PCM Code Equals Positive Zero VBB = −5.0 VDC + 100 mVrms Measure VFRO f = 0 Hz–4000 Hz f = 4 kHz–25kHz f = 25 kHz–50 kHz SOS Spurious Out-of-Band Signals at the Channel Output 0 dBm0, 300 Hz to 3400 Hz Input PCM Code Applied at DR0 (or DR1) 4600 Hz–7600 Hz 7600 Hz–8400 Hz 8400 Hz–50,000 Hz DISTORTION STDX STDR Signal to Total Distortion Transmit or Receive Half-Channel, µ-law Selected Sinusoidal Test Method Level = 3.0 dBm0 = 0 dBm0 to − 30 dBm0 = −40 dBm0 = −45 dBm0 STDRL Signal to Total Distortion Receive with Resistive Load SFDX SFDR IMD Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion Transmit or Receive Two Frequencies in the Range 300 Hz–3400 Hz −41 dB −46 dB Sinusoidal Test Method Level = +3.1 dBm0 RL = 600Ω, GR = −0.5 dB RL = 300Ω, GR = −1.2 dB 33 33 −46 dBC dBC dB 33 36 30 25 dBC dBC dBC dBC −30 −40 −30 dB dB dB 36 40 36 dBC dB dB 36 40 36 dBC dB dB Parameter Conditions Min Typ Max Units www.national.com 20 Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5V ± 5%, VBB = −5V ± 5%; TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f = 1015.625 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol CROSSTALK CTX-R Transmit to Receive Crosstalk, 0 dBm0 Transmit Level Receive to Transmit Crosstalk, 0 dBm0 Receive Level f = 300 Hz–3400 Hz DR = Idle Code f = 300 Hz–3400 Hz (Note 13) −90 −70 dB −90 −75 dB Parameter Conditions Min Typ Max Units CTR-X Note 12: Measured by grounded input at VFXI. Note 13: PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI. Note 14: A signal is Valid if it is above VIHor below VIL and Invalid if it is between VIL and VIH. For the purposes of this specification the following conditions apply: a) All input signals are defined as: VIL = 0.4V, VIH = 2.7V, tR < 10 ns, tF < 10 ns. b) tR is measured from VIL to VIH. tF is measured from VIH to VIL. c) Delay Times are measured from the input signal Valid to the output signal Valid. d) Setup Times are measured from the data input Valid to the clock input Invalid. e) Hold Times are measured from the clock signal Valid to the data input Invalid. f) Pulse widths are measured from VIL to VIL or from VIH to VIH. Note 15: A multi-tone test technique is used. 21 www.national.com Definitions and Timing Conventions DEFINITIONS VIH VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nominal timing, (i.e., not minimum setup and hold times or output strobes), with the high level of all driving signals set to VIH and maximum supply voltages applied to the device. VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero to the device. This parameter is measured in the same manner as VIH but with all driving signal low levels set to VIL and minimum supply voltages applied to the device. VOH is the minimum D.C. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. Pulse Width Low pulse widths are measured from VIH to VIH. The low pulse width is designated as tWzzL, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from VIL to VIL. Setup times are designated as tSwwxx, where ww represents the mnemonic of the input signal whose setup time is being specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold times are designated as THwwxx, where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe input represented by the mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay times are designated as TDxxyy[ IHIL], where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications section of this datasheet. Setup Time VIL Hold Time VOH Delay Time VOL is the maximum D.C. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of input voltages between VIL and VIH. Valid Signal A signal is Valid if it is in one of the valid logic states. (i.e., above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. Invalid signal A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the threshold region. TIMING CONVENTIONS For the purposes of this timing specification the following conventions apply. Input Signals All input signals may be characterized as: VL = 0.4V, VH = 2.4V, tR < 10 ns, tF < 10 ns. The period of the clock signal is designated as tPxx where xx represents the mnemonic of the clock signal being specified. Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise time is being specified. tRyy is measured from VIL to VIH. Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall time is being specified. tFyy is measured from VIH to VIL. VOL Period Rise Time Fall Time Pulse Width High The high pulse width width is designated as tWzzH, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. 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