TP5088

TP5088 DTMF Generator for Binary Data October 1991 TP5088 DTMF Generator for Binary Data General Description This CMOS device provides low cost tone-dialing capability in microprocessor-controlled telephone applications 4-bit binary data is decoded directly without the need for conversion to simulated keyboard inputs required by standard DTMF generators With the TONE ENABLE input low the oscillator is inhibited and the device is in a low power idle mode On the low-to-high transition of TONE ENABLE data is latched into the device and the selected tone pair from the standard DTMF frequencies is generated An open-drain N-channel transistor provides a MUTE output during tone generation Features Y Y Y Y Y Y Y Y Y Y Direct microprocessor interface Binary data inputs with latches Generates 16 standard tone pairs On-chip 3 579545 MHz crystal-controlled oscillator Better than 0 64% frequency accuracy High group pre-emphasis Low harmonic distortion MUTE output interfaces to speech network Low power idle mode 3 5V – 8V operation Block Diagram TL H 5004 – 1 Crystal Specification Parallel Resonant 3 579545 MHz RS s 150X L e 100 mH C0 e 5 pF C1 e 0 02 pF C1995 National Semiconductor Corporation TL H 5004 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDDbVSS) MUTE Voltage Maximum Voltage at Any Other Pin 12V 12V VDD a 0 3V to VSS b 0 3V Operating Temperature TA Storage Temperature Maximum Power Dissipation b 30 C to a 70 C b 55 C to a 150 C 500 mW Electrical Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VDD e 3 5V to 8V TA e 0 C to a 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Parameter Minimum Supply Voltage VDD (min) Minimum Supply Voltage for Data Input TONE ENABLE and MUTE Logic Functions Operating Current Idle Generating Tones Input Pull-Up Resistance D0 – D3 TONE ENABLE Input Low Level TONE ENABLE D0–D3 Input High Level TONE ENABLE D0–D3 MUTE OUT Sink Current (TONE ENABLE LOW) MUTE OUT Leakage Current (TONE ENABLE HIGH) Output Amplitudes Low Group High Group Mean Output DC Offset High Group Pre-Emphasis Dual Tone Total Harmonic Distortion Ratio Start-Up Time (to 90% Amplitude) tOSC Data Set-Up Time tS (Figure 2 ) Data Hold Time tH Data Duration tW VDD e 5V VDD e 5V VDD e 5V 100 280 600 1 MHz Bandwidth VDD e 5V RL e 240X VDD e 3 5V Vo e 0 5V VDD e 3 5V Vo e VDD RL e 240 X VDD e 3 5V TA e 25 C VDD e 3 5V VDD e 8V 22 b 20 Conditions Generating Tones Min 35 2 Typ Max Units V V RL e % D0 – D3 Open VDD e 3 5V Mute Open 55 15 100 50 350 25 mA mA kX kX 0 2 VDD 0 8 VDD 04 1 130 180 170 230 12 36 27 32 220 310 V V mA mA mVrms mVrms V V dB dB 4 ms ns ns ns Note 1 RL is the external load resistor connected from TONE OUT to VSS 2 Connection Diagram Dual-In-Line Package TL H 5004 – 2 Top View Order Number TP5088WM or TP5088N See NS Package M14B or N14A Functional Description With the TONE ENABLE pin pulled low the device is in a low power idle mode with the oscillator inhibited and the output transistor turned off Data on inputs D0–D3 is ignored until a rising transition on TONE ENABLE Data meeting the timing specifications is latched in the oscillator and output stage are enabled and tone generation begins The decoded data sets the high group and low group programmable counters to the appropriate divide ratios These counters sequence two ratioed-capacitor D A converters through a series of 28 equal duration steps per sine wave cycle On-chip regulators ensure good stability of tone amplitudes with variations in supply voltage and temperature The two tones are summed by a mixer amplifier with preemphasis applied to the high group tone The output is an NPN emitter-follower requiring the addition of an external load resistor to VSS Table I shows the accuracies of the tone output frequencies and Table II is the Functional Truth Table TABLE I Output Frequency Accuracy Tone Group Low Group fL High Group fH Standard DTMF (Hz) 697 770 852 941 1209 1336 1477 1633 Tone Output Frequency 694 8 770 1 852 4 940 0 1206 0 1331 7 1486 5 1639 0 % Deviation from Standard b 0 32 a 0 02 a 0 03 b 0 11 b 0 24 b 0 32 a 0 64 a 0 37 3 579545 MHz A-cut crystal (NTSC TV color-burst) is needed between pins 6 and 7 Load capacitors and a feedback resistor are included on-chip for good start-up and stability The oscillator is stopped when the TONE ENABLE input is pulled to logic low TONE ENABLE Input (Pin 2) This input has an internal pull-up resistor When TONE ENABLE is pulled to logic low the oscillator is inhibited and the tone generators and output transistor are turned off A low to high transition on TONE ENABLE latches in data from D0 – D3 The oscillator starts and tone generation continues until TONE ENABLE is pulled low again MUTE (Pin 8) This output is an open-drain N-channel device that sinks current to VSS when TONE ENABLE is low and no tones are being generated The device turns off when TONE ENABLE is high D0 D1 D2 D3 (Pins 9 10 11 12) These are the inputs for binary-coded data which is latched in on the rising edge of TONE ENABLE Data must meet the timing specifications of Figure 2 At all other times these inputs are ignored and may be multiplexed with other system functions TONE OUT (Pin 14) This output is the open emitter of an NPN transistor the collector of which is connected internally to VDD When an external load resistor is connected from TONE OUT to VSS the output voltage on this pin is the sum of the high and low group tones superimposed on a DC offset When not generating tones this output transistor is turned off to minimize the device idle current SINGLE TONE ENABLE (Pin 3) This input has an internal pull-up resistor When pulled to VSS the device is in single tone mode and only a single tone will be generated at pin 14 (for testing purposes) For normal operation leave this pin open-circuit or pull to VDD GROUP SELECT (Pin 4) This pin is used to select the high group or low group frequency when the device is in single tone mode It has an internal pull-up resistor Leaving this pin open-circuit or pulling it to VDD will generate the high group while pulling to VSS will generate the low group frequency at the TONE OUT pin Pin Descriptions VDD (Pin 1) This is the positive supply to the device referenced to VSS The collector of the TONE OUT transistor is also connected to this pin VSS (Pin 5) This is the negative voltage supply All voltages are referenced to this pin OSC IN OSC OUT (Pins 6 and 7) All tone generation timing is derived from the on-chip oscillator circuit A low-cost 3 TABLE II Functional Truth Table Keyboard Equivalent X 1 2 3 4 5 6 7 8 9 0 Data Inputs D3 X 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 X 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 X 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TONE ENABLE 0 L L L L L L L L L L L L L L L L TONES OUT fL (Hz) 0V 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 fH(Hz) 0V 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 0V OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC MUTE A B C D Timing Diagram Typical Application TL H 5004 – 4 TL H 5004 – 3 Adjust RE for desired tone amplitude FIGURE 2 FIGURE 3 4 Physical Dimensions inches (millimeters) Order Number TP5088WM NS Package Number M14B 5 TP5088 DTMF Generator for Binary Data Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line (N) Order Number TP5088N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications