NTE1853

NTE1853 Integrated Circuit Digital Filter for Compact Disc Digital Audio System Features: D 16–Bit Serial Data Input (Two’s Complement) D Interpolated Data Replaces Erroneous Data Samples D –12dB Attenuation via the Active Low Attenuation Input Control (ATSB) D Smoothed Trasitions Before and After Muting D Two Identical Finite Impulse Response Transversal Filters each with a Sampling Rate of Four Times that of the Normal Digital Audio Data D Digital Audio Output of 32–Bit Words Transmitted in Biphasemark Code Applications: D Compact Disc Digital Audio System D Digital Filter Absolute Maximum Ratings: Supply Voltage Range (Pin24), VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +7.0V Maximum Input Voltage Range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VDD+0.5V Electrostatic Handling (Note 2), VES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1000V to +1000V Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Note 1. All outputs are short–circuit protected except the crystal oscillator output. Note 2. Equivalent to discharging a 100pF capacitor through a 1.5Ω series resistor with a rise time of 15ns. DC and AC Electrical Characteristics: (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter Supply Voltage (Pin24) Supply Current (Pin24) Symbol VDD IDD Test Conditions Min 4.5 – Typ 5.0 180 Max 5.5 – Unit V mA DC and AC Electrical Characteristics (Cont’d): (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter WSAB, DAAB Input Voltage, Low Input Voltage, High Input Leakage Current Input Capacitance EFAB, SDAB (Note 1) Input Voltage, Low Input Voltage, High Input Leakage Current Input Capacitance CLAB, SCAB, ATSB, MUSB (Note 2) Input Voltage, Low Input Voltage, High Input Leakage Current Input Capacitance Output XOUT Mutual Conductance at 100kHz Small–Signal Voltage Gain Input Capacitance Feedback Capacitance Output Capacitance Input Leakage Current Slave Clock Mode Input Voltage (Peak to Peak) Input Voltage, Low Input Voltage, High Input Rise Time Input Fall Time Input High Time at 2V (Relative to Clock Period) VI(P–P) VIL VIH tR tF tHIGH Note 3 Note 3 Note 3 Note 4 Note 4 3.0 0 3.0 – – 35 – – – – – – VDD+0.5 1 VDD+0.5 20 20 65 V V V ns ns % GM AV CI CFB CO ILI AV = GM x RO 1.5 3.5 – – – –10 – – – – – 0 – – 10 5 10 +10 mA/V V/V pF pF pF µA VIL VIH ILI CI VI = 0V VI = VDD –0.3 2.0 –30 – – – – – – – +0.8 VDD+0.5 – +10 7 V V µA µA pF VIL VIH ILI CI VI = 0V VI = VDD –0.3 2.0 –10 – – – – – – – +0.8 VDD+0.5 – +50 7 V V µA µA pF VIL VIH ILI CI –0.3 2.0 –10 – – – – – +0.8 VDD+0.5 +10 7 V V µA pF Symbol Test Conditions Min Typ Max Unit Note 1. Inputs EFAB and SDAB both have internal pull–downs. Note 2. Inputs CLAB, SCAB, ATSB, and MUSB have internal pull–ups. Note 3. The minimum peak–to–peak voltage can be reduced to 2V if the output XSYS is not being used. Similarly VIH can be reduced to 2.4V (Min). All other levels remain the same. Note 4. Reference levels = 10% and 90%. DC and AC Electrical Characteristics (Cont’d): (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter DABD, CLBD, WSBD Output Voltage, Low Output Voltage, High Load Capacitance XSYS (Note 5) Output Voltage, Low Output Voltage, High Load Capacitance DOBM Voltage Across a 75Ω Load via Attenuator (Peak–to–Peak) VL(P–P) 0.4 – 0.6 V VOL VOH CL 0 2.4 – – – – 0.4 VDD 50 V V pF VOL VOH CL IOL = 1.6mA –IOH = 0.2mA 0 2.4 – – – – 0.4 VDD 50 V V pF Symbol Test Conditions Min Typ Max Unit Note 5. The output current conditions are dependent on the drive conditions. When a crystal oscillator is being used, the output current capability is IOL = +1.6mA; IOH = –0.2mA. But if a slave input is being used, the output currents are reduced to IOL = +0.2mA; IOH = –0.2mA. Timing Characteristics: Parameter Operating Frequency (XTAL) Inputs SCAB, CLAB (Note 6) SCAB Clock Frequency (Burst Clock) CLAB Clock Frequency Clock Low Time Clock High Time Input Rise Time Input Fall Time DAAB, WSAB, EFAB (Note 8) Data Setup Time Data Hold Time Input Rise Time Input Fall Time tSU, tDAT tHD, tDAT tR tF 40 0 – – – – – – – – 20 20 ns ns ns ns fSCAB fCLAB tCKL tCKH tR tF Note 7 – – – 110 110 – – 2.8224 2.8224 1.4112 – – – – – – – – – 20 20 MHz MHz MHz ns ns ns ns Symbol fXTAL Test Conditions Min 10.16 Typ 11.2896 Max 12.42 Unit MHz Note 6. Reference levels = 0.8V and 2.0V Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock) under typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4 or 1/8 of the system clock frequency. Note 8. Input setup and hold times measured with respect to clock input from A–chip (CLAB). Reference levels = 0.8V and 2.0V. Timing Characteristics (Cont’d): Parameter SDAB (Note 9) Subcode Data Setup Time Subcode Data Hold Time Input Rise Time Input Fall Time Outputs WSBD (Note 6 & Note 10) Word Select Setup Time Word Select Hold Time WSBD (Note 6) Output Rise Time Output Fall Time DABD (Note 6 & Note 10) Data Setup Time Data Hold Time Outputs (Cont’d) DABD (Note 6) Output Rise Time Output Fall Time CLBD (Note 6 & Note 10) Clock Period Clock Low Time Clock High Time Clock Setup Time Clock Hold Time CLBD (Note 6) Output Rise Time Output Fall Time DABD (Note 6 & Note 11) Data Setup Time Data Hold Time tSU, tDATBD tHD, tDATBD 40 60 – – – – ns ns tR tF – – – – 20 20 ns ns tCK tCKL tCKH tSU, tCLD tHD, tCLD 161 65 65 40 0 177 – – – – 197 – – – – ns ns ns ns ns tR tF – – – – 20 20 ns ns tSU, tDATD tHD, tDATD 40 0 – – – – ns ns tR tF – – – – 20 20 ns ns tSU, tWS tHD, tWS 40 0 – – – – ns ns tSU, tSDAT tHD, tSDAT tR tF 40 0 – – – – – – – – 20 20 ns ns ns ns Symbol Test Conditions Min Typ Max Unit Note 6. Reference levels = 0.8V and 2.0V Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock) under typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4 or 1/8 of the system clock frequency. Note 8. Input setup and hold times measured with respect to clock input from A–chip (CLAB). Reference levels = 0.8V and 2.0V. Note 9. Input setup and hold times measured with respect to subcode burst clock input from A–chip (SCAB). Reference levels = 0.8V and 2.0V. Note10. Output setup and hold times measured with respect to system clock output (XSYS). Note 11. Output setup and hold times measured with respect to clock output (CLBD). Timing Characteristics (Cont’d): Parameter WSBD (Note 6 & Note 11) Word Select Setup Time Word Select Hold Time DOBM (Note 12) Output Rise Time Output Fall Time Data Bit 0 Pulse Width High Data Bit 0 Pulse Width Low Data Bit 1 Pulse Width High Data Bit 1 Pulse Width Low XSYS Output Rise Time Output Fall Time Output High Time at 2V (Relative to Clock Period) tR tF tHIGH Note 6 Note 6 – – 35 – – – 20 20 65 ns ns % tR tF tHIGH(0) tLOW(0) tHIGH(1) tLOW(1) – – – – – – – – 354 354 177 177 20 20 – – – – ns ns ns ns ns ns tSU, tDATWSD tSU, tDATWSD 40 60 – – – – ns ns Symbol Test Conditions Min Typ Max Unit Note 6. Reference levels = 0.8V and 2.0V Note 11. Output setup and hold times measured with respect to clock output (CLBD). Note12. Output rise and fall times measured between the 10% and 90% levels; the data bit pulse width measured at the 50% level. Pin Connection Diagram WSAB 1 CLAB 2 DAAB 3 EFAB 4 N.C. 5 SCAB 6 SDAB 7 N.C. 8 XSYS 9 XOUT 10 XIN 11 VSS 12 24 VDD 23 MUSB 22 ATSB 21 N.C. 20 N.C. 19 N.C. 18 WSDB 17 N.C. 16 CLBD 15 DABD 14 DOBM 13 TEST 24 13 1 12 1.300 (33.02) Max .225 (5.73) Max .520 (13.2) .100 (2.54) 1.100 (27.94) .600 (15.24) .126