NTE2057

NTE2057 Integrated Circuit Dual 16–Bit Digital–to–Analog Converter for CD and DAT Players Description: The NTE2057 is a monolithic integrated dual 16–bit digital –to–analog converter (DAC) in a 28–Lead DIP type package designed for use in Hi–Fi digital audio equipment such as compact disc players, digital tape, or cassette recorders. Features: D Selectable Input Format: Offset Binary or Two’s Complement D Internal Timing and Control Circuit D TTL–Compatible Digital Inputs D High Maximum Input Bit Rate and Fast Settling Time D 6Mbits/s Data Rate D Low Linearity Error (1/2 LSB typ) D Fast Settling (1µs typ) Applications: D Compact Disc Players D Digital Audio Tape, and Cassette Recorders and Players D Waveform Generation Absolute Maximum Ratings: Supply Voltage Range, VDD Pin28 (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Pin26 (VDD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7V Pin15 (VDD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –17V Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Electrostatic Handling (Note 1), VES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1000 to +1000V Note 1. Discharging a 250pF capacitor through a 1kΩ series resistor. DC and AC Electrical Characteristics: (VDD = +5V, VDD1 = –5V, VDD2 = –15V, TA = +25°C unless otherwise specified) Parameter Supply Supply Voltage Range Pin28 Pin26 Pin15 Supply Currents Pin28 Pin26 Pin15 Resolution Inputs Input Current (Pin3, Pin4) Digital Inputs Low Digital Inputs High Input Frequency At Clock Input (Pin4) At Clock Input (Pin2) At Data Inputs (Pin3, Pin4) At Word Select Input (Pin1) Input Capacitance of Digital Inputs Oscillator Oscillator Frequency w/Internal Capacitor Analog Outputs (AOL, AOR) Output Voltage Compliance Full–Scale Current Zero–Scale Current Full–Scale Temperature Coefficient Linearity Error Integral Linearity Error Differential Signal–to–Noise Ratio + THD Setting Time to ±1 LSB Channel Separation Unbalance Between Outputs Time Delay Between Outputs Power Supply Ripple Rejection (Note 3) VCC IFS ±IZS TCFS E1 ED1 S/N tCS T ∆IFS tD RR VDD = +5V VDD1 = –5V VDD2 = –15V TA = –20° to +70°C TA = +25°C TA = –20° to +70°C TA = +25°C TA = –20° to +70°C Note 2 TBD 3.4 – – – – – – 90 – 80 – – – – – – 4.0 TBD ±200 0.5 TBD 0.5 TBD 95 1 TBD 0.1 – TBD TBD TBD TBD 4.6 – – – – 1.0 – – – – 0.2 1 – – – mV mA nA ppm/°C LSB LSB LSB LSB dB µs dB dB µs dB dB dB fOSC 150 200 250 kHz IIL IIH fSCK fBCK fDAT fWS CI < 0.8V > 2.0V – – – – – – – – – – – – – 12 TBD TBD 6 – – – – mA µA MHz MHz MHz kHz pF VDD –VDD1 –VDD2 IDD –IDD1 –IDD2 4.0 4.5 14.0 – – – – 5.0 5.0 15.0 45 45 25 16 6.0 6.0 16.0 60 75 60 – V V V mA mA mA bits Symbol Test Conditions Min Typ Max Unit Note 2. Signal–to–noise ratio + THD with 1kHz full–scale sine wave generated at a sampling rate of 176.4kHz. Note 3. VRIPPLE = 1% of supply voltage and fRIPPLE = 100Hz. DC and AC Electrical Characteristics (Cont’d): (VDD = +5V, VDD1 = –5V, VDD2 = –15V, TA = +25°Cunless otherwise specified) Parameter Analog Outputs (AOL, AOR) (Cont’d) Signal–to–Noise Ratio at Bipolar Zero Timing Rise Time Fall Time Bit Clock Cycle Time Bit Clock High Time Bit Clock Low Time Bit Clock Fall Time to Latch Rise Time Bit Clock Rise Time to Latch Fall Time Data Setup Time to Bit Clock Data Hold Time to Bit Clock Data Setup Time to System Clock Word Select Hold Time to System Clock Word Select Setup Time to System Clock Bit Clock Fall Time to System Clock Rise Time System Clock Rise Time to Bit Clock Fall Time System Clock Fall Time to Bit Clock Rise Time Bit Clock Rise Time to System Clock Fall Time Latch Enable Low Time Latch Enable High Time tR tF tCY tHB tLB tFBRL tRBFL tSDB tHDB tSDS tHWS tSWS tFBRS tRSFB tFSRB tRBFS tLLE tHLE Pin Connection Diagram LE/WS 1 BCK 2 Data l/Data Data R/SCK AGND 3 4 5 28 VDD 27 OB/TWC 26 VDD 1 25 AOL 24 Decoupling 23 Decoupling 22 Decoupling 21 Decoupling 20 Decoupling 19 Decoupling 18 Decoupling 17 CCLK 16 CCLK 15 VDD 2 – – 160 48 48 0 0 32 0 32 0 32 32 32 50 0 20 32 – – – – – – – – – – – – – – – – – – 35 35 – – – – – – – – – – – – – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns S/N – –100 – dB Symbol Test Conditions Min Typ Max Unit AOR 6 Decoupling 7 Decoupling 8 Decoupling 9 Decoupling 10 Decoupling 11 Decoupling 12 Decoupling 13 DGND 14 14 1 15 28 1.469 (37.32) Max .540 (13.7) .250 (6.35) .100 (2.54) 1.300 (33.02) .122 (3.1) Min .600 (15.24)