NTE4012BT

NTE4012B & NTE4012BT Integrated Circuit CMOS, Quad 4−Input NAND Gate Description: The NTE4012B (14−Lead DIP) and NTE4012BT (SOIC−14) are quad 4−input NAND gate devices constructed with P−Channel and N−Channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. Features: D Supply Voltage Range: 3Vdc to 18Vdc D All Outputs Buffered D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range D Double Diode Protection on All Inputs Absolute Maximum Ratings: (Voltages referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (DC or Transient), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V Output Voltage (DC or Transient), Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V Input Current (DC or Transient, Per Pin), Iin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Current (DC or Transient, Per Pin), Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Power Dissipation (Per Package), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Temperature Derating (from +65° to +125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7.0mW/°C Storage Temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Lead Temperature (During Soldering, 8sec max), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc 5.0 −3.0 − −2.4 −4.2 − −1.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.64 − −0.51 −0.88 − −0.36 − mAdc (VOH = 9.5Vdc) 10 −1.6 − −1.3 −2.25 − −0.9 − mAdc (VOH = 13.5Vdc) 15 −4.2 − −3.4 −8.8 − −2.4 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 μAdc 10 − 0.5 − 0.0010 0.5 − 15 μAdc 15 − 1.0 − 0.0015 1.0 − 30 μAdc Total Supply Current (Dynamic plus Quiescent, Per Gate, CL = 50pF, Note 3, Note 4) IT 5.0 IT = (0.3μA/kHz) f + IDD/N μAdc 10 IT = (0.6μA/kHz) f + IDD/N μAdc 15 IT = (0.8μA/kHz) f + IDD/N μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + (CL −50) Vfk where: IT is in μH (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) VDD Vdc Min Typ Max Unit 5.0 − 100 200 ns tTLH = (0.60ns/pf) CL + 20ns 10 − 50 100 ns tTLH = (0.40ns/pf) CL + 20ns 15 − 40 80 ns 5.0 − 100 200 ns tTHL = (0.60ns/pf) CL + 20ns 10 − 50 100 ns tTHL = (0.40ns/pf) CL + 20ns 15 − 40 80 ns 5.0 − 160 300 ns tPLH, tPHL = (0.36ns/pf) CL + 47ns 10 − 65 130 ns tPLH, tPHL = (0.26ns/pf) CL + 37ns 15 − 50 100 ns Parameter Symbol Output Rise Time tTLH = (1.35ns/pf) CL + 33ns tTLH Output Fall Time tTHL = (1.35ns/pf) CL + 33ns tTHL Propagation Delay Time tPLH, tPHL = (0.90ns/pf) CL + 115ns tPLH. tPHL Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Logic Diagram 2 3 4 5 9 10 11 12 1 13 VDD = Pin14 VSS = Pin7 Pin Connection Diagram J = ABCD 1 14 VDD A 2 B 3 13 K = EFGH 12 H C 4 11 G D 5 10 F N.C. 6 VSS 7 9 E 8 N.C. NTE4012B 14 8 1 7 .300 (7.62) .600 (15.24) .200 (5.08) Max .100 (2.45) .099 (2.5) Min .785 (19.95) Max NTE4012BT .340 (8.64) .050 (1.27) 14 8 1 7 .198 (5.03) .154 (3.91) .236 (5.99) 016 (.406) 061 (1.53) .006 (.152) NOTE: Pin1 on Beveled Edge