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NTE4027B

NTE4027B

  • 厂商:

    NTE

  • 封装:

    DIP-16

  • 描述:

    IC FF JK TYPE DUAL 1BIT 16DIP

  • 数据手册
  • 价格&库存
NTE4027B 数据手册
NTE4027B & NTE4027BT Integrated Circuit CMOS, Dual J−K Flip−Flop Description: The NTE4027B (16−Lead DIP) and NTE4027BT (SOIC−16) dual J−K flip−flops have independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control, register, or toggle functions. Features: D Diode Protection on All Inputs D Supply Voltage Range: 3Vdc to 18Vdc D Logic Swing Independent of Fanout D Logic Edge−Clocked Flip−Flop Design — Logic State is retained Indefinitely with Clock Level either High or Low; Information is Transferred to the Output Only on the Positive−Going Edge o the Clock Pulse D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range Absolute Maximum Ratings: (Voltages referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (DC or Transient), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V Output Voltage (DC or Transient), Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V Input Current (DC or Transient, Per Pin), Iin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Current (DC or Transient, Per Pin), Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Power Dissipation (Per Package), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Temperature Derating (from +65° to +125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7.0mW/°C Storage Temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Lead Temperature (During Soldering, 8sec max), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc 5.0 −3.0 − −2.4 −4.2 − −1.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.64 − −0.51 −0.88 − −0.36 − mAdc (VOH = 9.5Vdc) 10 −1.6 − −1.3 −2.25 − −0.9 − mAdc (VOH = 13.5Vdc) 15 −4.2 − −3.4 −8.8 − −2.4 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 1.0 − 0.002 1.0 − 30 μAdc 10 − 2.0 − 0.004 2.0 − 60 μAdc 15 − 4.0 − 0.006 4.0 − 120 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on all outputs, all buffers switching, Note 3, Note 4) IT 5.0 IT = (0.8μA/kHz) f + IDD μAdc 10 IT = (1.6μA/kHz) f + IDD μAdc 15 IT = (2.4μA/kHz) f + IDD μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + (CL −50) Vfk where: IT is in μA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) Parameter Output Rise and Fall Time tTLH, tTHL = (1.5ns/pf) CL + 25ns tTLH, tTHL = (0.75ns/pf) CL + 12.5ns tTLH, tTHL = (0.55ns/pf) CL + 9.5ns Propagation Delay Time Clock to Q, Q tPLH, tPHL = (1.7ns/pf) CL + 90ns tPLH, tPHL = (0.66ns/pf) CL + 42ns tPLH, tPHL = (0.5ns/pf) CL + 25ns Set to Q, Q tPLH, tPHL = (1.7ns/pf) CL + 90ns tPLH, tPHL = (0.66ns/pf) CL + 42ns tPLH, tPHL = (0.5ns/pf) CL + 25ns Reset to Q, Q tPLH, tPHL = (1.7ns/pf) CL + 265ns tPLH, tPHL = (0.66ns/pf) CL + 67ns tPLH, tPHL = (0.5ns/pf) CL + 50ns Setup Times Hold Times Clock Pulse Width Clock Pulse Frequency Symbol tTLH, tTHL tPLH. tPHL tsu th tWH, tWL fcl Clock Pulse Rise and Fall Time tTLH, tTHL Removal Times Set trem Reset Set and Reset Pulse Width tWH VDD Vdc Min Typ Max Unit 5.0 10 15 − − − 100 50 40 200 100 80 ns ns ns 5.0 10 15 − − − 175 75 50 350 150 100 ns ns ns 5.0 10 15 − − − 175 75 50 350 150 100 ns ns ns 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 − − − 140 50 35 140 50 35 330 110 75 − − − − − − 350 100 75 70 25 17 70 25 17 165 55 38 3.0 9.0 13.0 − − − 450 200 150 − − − − − − − − − 1.5 4.5 6.5 15 5.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz μs μs μs 5.0 10 15 5.0 10 15 5.0 10 15 90 45 35 50 25 20 250 100 70 10 5 3 −30 −15 −10 125 50 35 − − − − − − − − − ns ns ns ns ns ns ns ns ns Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Truth Table Inputs C[ X X X J 1 X 0 X 1 X X X X K X 0 X 1 1 X X X X Outputs * S 0 0 0 0 0 0 1 0 1 R 0 0 0 0 0 0 0 1 1 Qn ] 0 1 0 1 QO X X X X X = Don’t Care [ = Level Change ] = Present State * = Next State Pin Connection Diagram Q2 1 16 VDD Q2 2 Clock 2 3 15 Q1 14 Q1 Reset 2 4 13 Clock 1 K2 5 12 Reset 1 J2 6 11 K1 Set 2 7 10 J1 VSS 8 9 Set 1 Qn + 1 1 1 0 0 QO Qn 1 0 1 Qn + 1 0 0 1 1 QO Qn 0 1 1 NTE4027B 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .099 (2.5) Min .700 (17.78) NTE4027BT .390 (9.9) 16 9 1 8 .050 (1.27) .236 (5.99) .154 (3.91) 016 (.406) 061 (1.53) .006 (.152) NOTE: Pin1 on Beveled Edge .198 (5.03)
NTE4027B 价格&库存

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