NTE4069T

NTE4069 and NTE4069T Integrated Circuit CMOS, Hex Inverter, High Voltage Type Description: The NTE4069 (14−Lead DIP) and NTE4069T (SOIC−14) are hex inverters constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays. Features: D Quiescent Current = 0.5nA Typ/Pkg at 5 Vdc D Noise Immunity = 45% of VDD (Typ) D Supply Voltage Range = 3Vdc to 18Vdc D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range D Double Diode Protection on All Inputs Absolute Maximum Ratings: (Voltages Referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD + 0.5V DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TsA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C Lead Temperature (8−Seconds Soldering), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Note 1. These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation is is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.0 − 2.25 1.0 − 1.0 Vdc (VO = 9.0 or 1.0Vdc) 10 − 2.0 − 4.50 2.0 − 2.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 2.5 − 6.75 2.5 − 2.5 Vdc 5.0 4.0 − 4.0 2.75 − 4.0 − Vdc (VO = 1.0 or 9.0Vdc) 10 8.0 − 8.0 5.50 − 8.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 12.5 − 12.5 8.25 − 12.5 − Vdc 5.0 −3.0 − −2.4 −4.2 − −1.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.64 − −0.51 −0.88 − −0.36 − mAdc (VOH = 9.5Vdc) 10 −1.6 − −1.3 −2.25 − −0.9 − mAdc (VOH = 13.5Vdc) 15 −4.2 − −3.4 −8.8 − −2.4 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 μAdc 10 − 0.5 − 0.0010 0.5 − 15 μAdc 15 − 1.0 − 0.0015 1.0 − 30 μAdc Total Supply Current (Dynamic plus Quiescent, Per Gate, CL = 50pF, Note 3, Note 4) IT 5.0 IT = (0.3μA/kHz) f + IDD/6 μAdc 10 IT = (0.6μA/kHz) f + IDD/6 μAdc 15 IT = (0.8μA/kHz) f + IDD/6 μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 6 x 10−3(CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in volts and f in kHz is input frequency. Note 3. The formulas given are for the typical characteristics only at +25°C. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) Symbol VDD Vdc Min Typ Max Unit tTLH, tTHL 5.0 − 100 200 ns tTLH ,tTHL = (0.60ns/pf) CL + 20ns 10 − 50 100 ns tTLH ,tTHL = (0.40ns/pf) CL + 20ns 15 − 40 80 ns 5.0 − 65 125 ns tPLH, tPHL = (0.36ns/pf) CL + 22ns 10 − 40 75 ns tPLH, tPHL = (0.26ns/pf) CL + 17ns 15 − 30 55 ns Parameter Output Rise and Fall Times tTLH ,tTHL = (1.35ns/pf) CL + 33ns Propagation Delay Time tPLH, tPHL = (0.90ns/pf) CL + 20ns tPLH. tPHL Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Logic Diagram 1 2 3 4 5 6 9 8 11 10 13 12 VDD = Pin14 VSS = Pin7 Pin Connection Diagram A 1 14 VDD G=A 2 B 3 13 F 12 L = F H=B 4 11 E C 5 I=C 6 VSS 7 10 K = E 9 D 8 J=D NTE4069 14 8 1 7 .300 (7.62) .600 (15.24) .200 (5.08) Max .100 (2.45) .099 (2.5) Min .785 (19.95) Max NTE4069T .340 (8.64) .050 (1.27) 14 8 1 7 .198 (5.03) .154 (3.91) .236 (5.99) 016 (.406) 061 (1.53) .006 (.152) NOTE: Pin1 on Beveled Edge