NTE4503B

NTE4503B Integrated Circuit CMOS, Hex 3−State Non−Inverting Buffer Description: The NTE4503B is a hex non−inverting buffer in a 16−Lead DIP type package with 3−state outputs and a high current source and sink capability. The 3−state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input causes the outputs of buffers 5 and 6 to go into a high impedance state. Features: D 3−State Outputs D TTL Compatible − Will Drive One TTL Load Over Full Temperature Range D Supply Voltage Range: 3Vdc to 18Vdc D Symmetrical Turn−On and Turn−Off Delays D Symmetrical Output Rise and Fall Times D Two Disable Controls for Added Versatility Absolute Maximum Ratings: (Voltages referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V DC Current Drain, I Per Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Per Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55° to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Note 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V9in9 and V9out9 be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic level (e.g., either VSS or VDD). Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc 10 − 3.0 − 4.50 3.0 − 3.0 Vdc 15 − 3.75 − 6.75 3.75 − 3.75 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc 10 7.0 − 7.0 5.50 − 7.0 − Vdc 15 11.25 − 11.25 8.25 − 11.25 − Vdc 4.5 −4.3 − −3.6 −5.0 − −2.5 − mAdc (VOH = 2.5Vdc) 5.0 −5.8 − −4.8 −6.1 − −3.0 − mAdc (VOH = 4.6Vdc) 5.0 −1.2 − −1.02 −1.4 − −0.7 − mAdc (VOH = 9.5Vdc) 10 −3.1 − −2.6 −3.7 − −1.8 − mAdc (VOH = 13.5Vdc) 15 −8.2 − −6.8 −14.1 − −4.8 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Noise Immunity (Note 4) “0” Level (VO = 3.6 or 1.4Vdc) VIL (VO = 7.2 or 2.8Vdc) (VO = 11.5 or 3.5Vdc) (VO = 1.4 or 3.6Vdc) “1” Level VIH (VO = 2.8 or 7.2Vdc) (VO = 3.5 or 11.5Vdc) Output Drive Current (VOH = 2.5Vdc) Source (VOL = 0.4Vdc) Sink IOH IOL 4.5 2.2 − 1.8 2.1 − 1.2 − mAdc (VOL = 0.4Vdc) 5.0 2.6 − 2.1 2.3 − 1.3 − mAdc (VOL = 0.5Vdc) 10 6.5 − 5.5 6.2 − 3.8 − mAdc (VOL = 1.5Vdc) 15 19.2 − 16.1 25.0 − 11.2 − mAdc 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Current Iin Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 1.0 − 0.002 1.0 − 30 μAdc 10 − 2.0 − 0.004 2.0 − 60 μAdc 15 − 4.0 − 0.006 4.0 − 120 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on all outputs, all outputs switching, 50% Duty Cycle, Note 3, Note 5) IT Three State Leakage Current ITL 5.0 IT = (2.5μA/kHz) f + IDD μAdc 10 IT = (6.0μA/kHz) f + IDD μAdc 15 IT = (10μA/kHz) f + IDD μAdc 15 − ±0.1 − ±0.00001 ±0.1 − ±3.0 μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. Noise immunity specified for worst−case input combination. Noise margin for both “1” and “0” = 1.0Vdc min @ VDD = 5Vdc 2.0Vdc min @ VDD = 10Vdc 2.5Vdc min @ VDD = 15Vdc Note 5. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 6 x 10−3 (CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in Vdc, f in kHz is input frequency. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) VDD Vdc Min Typ Max Unit 5.0 − 45 90 ns tTLH = (0.3ns/pf) CL + 8ns 10 − 23 45 ns tTLH = (0.2ns/pf) CL + 8ns 15 − 18 35 ns 5.0 − 45 90 ns tTHL = (0.3ns/pf) CL + 8ns 10 − 23 45 ns tTHL = (0.2ns/pf) CL + 8ns 15 − 18 35 ns 5.0 − 75 150 ns tPLH = (0.15ns/pf) CL + 27ns 10 − 35 70 ns tPLH = (0.1ns/pf) CL + 20ns 15 − 25 50 ns 5.0 − 75 150 ns tPHL = (0.15ns/pf) CL + 27ns 10 − 35 70 ns tPHL = (0.1ns/pf) CL + 20ns 15 − 25 50 ns 5.0 − 75 150 ns 10 − 40 80 ns 15 − 35 70 ns 5.0 − 65 130 ns 10 − 25 50 ns 15 − 20 40 ns 5.0 − 80 160 ns 10 − 40 80 ns 15 − 35 70 ns 5.0 − 100 200 ns 10 − 35 70 ns 15 − 25 50 ns Parameter Symbol Output Rise Time tTLH = (0.5ns/pf) CL + 20ns tTLH Output Fall Time tTHL = (0.5ns/pf) CL + 20ns tTHL Turn−Off Delay Time, All Outputs tPLH = (0.3ns/pf) CL + 60ns tPLH Turn−On Delay Time, All Outputs tPHL = (0.3ns/pf) CL + 60ns tPHL 3−State Propagation Delay, Output “1” to High Impedance 3−State Propagation Delay, High Impedance to Output “1” 3−State Propagation Delay, Output “0” to High Impedance 3−State Propagation Delay, High Impedance to Output “0” tPHZ tPZH tPLZ tPZL Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Inn 0 1 X Truth Table Appropriate Disable Input Outn 0 0 0 1 1 High Impedance X = Don’t Care Pin Connection Diagram 16 VDD Disable A 1 D1 2 Q1 3 15 Disable B 14 D6 D2 4 13 Q6 Q2 5 12 D5 D3 6 11 Q5 Q3 7 10 D4 VSS 8 9 Q4 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min