NTE4512B

NTE4512B Integrated Circuit CMOS, 8−Channel Data Selector Description: The NTE4512B is an 8−channel data selector in a 16−Lead DIP type package constructed with MOS P−channel and N−channel enhancement mode devices is a single monolithic structure. This data selector finds primary application in signal multiplexing functions. It may also be used for data routing, digital signal switching, signal gating, and number sequencing generation. Features: D Noise Immunity = 45% of VDD (Typ) D Diode Protection on All Inputs D High Fanout > 50 D Single Supply Operation − Positive or Negative D 3−State Output (Logic “1”, Logic “0”, High Impedance) D Supply Voltage Range: 3Vdc to 18Vdc D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range Absolute Maximum Ratings: (Voltages referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55° to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Note 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc 5.0 −1.2 − −1.0 −1.7 − −0.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.25 − −0.2 −0.36 − −0.14 − mAdc (VOH = 9.5Vdc) 10 −0.62 − −0.5 −0.9 − −0.35 − mAdc (VOH = 13.5Vdc) 15 −1.8 − −1.5 −3.5 − −1.1 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage (Note 4) “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 5.0 − 0.005 5.0 − 150 μAdc 10 − 10 − 0.010 10 − 300 μAdc 15 − 20 − 0.015 20 − 600 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on all outputs, all buffers switching, Note 3, Note 5) IT Three State Leakage Current ITL 5.0 IT = (0.8μA/kHz) f + IDD μAdc 10 IT = (1.6μA/kHz) f + IDD μAdc 15 IT = (2.4μA/kHz) f + IDD μAdc 15 − ±0.1 − ±0.00001 ±0.1 − ±3.0 μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. Noise immunity specified for worst−case input combination. Noise margin for both “1” and “0” = 1.0Vdc min @ VDD = 5Vdc 2.0Vdc min @ VDD = 10Vdc 2.5Vdc min @ VDD = 15Vdc Note 5. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 1 x 10−3 (CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in Vdc, f in kHz is input frequency. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) VDD Vdc Min Typ Max Unit 5.0 − 225 360 ns tTLH = (1.5ns/pF) CL + 12ns 10 − 110 180 ns tTLH = (1.1ns/pF) CL + 8ns 15 − 80 130 ns 5.0 − 130 200 ns tTHL = (0.75ns/pF) CL + 24ns 10 − 65 100 ns tTHL = (0.55ns/pF) CL + 17ns 15 − 50 80 ns 5.0 − 330 650 ns tPLH = (0.3ns/pF) CL + 70ns 10 − 125 250 ns tPLH = (0.23ns/pF) CL + 54ns 15 − 85 170 ns 5.0 − 330 650 ns tPHL = (0.9ns/pF) CL + 61ns 10 − 125 250 ns tPHL = (0.68ns/pF) CL + 47ns 15 − 85 170 ns 5.0 − 60 150 ns 10 − 35 100 ns 15 − 30 75 ns Parameter Symbol Output Rise Time tTLH = (3.0ns/pF) CL + 25ns tTLH Output Fall Time tTHL = (1.5ns/pF) CL + 47ns tTHL Turn−Off Delay Time tPLH = (0.9ns/pF) CL + 211ns tPLH Turn−On Delay Time tPHL = (2.7ns/pF) CL + 184ns tPHL 3−State Output Delay Time “1” or “0” to High Impedance, and High Impedance to “1” or “0” tPHZ, tPLZ, tPZH, tPZL Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Truth Table C 0 0 0 0 1 1 1 1 DC DC B 0 0 1 1 0 0 1 1 DC DC DC = Don’t Care A 0 1 0 1 0 1 0 1 DC DC Inhibit 0 0 0 0 0 0 0 0 1 DC Disable 0 0 0 0 0 0 0 0 0 1 Z X0 X1 X2 X3 X4 X5 X6 X7 0 High Impedance Pin Connection Diagram D0 1 16 VDD D1 2 D2 3 15 3−State Disable 14 Selector Output D3 4 13 C D4 5 12 B D5 6 11 A D6 7 10 Inhibit VSS 8 9 D7 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min