NTE4514B

NTE4514B & NTE4515B Integrated Circuit CMOS, 4−Bit Latch/4−to−16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4−to−16 line decoder with latched inputs. The NTE4514B presents a logical “1” at the selected output, whereas the NTE4515B presents a logical “0” at the selected output. The latches are R−S type flip−flops which hold the last input data presented prior to the strobe transition from “1” to “0”. These high and low options of a 4−bit latch/4−to−16 line decoder are constructed with N−channel and P−channel enhancement mode devices in a single monolithic structure. The latches are R−S type flip−flops and data admitted upon a signal incident at the strobe input, decoded, and presented at the output. These complementary circuits find primary use in decoding applications where low power dissipation and/or high immunity is desired. Features: D Quiescent Current = 5nA/Package (Typ) at 5Vdc D Noise Immunity = 45% of VDD (Typ) D Supply Voltage Range: 3Vdc to 18Vdc D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range D Single Supply Operation − Positive or Negative D Input Impedance = 1012 Ohms (Typ) Absolute Maximum Ratings: (Voltages referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD to +0.5V DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55° to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Note 2. These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic level (e.g., either VSS or VDD). Electrical Characteristics: (Voltages referenced to VSS, Note 3) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc 5.0 −1.2 − −1.0 −1.7 − −0.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.25 − −0.2 −0.36 − −0.14 − mAdc (VOH = 9.5Vdc) 10 −0.62 − −0.5 −0.9 − −0.35 − mAdc (VOH = 13.5Vdc) 15 −1.8 − −1.5 −3.5 − −1.1 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage (Note 5) “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 5.0 − 0.005 5.0 − 150 μAdc 10 − 10 − 0.010 10 − 300 μAdc 15 − 20 − 0.015 20 − 600 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on all outputs, all buffers switching, Note 4, Note 6) IT 5.0 IT = (1.35μA/kHz) f + IDD μAdc 10 IT = (2.70μA/kHz) f + IDD μAdc 15 IT = (4.05μA/kHz) f + IDD μAdc Note 3. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 4. The formulas given are for the typical characteristics only at +25°C. Note 5. Noise immunity specified for worst−case input combination. Noise margin for both “1” and “0” = 1.0Vdc min @ VDD = 5Vdc 2.0Vdc min @ VDD = 10Vdc 2.5Vdc min @ VDD = 15Vdc Note 6. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 2 x 10−3 (CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in Vdc, f in kHz is input frequency. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 3) VDD Vdc Min Typ Max Unit 5.0 − 180 360 ns tTLH = (1.5ns/pf) CL + 15ns 10 − 90 180 ns tTLH = (1.1ns/pf) CL + 10ns 15 − 65 130 ns 5.0 − 100 200 ns tTHL = (0.75ns/pf) CL + 12.5ns 10 − 50 100 ns tTHL = (0.55ns/pf) CL + 9.5ns 15 − 40 80 ns 5.0 − 550 1100 ns tPLH, tPHL = (0.66ns/pf) CL + 192ns 10 − 225 450 ns tPLH, tPHL = (0.5ns/pf) CL + 125ns 15 − 150 300 ns 5.0 − 400 800 ns tPLH, tPHL = (0.66ns/pf) CL + 117ns 10 − 150 300 ns tPLH, tPHL = (0.5ns/pf) CL + 75ns 15 − 100 200 ns 5.0 250 125 − ns 10 100 50 − ns 15 75 38 − ns 5.0 350 175 − ns 10 100 50 − ns 15 75 38 − ns Parameter Output Rise Time tTLH = (3.0ns/pf) CL + 30ns Output Fall Time tTHL = (1.5ns/pf) CL + 25ns Propagation Delay Time tPLH, tPHL = (1.7ns/pf) CL + 465ns Inhibit Propagation Delay Times tPLH, tPHL = (1.7ns/pf) CL + 315ns Setup Time Strobe Pulse Width Symbol tTLH tTHL tPLH, tPHL tPLH, tPHL tsu tWH Note 3. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 4. The formulas given are for the typical characteristics only at +25°C. Truth Table Selected Output NTE4514B = Logic “1” NTE4515B = Logic “0” S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 All Outputs = 0, NTE4514B All Output = 1, NTE4515B Data Inputs Inhibit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X = Don’t Care Pin Connection Diagram Strobe 1 Data 1 2 Data 2 3 S7 4 S6 5 S5 6 S4 7 S3 8 S1 9 S2 10 S0 11 VSS 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD Inhibit Data 4 Data 3 S10 S11 S8 S9 S14 S15 S12 S13 24 13 1 12 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24)