NTE74HC109

NTE74HC109 Integrated Circuit TTL − High Speed CMOS, Dual J−K Positive Edge Triggered Flip−Flop w/Set & Reset Description: The NTE74HC109 is a dual J−K flip−flip with set and reset in a 16−Lead plastic DIP type package. The flip−flop changes state with the positive transition of Clock (1CP and 2CP). The flip−flip is set and reset by active−low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. Features: D Asynchronous Set and Reset D Schmitt Trigger Clock Inputs D Typical Propagation Delay: 18ns (typ) D Fanout (Over Temperature Range): Standard Outputs . . . . . . . . . 10 LS−TTL Loads Bus Driver Outputs . . . . . . . . 15 LS−TTL Loads D Balanced Propagation Delay and Transition Times D Significant Power Reduction Compared to LS−TTL Logic ICs Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V Clamp Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA DC Output Current (Per Pin), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Typical Thermal Resistance, Junction−to−Ambient (Note 3), RthJA . . . . . . . . . . . . . . . . . . . . 90°C/W Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Note 1. Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the Recommended Operating Conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the Recommended Operating Conditions may effect device reliability. The Absolute Maximum Ratings are stress ratings only. Note 2. Unless otherwise specified, all voltages are referenced to GND. Note 3. RthJA is measured with the component mounted on an evaluation PC board in free air. Recommended Operating Conditions: Parameter Symbol Min Typ Max Unit VCC 2.0 − 6.0 V VIN, VOUT 0 − VCC V Operating Temperature Range TA −55 − +125 °C CP Input Rise or Fall Times VCC = 2.0V tr, tf − − 1.0 ms VCC = 4.5V − − 1.0 ms VCC = 6.0V − − 1.0 ms − − 1000 ns VCC = 4.5V − − 500 ns VCC = 6.0V − − 400 ns Supply Voltage DC Input or Output Voltage Input Rise or Fall Times (All Inputs Except CP) VCC = 2.0V tr, tf DC Electrical Characteristics: Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads Symbol -555 to +1255C Max Min Max Min Max Unit − − 1.5 − 1.5 − V 3.15 − − 3.15 − 3.15 − V 6.0 4.2 − − 4.2 − 4.2 − V 2.0 − − 0.5 − 0.5 − 0.5 V 4.5 − − 1.35 − 1.35 − 1.35 V 6.0 − − 1.8 − 1.8 − 1.8 V 2.0 1.9 − − 1.9 − 1.9 − V 4.5 4.4 − − 4.4 − 4.4 − V 6.0 5.9 − − 5.9 − 5.9 − V IO = −4mA 4.5 3.98 − − 3.84 − 3.7 − V IO = −5.2mA 6.0 5.48 − − 5.34 − 5.2 − V 2.0 − − 0.1 − 0.1 − 0.1 V 4.5 − − 0.1 − 0.1 − 0.1 V 6.0 − − 0.1 − 0.1 − 0.1 V IO = 4mA 4.5 − − 0.26 − 0.33 − 0.4 V IO = −5.2mA 6.0 − − 0.26 − 0.33 − 0.4 V Test Conditions VIH TTL Loads Low Level Output Voltage CMOS Loads -405 to +855C VIH VOH VIN = VIH or VIL, IO = −0.02mA VI = VIH or VIL VOL TTL Loads VIN = VIH or VIL, IO = 0.02mA VIN = VIH or VIL +255C VCC (V) Min Typ 2.0 1.5 4.5 Input Leakage Current IIN VIN = VCC or GND 6.0 − − ±0.1 − ±1.0 − ±1.0 μA Quiescent Supply Current ICC VIN = VCC or GND, IO = 0mA 6.0 − − 4.0 − 40 − 80 μA Prerequisite for Switching Characteristics: Parameter Setup Time J, K, to CP Symbol tSU Test Conditions +255C -405 to +855C -555 to +1255C Max Min Max Min Max Unit − − 100 − 120 − ns 16 − − 20 − 24 − ns 14 − − 17 − 20 − ns VCC (V) Min Typ 2.0 80 4.5 6.0 Prerequisite for Switching Characteristics (Cont’d): Parameter Hold Time J, K, to CP Removal Time R, S, to CP Pulse Width CP, R, S CP Frequency Symbol Test Conditions tH tREM tW fMAX +255C -405 to +855C -555 to +1255C Max Min Max Min Max Unit − − 5 − 5 − ns 5 − − 5 − 5 − ns 6.0 5 − − 5 − 5 − ns 2.0 80 − − 100 − 120 − ns 4.5 16 − − 20 − 24 − ns 6.0 14 − − 17 − 20 − ns 2.0 80 − − 100 − 120 − ns 4.5 16 − − 20 − 24 − ns 6.0 14 − − 17 − 20 − ns 2.0 6 − − 5 − 4 − MHz 4.5 30 − − 25 − 20 − MHz 6.0 35 − − 29 − 23 − MHz VCC (V) Min Typ 2.0 5 4.5 Switching Characteristics: (tr = tf = 6ns) Parameter Propagation Delay, CP to Q, Q Propagation Delay, S to Q Propagation Delay, S to Q Propagation Delay, R to Q Propagation Delay, R to Q Transition Times +255C -405 to +855C -555 to +1255C Max Min Max Min Max Unit − 175 − 220 − 265 ns − − 35 − 44 − 53 ns 5.0 − 14 − − − − − ns CL = 50pF 6.0 − − 30 − 37 − 45 ns tPLH, tPHL CL = 50pF 2.0 − − 120 − 150 − 180 ns CL = 50pF 4.5 − − 24 − 30 − 36 ns CL = 15pF 5.0 − 9 − − − − − ns CL = 50pF 6.0 − − 20 − 26 − 31 ns tPLH, tPHL CL = 50pF 2.0 − − 155 − 195 − 235 ns CL = 50pF 4.5 − − 31 − 39 − 47 ns CL = 15pF 5.0 − 13 − − − − − ns CL = 50pF 6.0 − − 26 − 33 − 40 ns tPLH, tPHL CL = 50pF 2.0 − − 185 − 230 − 280 ns CL = 50pF 4.5 − − 37 − 46 − 56 ns CL = 15pF 5.0 − 15 − − − − − ns CL = 50pF 6.0 − − 31 − 39 − 48 ns tPLH, tPHL CL = 50pF 2.0 − − 170 − 215 − 255 ns CL = 50pF 4.5 − − 34 − 43 − 51 ns CL = 15pF 5.0 − 14 − − − − − ns CL = 50pF 6.0 − − 29 − 37 − 43 ns tTLH, tTHL CL = 50pF 2.0 − − 75 − 95 − 110 ns 4.5 − − 15 − 19 − 22 ns 6.0 − − 13 − 16 − 19 ns VCC (V) Min Typ tPLH, tPHL CL = 50pF 2.0 − CL = 50pF 4.5 CL = 15pF Symbol Test Conditions Switching Characteristics (Cont’d): (tr = tf = 6ns) Parameter Symbol Test Conditions +255C -405 to +855C -555 to +1255C Max Min Max Min Max Unit − 10 − 10 − 10 pF VCC (V) Min Typ − − Input Capacitance CIN CP Frequency fMAX CL = 15pF 5.0 − 60 − − − − − MHz Power Dissipation Capacitance CPD Note 4 5.0 − 30 − − − − − pF Note 4. CPD is used to determine the dynamic power consumption, per flip−flop. PD = VCC2 fI + Σ + CL fO where fI = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage. Truth Table: S L H L H H H H H R H L L H H H H H Inputs CP X X X ↑ ↑ ↑ ↑ L Output J X X X L H L H X K X X X L L H H X Q H L Q L H H (NOTE) H (NOTE) L H Toggle No Change H L No Change H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care ↑ = Low−to−High Transition NOTE: Unpredictable and unstable condition if both S and R go high simultaneously. Pin Connection Diagram 1R 1 16 VCC 1J 2 1K 3 15 2 R 14 2 J 1 CP 4 13 2 K 1S 5 12 2 CP 1Q 6 11 2 S 10 2 Q 1Q 7 GND 8 9 2Q 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min