NTE74HC374

NTE74HC374 Integrated Circuit TTL − High Speed CMOS, Octal D−Type Flip−Flop with 3−State Outputs Common Output Control and Common Clock Description: The NTE74HC374 is a high speed octal D−type flip−flop with 3−state outputs in a 20−Lead DIP type package with the capability to drive 15 LS−TTL loads. The eight edge−triggered flip−flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable (OE) controls the 3−state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high−impedance state. Features: D Wide Power Supply Range: 2V to 6V D High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V D Buffered Inputs D Common Three−State Output Enable Control D Three−State Outputs D Bus Line Driving Capability D Typical Propagation Delay (Clock to Q): 15ns at VCC = 5V, CL = 15pF, TA = +25C D Fanout (Over Temperature Range): Standard Outputs . . . 10 LS−TTL Loads Bus Driver Outputs . . 15 LS−TTL Loads Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V Clamp Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA DC Drain Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35mA DC Output Source or Sink Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Maximum Junction, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Typical Thermal Resistance, Junction−to−Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2. Unless otherwise specified, all voltages are referenced to GND. Recommended Operating Conditions: Parameter Symbol Min Typ Max Unit VCC 2.0 − 6.0 V VIN, VOUT 0 − VCC V Operating Temperature Range TA −40 − +85 C Input Rise or Fall Times VCC = 2.0V tr, tf − − 1000 ns VCC = 4.5V − − 500 ns VCC = 6.0V − − 400 ns Supply Voltage DC Input or Output Voltage DC Electrical Characteristics: TA = +25C Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage Minimum LOW Level Output Voltage Symbol VIH Test Conditions VIL VOH VOL VIN = VIH or VIL VIN = VIH or VIL TA = −40 to +85C VCC Typ Guaranteed Limits 2.0 − 1.5 1.5 Unit V 4.5 − 3.15 3.15 V 6.0 − 4.2 4.2 V 2.0 − 0.5 0.5 V 4.5 − 1.35 1.35 V 6.0 − 1.8 1.8 V VCC VCC −0.1 VCC −0.1 IOUT = −20A − IOUT = −6mA 4.5 − 3.98 3.84 V V IOUT = −7.8mA 6.0 − 5.48 5.34 V IOUT = 20A − − 0.1 0.1 V IOUT = 6mA 4.5 0.2 0.26 0.33 V IOUT = 7.8mA 6.0 0.2 0.26 0.33 V Maximum Input Leakage Current IIN VIN = VCC or GND 6.0 − 0.1 1.0 A Maximum Quiescent Supply Current ICC VIN = VCC or GND, IOUT = 0A 6.0 − 8.0 80 A Three−State Leakage Current IOZ VIN = VIH or VIL 6.0 − 0.5 5.0 A Prerequisite for Switching Specifications: TA = +25C Parameter Maximum Clock Frequency Clock Pulse Width Setup Time (Date to Clock) Hold Time (Date to Clock) Symbol fMAX tW tSU tH Test Conditions TA = −40 to +85C VCC Typ 2.0 − 6 Guaranteed Limits 5 Unit MHz 4.5 − 30 25 MHz 6.0 − 35 29 MHz 2.0 − 80 100 ns 4.5 − 16 20 ns 6.0 − 14 17 ns 2.0 − 60 75 ns 4.5 − 12 15 ns 6.0 − 10 13 ns 2.0 − 5 5 ns 4.5 − 5 5 ns 6.0 − 5 5 ns Switching Specifications: (tr = tf = 6ns unless otherwise specified) TA = +25C Parameter Propagation Delay Time (Clock to Output) Propagation Delay Time (Disable to Q) Propagation Delay Time (Output Enable to Q) Maximum Clock Frequency VCC Typ 2.0 − 165 205 Unit ns 4.5 − 33 41 ns CL = 15pF 5.0 15 − − ns CL = 50pF 6.0 − 28 35 ns tPLZ, tPHZ CL = 50pF 2.0 − 135 170 ns 4.5 − 27 34 ns CL = 15pF 5.0 11 − − ns CL = 50pF 6.0 − 23 29 ns tPZL, tPZH CL = 50pF 2.0 − 150 190 ns Symbol Test Conditions tPLH, tPHL CL = 50pF Guaranteed Limits 4.5 − 30 38 ns CL = 15pF 5.0 12 − − ns CL = 50pF 6.0 − 26 33 ns CL = 15pF 5.0 60 − − MHz tTLH, tTHL CL = 50pF 2.0 − 60 75 ns 4.5 − 12 15 ns fMAX Output Transition Time TA = −40 to +85C 6.0 − 10 13 ns Maximum Input Capacitance CIN − − 10 10 pF Minimum Three−State Output Capacitance CO − − 20 20 pF Power Dissipation Capacitance CPD 5.0 39 − − pF CL = 15pF, Note 3 Note 3. CPD is used to determine the dynamic power consumption, per channel. PD = CPD VCC2 fi +  VCC2 fO CL where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Truth Table: Inputs Output OE CP Data Dn Qn L  H H L  L L L L X Q0 H X X Z H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care  = Transition from LOW to HIGH Level Q0 = The level of Q before the indicated steady state input conditions were established. Z = High Impedance State Pin Connection Diagram OE 1 20 VCC Q0 2 D0 3 19 Q7 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 20 11 1 10 .300 (7.62) .260 (6.6) Max 1.200 (30.5) Max .200 (5.08) Max .012 (0.30) .100 (2.54) Typ .100 (2.54) Min .350 (8.89)