NTE74HCT174

NTE74HCT174 Integrated Circuit TTL − High Speed CMOS, Hex D−Type Flip−Flop with Clear Description: The NTE74HCT174 is a positive edge−triggered flip−flop in a 16−Lead DIP type package that has a common clock and clear and independent Q outputs. Data on a D input, having the specified set−up and hold time, is transferred to the corresponding Q output on the positive−going transition of the clock pulse. The asynchronous clear forces all outputs low when it is low. All inputs to this device are protected from damage due to electrostatic discharge by diodes to VCC and GND. Features: D Typical Propagation Delay: 20ns D Low Quiescent Current: 80μA (max) D Fanout of 10 LS−TTL Loads Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.5 to VCC +1.5V DC Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VCC + 0.5V Clamp Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA DC Output Current (Per Pin), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA Power Dissipation (Note 3), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2. Unless otherwise specified, all voltages are referenced to GND. Note 3. Power Dissipation temperature derating: 12mW/°C from +65°C to +85°C. Recommended Operating Conditions: Parameter Symbol Min Typ Max Unit VCC 4.5 − 5.5 V VIN, VOUT 0 − VCC V Operating Temperature Range TA −40 − +85 °C Input Rise or Fall Times tr, tf − − 500 ns Supply Voltage DC Input or Output Voltage DC Electrical Characteristics: (VCC = 5V ±10% unless otherwise specified) TA = +25°C Typ Guaranteed Limits Parameter Symbol Minimum High Level Input Voltage VIH − 2.0 2.0 V Maximum Low Level Input Voltage VIL − 0.8 0.8 V Minimum High Level Output Voltage Maximum Low Level Output Voltage VOH VOL Test Conditions TA = −40° to +85°C VIN = VIH or VIL VIN = VIH −0.1 |IOUT| = 20μA VCC VCC |IOUT| = 4.0mA, VCC = 4.5V 4.2 3.98 3.84 V |IOUT| = 4.8mA, VCC = 5.5V 5.7 4.98 4.84 V 0 0.1 0.1 V |IOUT| = 4.0mA, VCC = 4.5V 0.2 0.26 0.33 V |IOUT| = 4.8mA, VCC = 5.5V 0.2 0.26 0.33 V |IOUT| = 20μA VCC −0.1 Unit V Maximum Input Current IIN VIN = VCC or GND, VIH or VIL − ±0.1 ±1.0 μA Maximum Quiescent Supply Current ICC VIN = VCC or GND, IOUT = 0μA − 8 80 μA VIN = 2.4V or 0.5V, Note 4 − − − μA Note 4. This is measured per input with all other inputs held at VCC or GND. AC Electrical Characteristics: (VCC = 5V, tr = tf = 6ns, CL = 15pF, TA = +25°C unless otherwise specified) Parameter Symbol Typ Guaranteed Limits Unit fMAX 50 30 MHz Maximum Propagation Delay (Clock to Q) tPHL, tPLH 18 30 ns Maximum Propagation Delay (Clear to Q) tPHL, tPLH 18 30 ns Maximum Removal Time (Clear to Clock) tREM − 20 ns Minimum Set Up Time (D to Clock) tS 10 30 ns Minimum Hold Time (Clock to Q) tH −3 0 ns Minimum Pulse Width (Clock or Clear) tW 8 16 ns Maximum Operating Frequency Test Conditions AC Electrical Characteristics: (VCC = 5V ±10%, tr = tf = 6ns, CL = 50pF unless otherwise specified) TA = +25°C Parameter Maximum Operating Frequency Symbol Test Conditions Typ TA = −40° to +85°C Guaranteed Limits Unit fMAX 40 22 18 MHz Maximum Propagation Delay (Clock to Q) tPHL, tPLH 22 35 44 ns Maximum Propagation Delay (Clear to Q) tPHL, tPLH 22 35 44 ns Minimum Removal Time (Clear to Clock) tREM − 20 25 ns Minimum Setup Time (D to Clock) tS 10 20 25 ns Minimum Hold Time (D to Clock) tH −3 0 0 ns Minimum Pulse Width (Clock or Clear) tW − 16 20 ns Maximum Input Rise and Fall Time tr, tf − 500 500 ns tTHL, tTLH − 15 19 ns − − − pF 5 10 10 pF Maximum Output Rise and Fall Time Power Dissipation Capacitance CPD Maximum Input Capacitance CIN Per Flip−Flop, Note 5 Note 5. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Pin Connection Diagram Clear 1 16 VCC 1Q 2 1D 3 15 6Q 14 6D 2D 4 13 5D 2Q 5 12 5Q 3D 6 11 4D 3Q 7 10 4Q GND 8 9 Clock 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min