M25P05-AVMN6P

M25P05-A 512-Kbit, serial flash memory, 50 MHz SPI bus interface Features ■ ■ 512 Kbits of flash memory Page program (up to 256 bytes) in 1.4 ms (typical) Sector erase (256 Kbits) in 0.65 s (typical) Bulk erase (512 Kbits) in 0.85 s (typical) 2.3 to 3.6 V single supply voltage SPI bus compatible serial interface 50 MHz clock rate (maximum) Deep power-down mode 1 µA (typical) Electronic signatures – JEDEC standard two-byte signature (2010h) – RES instruction, one-byte, signature (05h), for backward compatibility More than 100,000 erase/program cycles per sector More than 20 years data retention ECOPACK® packages available TSSOP8 (DW) SO8 (MN) 150 mil width ■ ■ ■ ■ ■ ■ ■ VFQFPN8 (MP) (MLP8) ■ ■ ■ UFDFPN8 (MB) 2 x 3 mm April 2008 Rev 11 1/52 www.numonyx.com 1 Contents M25P05-A Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 4.2 4.3 4.4 4.5 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12 Active power, standby power and deep power-down modes . . . . . . . . . . 12 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5.1 4.5.2 4.5.3 4.5.4 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 6.2 6.3 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/52 M25P05-A Contents 6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 6.4.2 6.4.3 6.4.4 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 27 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Release from deep power-down and read electronic signature (RES) . . 33 7 8 9 10 11 12 13 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3/52 List of tables M25P05-A List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Instruction times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC characteristics (40 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 45 VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 47 UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/52 M25P05-A List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO, VFQFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21 Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 23 Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Release from deep power-down and read electronic signature (RES) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Release from deep power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write protect setup and hold timing during WRSR when SRWD =1. . . . . . . . . . . . . . . . . . 43 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 45 VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 47 UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5/52 Description M25P05-A 1 Description The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the page program instruction. The memory is organized as 2 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes. The whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. Figure 1. Logic diagram VCC D C S W HOLD M25P05-A Q VSS AI05757 Table 1. Signal names Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Supply Supply Direction Signal name C D Q S W HOLD VCC VSS 6/52 M25P05-A Figure 2. SO, VFQFPN and TSSOP connections M25P05-A S Q W VSS 1 2 3 4 8 7 6 5 AI05758B Description VCC HOLD C D 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. 7/52 Signal descriptions M25P05-A 2 2.1 Signal descriptions Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal program, erase or write status register cycle is in progress, the device will be in the standby mode (this is not the deep power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are don’t care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the status register). 8/52 M25P05-A Signal descriptions 2.7 VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 9/52 SPI modes M25P05-A 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● ● CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in standby mode and not transferring data: ● ● C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus master and memory devices on the SPI bus VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI bus master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI memory device VCC VSS R SPI memory device CQD VCC VSS R SPI memory device CQD VCC VSS Figure 3. AI12836b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the M25P05-A is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the SPI bus in high impedance. 10/52 M25P05-A SPI modes Example: Cp = 50 pF, that is R*Cp = 5 µs the application must ensure that the bus master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. CPOL CPHA C SPI modes supported 0 0 1 1 C D MSB Q MSB AI01438B 11/52 Operating features M25P05-A 4 4.1 Operating features Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data. This is followed by the internal program cycle (of duration tPP). To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Section 6.8: Page program (PP) and Table 14: Instruction times). 4.2 Sector erase and bulk erase The page program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the sector erase (SE) instruction, or throughout the entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of duration tSE or tBE). The erase instruction must be preceded by a write enable (WREN) instruction. 4.3 Polling during a write, program or erase cycle A further improvement in the time to write status register (WRSR), program (PP) or erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The write in progress (WIP) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. 4.4 Active power, standby power and deep power-down modes When Chip Select (S) is Low, the device is selected, and in the active power mode. When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The device consumption drops to ICC1. The deep power-down mode is entered when the specific instruction (the deep power-down (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the release from deep power-down and read electronic signature (RES) instruction) is executed. While in the deep power-down mode, the device ignores all write, program and erase instructions (see Section 6.11: Deep power-down (DP)). This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. 12/52 M25P05-A Operating features 4.5 Status register The status register contains a number of status and control bits, as shown in Table 6, that can be read or set (as appropriate) by specific instructions. 4.5.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program or erase cycle. 4.5.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. 4.5.3 BP1, BP0 bits The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against program and erase instructions. 4.5.4 SRWD bit The status register write disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the hardware protected mode. In this mode, the non-volatile bits of the status register (SRWD, BP1, BP0) become read-only bits. 13/52 Operating features M25P05-A 4.6 Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P05-A features the following data protection mechanisms: ● ● Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification Program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following events: – – – – – – Power-up Write disable (WRDI) instruction completion Write status register (WRSR) instruction completion Page program (PP) instruction completion Sector erase (SE) instruction completion Bulk erase (BE) instruction completion ● ● ● The block protect (BP1, BP0) bits allow part of the memory to be configured as readonly. This is the software protected mode (SPM) The Write Protect (W) signal, in co-operation with the status register write disable (SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable (SRWD) bit to be write-protected. This is the hardware protected mode (HPM) In addition to the low power consumption feature, the deep power-down mode offers extra software protection, as all write, program and erase instructions are ignored. Protected area sizes Memory content Protected area none Unprotected area All sectors (sectors 0 and 1) ● Table 2. Status Register content BP1 bit 0 0 1 1 BP0 bit 0 1 0 1 No protection against page program (PP) and sector erase (SE) All sectors (sectors 0 and 1) protected against bulk erase (BE) All sectors (sectors 0 and 1) none 1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0. 14/52 M25P05-A Operating features 4.7 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress. To enter the hold condition, the device must be selected, with Chip Select (S) Low. The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 5). The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes Low (this is shown in Figure 5). During the hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are don’t care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. If Chip Select (S) goes High while the device is in the hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the hold condition. Figure 5. Hold condition activation C HOLD Hold condition (standard use) Hold condition (non-standard use) AI02029D 15/52 Memory organization M25P05-A 5 Memory organization The memory is organized as: ● ● ● 65,536 bytes (8 bits each) 2 sectors (256 Kbits, 32768 bytes each) 256 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. Table 3. Memory organization Sector 1 0 08000h 00000h Address range 0FFFFh 07FFFh 16/52 M25P05-A Figure 6. HOLD W S C D Q Control logic Memory organization Block diagram High voltage generator I/O shift register Address register and counter 256 byte data buffer Status register 0FFFFh Y decoder 08000h Size of the read-only memory area 00000h 256 bytes (page size) X decoder 000FFh AI05759 17/52 Instructions M25P05-A 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (S) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a read data bytes (READ), read data bytes at higher speed (Fast_Read), read identification (RDID), read status register (RDSR) or release from deep power-down, and read electronic signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a page program (PP), sector erase (SE), bulk erase (BE), write status register (WRSR), write enable (WREN), write disable (WRDI) or deep power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. 18/52 M25P05-A Table 4. Instruction WREN WRDI RDID (1) Instructions Instruction set Description Write enable Write disable Read identification Read status register Write status register Read data bytes Read data bytes at higher speed Page program Sector erase Bulk erase Deep power-down Release from deep powerdown, and read electronic signature Release from deep powerdown One-byte instruction Address Dummy code bytes bytes 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 06h 04h 9Fh 05h 01h 03h 0Bh 02h D8h C7h B9h 0 0 0 0 0 3 3 3 3 0 0 0 1010 1011 ABh 0 0 0 0 0 0 0 0 0 1 0 0 0 0 3 Data bytes 0 0 1 to 3 1 to ∞ 1 1 to ∞ 1 to ∞ 1 to 256 0 0 0 1 to ∞ RDSR WRSR READ FAST_READ PP SE BE DP RES 1. The read identification (RDID) instruction is available only in products with process technology code X and Y (see application note AN1995). 6.1 Write enable (WREN) The write enable (WREN) instruction (Figure 7) sets the write enable latch (WEL) bit. The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase (SE), bulk erase (BE) and write status register (WRSR) instruction. The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 7. Write enable (WREN) instruction sequence S 0 C Instruction D High Impedance Q AI02281E 1 2 3 4 5 6 7 19/52 Instructions M25P05-A 6.2 Write disable (WRDI) The write disable (WRDI) instruction (Figure 8) resets the write enable latch (WEL) bit. The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions: ● ● ● ● ● ● Power-up Write disable (WRDI) instruction completion Write status register (WRSR) instruction completion Page program (PP) instruction completion Sector erase (SE) instruction completion Bulk erase (BE) instruction completion. Write disable (WRDI) instruction sequence S 0 C Instruction D High Impedance Q AI03750D Figure 8. 1 2 3 4 5 6 7 20/52 M25P05-A Instructions 6.3 Read identification (RDID) The read identification (RDID) instruction is available in products with process technology code X and Y. The read identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (10h). Any read identification (RDID) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The read identification (RDID) instruction should not be issued while the device is in deep power-down mode. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The read identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the standby power mode. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read identification (RDID) data-out sequence Device identification Manufacturer identification Memory type 20h 20h Memory capacity 10h Figure 9. Read identification (RDID) instruction sequence and data-out sequence S 0 C Instruction D Manufacturer identification High Impedance Q MSB 15 14 13 MSB AI06809b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 Device identification 3 2 1 0 21/52 Instructions M25P05-A 6.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write status register cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the status register continuously, as shown in Figure 10. Table 6. b7 SRWD 0 0 0 BP1 BP0 WEL Status register format b0 WIP Status register write protect Block protect bits Write enable latch bit Write in progress bit The status and control bits of the status register are as follows: 6.4.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is in progress. 6.4.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is reset and no write status register, program or erase instruction is accepted. 6.4.3 BP1, BP0 bits The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against program and erase instructions. These bits are written with the write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes protected against page program (PP) and sector erase (SE) instructions. The block protect (BP1, BP0) bits can be written provided that the hardware protected mode has not been set. The bulk erase (BE) instruction is executed if, and only if, both block protect (BP1, BP0) bits are 0. 6.4.4 SRWD bit The status register write disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The status register write disable (SRWD) bit and write protect (W) signal allow the device to be put in the hardware protected mode (when the status register write disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the nonvolatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write status register (WRSR) instruction is no longer accepted for execution. 22/52 M25P05-A Instructions Figure 10. Read status register (RDSR) instruction sequence and data-out sequence S 0 C Instruction D Status register out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB AI02031E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Status register out 6 5 4 3 2 1 0 7 6.5 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). The write status register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (D). The instruction sequence is shown in Figure 11. The write status register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) is reset. The write status register (WRSR) instruction allows the user to change the values of the block protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The write status register (WRSR) instruction also allows the user to set or reset the status register write disable (SRWD) bit in accordance with the Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the hardware protected mode (HPM). The write status register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. The protection features of the device are summarized in Table 7. When the status register write disable (SRWD) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. 23/52 Instructions M25P05-A When the status register write disable (SRWD) bit of the status register is set to ‘1’, two cases need to be considered, depending on the state of Write Protect (W): ● If Write Protect (W) is driven High, it is possible to write to the status register provided that the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction If Write Protect (W) is driven Low, it is not possible to write to the status register even if the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction (attempts to write to the status register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the block protect (BP1, BP0) bits of the status register, are also hardware protected against data modification. ● Regardless of the order of the two events, the hardware protected mode (HPM) can be entered: ● ● by setting the status register write disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the status register write disable (SRWD) bit. The only way to exit the hardware protected mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can never be activated, and only the software protected mode (SPM), using the block protect (BP1, BP0) bits of the status register, can be used. Figure 11. Write status register (WRSR) instruction sequence S 0 C Instruction Status register in 7 High Impedance Q AI02282D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D 6 5 4 3 2 1 0 MSB 24/52 M25P05-A Table 7. Protection modes Instructions Memory content W SRWD signal bit 1 0 1 0 0 1 Mode Write protection of the status register Protected area(1) Protected against page program, sector erase and bulk erase Protected against page program, sector erase and bulk erase Unprotected area(1) Ready to accept page program and sector erase instructions Ready to accept page program and sector erase instructions Status register is writable (if the Software WREN instruction has set the WEL protected bit). (SPM) The values in the SRWD, BP1 and BP0 bits can be changed Status register is hardware write Hardware protected. protected The values in the SRWD BP1 and (HPM) BP0 bits cannot be changed 0 1 1. As defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Table 2. 25/52 Instructions M25P05-A 6.6 Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes (READ) instruction. There is no address roll-over; when the highest address (0FFFFh) is reached, the instruction should be terminated. The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read data bytes (READ) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read data bytes (READ) instruction sequence and data-out sequence S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 D High Impedance Q 23 22 21 MSB 3 2 1 0 Data out 1 7 6 5 4 3 2 1 0 Data out 2 7 MSB AI03748D 1. Address bits A23 to A16 must be set to 00h. 26/52 M25P05-A Instructions 6.7 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction. There is no address roll-over; when the highest address (0FFFFh) is reached, the instruction should be terminated. The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 D High Impedance Q 23 22 21 3 2 1 0 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte D 7 6 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI04006 Q 7 MSB 6 5 4 3 2 1. Address bits A23 to A16 must be set to 00h. 27/52 Instructions M25P05-A 6.8 Page program (PP) The page program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Table 14: Instruction times). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the page program cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A page program (PP) instruction applied to a page which is protected by the block protect (BP1, BP0) bits (see Table 3. and Table 2.) is not executed. 28/52 M25P05-A Figure 14. Page program (PP) instruction sequence S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10 Instructions 28 29 30 31 32 33 34 35 36 37 38 39 D 23 22 21 MSB 3 2 1 0 7 6 5 4 3 2 1 0 MSB S 2072 2073 2074 2075 2076 2077 2078 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte 256 D 7 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB AI04082B 1. Address bits A23 to A16 must be set to 00h. 2079 29/52 Instructions M25P05-A 6.9 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (D). Any address inside the sector (see Table 3) is a valid address for the sector erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is initiated. While the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A sector erase (SE) instruction applied to a page which is protected by the block protect (BP1, BP0) bits (see Table 3 and Table 2) is not executed. Figure 15. Sector erase (SE) instruction sequence S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 29 30 31 D 23 22 MSB 2 1 0 AI03751D 1. Address bits A23 to A16 must be set to 00h. 30/52 M25P05-A Instructions 6.10 Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed bulk erase cycle (whose duration is tBE) is initiated. While the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. The bulk erase (BE) instruction is executed only if both block protect (BP1, BP0) bits are 0. The bulk erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk erase (BE) instruction sequence S 0 C Instruction D 1 2 3 4 5 6 7 AI03752D 31/52 Instructions M25P05-A 6.11 Deep power-down (DP) Executing the deep power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). It can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all write, program and erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in standby mode (if there is no internal cycle currently in progress). But this mode is not the deep power-down mode. The deep power-down mode can only be entered by executing the deep power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 13). To take the device out of deep power-down mode, the release from deep power-down and read electronic signature (RES) instruction must be issued. No other instruction must be issued while the device is in deep power-down mode. The release from deep power-down and read electronic signature (RES) instruction, and the read identification (RDID) instruction also allow the electronic signature of the device to be output on Serial Data output (Q). The deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the deep power-down mode is entered. Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep power-down (DP) instruction sequence S 0 C Instruction D 1 2 3 4 5 6 7 tDP Standby mode Deep power-down mode AI03753D 32/52 M25P05-A Instructions 6.12 Release from deep power-down and read electronic signature (RES) To take the device out of deep power-down mode, the release from deep power-down and read electronic signature (RES) instruction must be issued. No other instruction must be issued while the device is in deep power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic signature, whose value for the M25P05-A is 05h. Except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (RES) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the deep powerdown mode has not been entered. Any release from deep power-down and read electronic signature (RES) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge of Serial Clock (C). Then, the 8-bit electronic signature, stored in the memory, is shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 18. The release from deep power-down and read electronic signature (RES) instruction is terminated by driving Chip Select (S) High after the electronic signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the electronic signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the standby power mode. If the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. If the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by tRES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 15. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in Figure 19), still ensures that the device is put into standby power mode. If the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. If the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by tRES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 15. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 33/52 Instructions Figure 18. Release from deep power-down and read electronic signature (RES) instruction sequence and data-out sequence M25P05-A S 0 C Instruction 3 dummy bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 D High Impedance Q 23 22 21 MSB 3 2 1 0 Electronic signature Out 7 MSB Deep power-down mode Standby mode AI04047C 6 5 4 3 2 1 0 1. The value of the 8-bit electronic signature, for the M25P05-A, is 05h. Figure 19. Release from deep power-down (RES) instruction sequence S 0 C Instruction D 1 2 3 4 5 6 7 tRES1 High Impedance Q Deep power-down mode Standby mode AI04078B 34/52 M25P05-A Power-up and power-down 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: ● ● VCC(min) at power-up, and then for a further delay of tVSL VSS at power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the power on reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all write enable (WREN), page program (PP), sector erase (SE), bulk erase (BE) and write status register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No write status register, program or erase instructions should be sent until the later of: ● ● tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for read instructions even if the tPUW delay is not yet fully elapsed. At power-up, the device is in the following state: ● ● ● The device is in the standby mode (not the deep power-down mode) The write enable latch (WEL) bit is reset The write in progress (WIP) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the power on reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result). 35/52 Initial delivery state Figure 20. Power-up timing VCC VCC(max) Program, erase and write commands are rejected by the device Chip selection not allowed VCC(min) Reset state of the device VWI tPUW tVSL Read access allowed M25P05-A Device fully accessible time AI04009C Table 8. Symbol tVSL(1) tPUW(1) VWI(1) Power-up timing and VWI threshold Parameter VCC(min) to S low Time delay to Write instruction Write inhibit voltage Min 10 1 1 10 2 Max Unit µs ms V 1. These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). The status register contains 00h (all status register bits are 0). 36/52 M25P05-A Maximum ratings 9 Maximum ratings Stressing the device above the rating listed in Table 9: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 9. Symbol TSTG TLEAD VIO VCC VESD Absolute maximum ratings Parameter Storage temperature Lead temperature during soldering Input and output voltage (with respect to ground) Supply voltage Electrostatic discharge voltage (human body model)(2) –0.6 –0.6 –2000 Min –65 Max 150 see(1) VCC + 0.6 4.0 2000 Unit °C °C V V V 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). 37/52 DC and AC parameters M25P05-A 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10. Symbol VCC TA Supply voltage Ambient operating temperature Operating conditions Parameter Min 2.3 (1) Max 3.6 85 Unit V °C –40 1. Only in products with process technology code Y. In products with process technology code X, VCC(min) is 2.7 V. Table 11. Symbol CL AC measurement conditions(1) Parameter Load capacitance Input rise and fall times Input pulse voltages Input timing reference voltages Output timing reference voltages Min 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max Unit pF ns V V V 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 21. AC measurement I/O waveform Input levels 0.8VCC Input and output timing reference levels 0.7VCC 0.5VCC 0.3VCC AI07455 0.2VCC Table 12. Symbol COUT CIN Capacitance(1) Parameter Output capacitance (Q) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min Max 8 6 Unit pF pF 1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 25 MHz. 38/52 M25P05-A Table 13. Symbol ILI ILO ICC1 ICC2 DC and AC parameters DC characteristics Parameter Input leakage current Output leakage current Standby current Deep power-down current S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 50 MHz, Q = open ICC3 Operating current (READ) C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open Operating current (PP) Operating current (WRSR) Operating current (SE) Operating current (BE) Input low voltage Input high voltage Output low voltage Output high voltage IOL = 1.6 mA IOH = –100 µA VCC–0.2 S = VCC S = VCC S = VCC S = VCC – 0.5 0.7VCC 4 15 15 15 15 0.3VCC VCC+0.4 0.4 mA mA mA mA mA V V V V Test condition (in addition to those in Table 10.) Min Max ±2 ±2 50 5 8 Unit µA µA µA µA mA ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH Table 14. Instruction times Test conditions specified in Table 10 and Table 11. Symbol tW tPP(1) tSE tBE Alt. Parameter Write status register cycle time Page program cycle time (256 bytes) Page program cycle time (n bytes) Sector erase cycle time Bulk erase cycle time Min Typ 5 1.4 0.4+n*1/256(2) 0.65 0.85 Max 15 5 3 6 Unit ms ms s s 1. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 2. tPP=2µs+8µs*[int(n-1)/2+1]+4µs*[int(n-1)/2]+2µs, only in products with process technology code X and Y. 39/52 DC and AC parameters Table 15. AC characteristics (25 MHz operation) Test conditions specified in Table 10 and Table 11. Symbol fC fR tCH(1) tCL(1) tCLCH(2) tCHCL (2) M25P05-A Alt. fC Parameter Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock frequency for read instructions Min D.C. D.C. 18 18 0.1 0.1 10 10 5 5 10 10 100 Typ Max 25 20 Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns tCLH Clock high time tCLL Clock low time Clock rise time(3) (peak to peak) Clock fall time(3) (peak to peak) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL tSHWL (4) (4) tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU Data in setup time tDH Data in hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH S deselect time tDIS tV tHO Output disable time Clock Low to Output Valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C) tLZ tHZ HOLD to Output Low-Z HOLD to Output High-Z Write protect setup time Write protect hold time S High to deep power-down mode S High to standby mode without electronic signature read S High to standby mode with electronic signature read 15 15 0 10 10 10 10 15 20 20 100 3 3 1.8 ns ns ns ns ns ns ns ns ns ns ns µs µs µs tDP (2) tRES1(2) tRES2(2) 1. tCH + tCL must be greater than or equal to 1/ fC. 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 40/52 M25P05-A Table 16. AC characteristics (40 MHz operation) DC and AC parameters 40 MHz available for products marked since week 20 of 2004, only(1) Test conditions specified in Table 10. and Table 11. Symbol fC fR tCH(2) tCL(2) tCLCH (3) Alt. fC Parameter Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock frequency for read instructions Min D.C. D.C. 11 11 Typ Max 40 20 Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns tCLH Clock high time tCLL Clock low time Clock rise time(4) (peak to peak) 0.1 0.1 5 5 2 5 5 5 100 9 9 0 5 5 5 5 9 9 20 100 3 3 1.8 tCHCL(3) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(3) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(3) tHLQZ(3) tWHSL tSHWL (5) (1) Clock fall time(4) (peak to peak) tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU Data in setup time tDH Data in hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH S deselect time tDIS tV tHO Output disable time Clock Low to Output Valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C) tLZ tHZ HOLD to Output Low-Z HOLD to Output High-Z Write protect setup time Write protect hold time S High to deep power-down mode S High to standby mode without electronic signature read S High to standby mode with electronic signature read ns ns ns ns ns ns ns ns ns ns ns µs µs µs tDP(3) tRES1(3) tRES2(3) 1. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 2. tCH + tCL must be greater than or equal to 1/ fC. 3. Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. 5. Details of how to find the date of marking are given in application note, AN1995. 41/52 DC and AC parameters Table 17. AC characteristics (50 MHz operation) 50 MHz available only in products with process technology code Y(1)(2) Test conditions specified in Table 10 and Table 11. Symbol fC fR tCH(3) tCL(3) tCLCH(4) tCHCL (4) M25P05-A Alt. fC Parameter Clock frequency(1) for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR Clock frequency for read instructions Min D.C. D.C. 9 9 0.1 0.1 5 5 2 5 5 5 100 Typ Max 50 25 Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns tCLH tCLL Clock high time Clock low time Clock rise time(5) (peak to peak) Clock fall time(5) (peak to peak) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(4) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(4) tHLQZ(4) tWHSL tSHWL (6) (6) tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU tDH Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH tDIS tV tHO S deselect time Output disable time Clock Low to Output Valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C) 8 8 0 5 5 5 5 8 8 20 100 3 30 30 ns ns ns ns ns ns ns ns ns ns ns µs µs µs tLZ tHZ HOLD to Output Low-Z HOLD to Output High-Z Write protect setup time Write protect hold time S High to deep power-down mode S High to standby mode without electronic signature read S High to standby mode with electronic signature read tDP(4) tRES1 tRES2 (4) (4) 1. Details of how to find the process on the device marking are given in application note AN1995. 2. 50 MHz operation is also available in products with process technology code X, but with a reduced supply voltage range (2.7 to 3.6 V). 3. tCH + tCL must be greater than or equal to 1/ fC. 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 42/52 M25P05-A Figure 22. Serial input timing DC and AC parameters tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH Q High Impedance AI01447C Figure 23. Write protect setup and hold timing during WRSR when SRWD =1 W tWHSL tSHWL S C D High Impedance Q AI07439 43/52 DC and AC parameters Figure 24. Hold timing S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH M25P05-A D HOLD AI02032 Figure 25. Output timing S tCH C tCLQV tCLQX Q tQLQH tQHQL D ADDR .LSB IN tCLQV tCLQX tCL tSHQZ LSB OUT AI01449e 44/52 M25P05-A Package mechanical 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. SO8N – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 b e 0.25 mm GAUGE PLANE k 8 A ccc c D E1 1 E A1 L L1 SO-A 1. Drawing is not to scale. Table 18. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data millimeters inches Max 1.75 0.10 1.25 0.28 0.17 4.90 6.00 3.90 1.27 4.80 5.80 3.80 – 0.25 0° 0.40 1.04 0.48 0.23 0.10 5.00 6.20 4.00 – 0.50 8° 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 – 0.010 0° 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 – 0.020 8° 0.050 Typ Min Max 0.069 0.010 Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min 45/52 Package mechanical M25P05-A Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package outline A R1 D1 B MCAB bbb D aaa C A E E1 E2 e 2x 0.10 C B aaa C B b 0.10 C A θ A2 D2 L ddd A A1 A3 C 70-ME 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 19. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data millimeters inches Max 1.00 0.05 0.026 0.008 0.35 0.48 0.016 0.236 0.226 3.20 3.60 0.134 0.197 0.187 3.80 – 0.00 0.50 0.75 12° 0.15 0.10 0.05 4.30 – 0.157 0.050 0.004 0.024 0.150 – 0.000 0.020 0.029 12° 0.006 0.004 0.002 0.169 – 0.126 0.142 0.014 0.019 Typ 0.033 Min 0.031 0.000 Max 0.039 0.002 Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e R1 L Q aaa bbb ddd 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.10 0.60 0.85 Min 0.80 0.00 46/52 M25P05-A Package mechanical Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline D 8 5 c E1 E 1 4 α A1 A CP b e A2 L L1 TSSOP8AM 1. Drawing is not to scale. Table 20. Symbol TSSOP8 – 8 lead thin shrink small outline, package mechanical data millimeters Typ Min Max 1.20 0.05 1.00 0.80 0.19 0.09 0.15 1.05 0.30 0.20 0.10 3.00 0.65 6.40 4.40 0.60 1.00 0° 8 8° 2.90 – 6.20 4.30 0.45 3.10 – 6.60 4.50 0.75 0.118 0.026 0.252 0.173 0.024 0.039 0° 8 8° 0.114 – 0.244 0.169 0.018 0.039 0.002 0.031 0.007 0.003 Typ inches Min Max 0.047 0.006 0.041 0.012 0.008 0.004 0.122 – 0.260 0.177 0.029 A A1 A2 b c CP D e E E1 L L1 α N 47/52 Package mechanical M25P05-A Figure 29. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline D L3 e b L1 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package mechanical data millimeters inches Max 0.60 0.05 0.30 2.10 1.70 0.08 3.00 0.20 0.50 0.45 2.90 0.10 – 0.40 3.10 0.30 – 0.50 0.15 0.30 0.012 0.118 0.008 0.020 0.018 0.114 0.004 – 0.016 Typ 0.022 0.001 0.010 0.079 0.063 Min 0.018 0.000 0.008 0.075 0.059 Max 0.024 0.002 0.012 0.083 0.067 0.003 0.122 0.012 – 0.020 0.006 Symbol Typ A A1 b(1) D D2 ddd E E2 e L L1 L3 (2) Min 0.45 0.00 0.20 1.90 1.50 0.55 0.02 0.25 2.00 1.60 1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 48/52 M25P05-A Ordering information 12 Ordering information Table 22. Example: Ordering information scheme M25P05-A V MN 6 T P Device type M25P Device function 05-A = 512 Kbits (64 Kbit x8) Operating voltage V = VCC = 2.3 to 3.6 V Package MN = SO8 (150 mil width) MP = VFQFPN8 (MLP8) DW = TSSOP8(1) MB = UFDFPN8 (MLP8) Temperature range 6 = –40 to 85 °C Option blank = standard packing T = tape & reel packing Plating technology P or G = ECOPACK® (RoHS compliant) 1. The TSSOP8 package is available in products with process technology code X and Y (details of how to find the process on the device marking are given in application note AN1995). Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. 49/52 Revision history M25P05-A 13 Revision history Table 23. Date 25-Feb-2001 11-Apr-2002 12-Sep-2002 Document revision history Revision 1.0 1.1 1.2 Initial release. Clarification of descriptions of entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or dataout sequence. VFQFPN8 package (MLP8) added. Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after. Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. 40 MHz AC characteristics table included as well as 25 MHz. ICC3(max), tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8 package Devices with process technology code X added (Read identification (RDID) and Table 17: AC characteristics (50 MHz operation)) added. TSSOP8 package added. Notes 1 and 2 removed from Table 22: Ordering information scheme and Note 1 added. Note 1 to Table 9: Absolute maximum ratings changed, note 2 and TLEAD values removed. Small text changes. Frequency test condition modified for ICC3 in Table 13: DC characteristics. Read identification (RDID), Deep power-down (DP) and Release from deep power-down and read electronic signature (RES) instructions and Active power, standby power and deep power-down modes paragraph clarified. SO8 package specifications updated (see Figure 26. and Table 18). Updated Page Program (PP) instructions in Page programming, Page program (PP) and Instruction times. Packages are fully ECOPACK® compliant. SO8N and VFQFPN8 package specifications updated (see Section 11: Package mechanical). Figure 3: Bus master and memory devices on the SPI bus updated and Note 2 added. TLEAD removed from Section Table 9.: Absolute maximum ratings. Small text changes. VCC supply voltage and VSS ground descriptions added. Figure 3: Bus master and memory devices on the SPI bus updated, note 2 removed replaced by explanatory paragraph. WIP bit behavior at power-up specified in Section 7: Power-up and powerdown. TLEAD added and VIO max modified in Table 9: Absolute maximum ratings. VFQFPN8 and SO8N packages updated (see Section 11: Package mechanical). Changes 13-Dec-2002 1.3 24-Nov-2003 2 13-Jan-2005 3 01-Apr-2005 4 01-Aug-2005 5 06-Jul-2006 6 19-Dec-2006 7 50/52 M25P05-A Table 23. Date Revision history Document revision history (continued) Revision Changes Removed ‘low voltage’ from the title. Small text changes. Changed note below Table 12: Capacitance. Changed the minimum value for VCC (from 2.7 to 2.3 V). UFDFPN8 package (MLP8) added. Frequency test condition modified for ICC3 in Table 13: DC characteristics. tSE(typ), tBE(typ) and tPP(typ) values improved in Table 14: Instruction times. Changed maximum value for fR in Table 17: AC characteristics (50 MHz operation). Added the reference to a new process technology (code Y). Applied Numonyx branding. Updated Table 3: Bus master and memory devices on the SPI bus. Modified the code for UFDFPN8 package from ‘ZW’ to ‘MB’. Minor text changes. 07-Aug-2007 8 10-Oct-2007 10-Dec-2007 18-Apr-2008 9 10 11 51/52 M25P05-A Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 52/52