M29DW641F90N1E

M29DW641F 64 Mbit (4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory Features ■ Supply voltage – VCC = 2.7V to 3.6V for Program, Erase and Read – VPP/WP=12V for Fast Program (optional) Asynchronous Page Read mode – Page Width 8 Words – Page Access 25, 30ns – Random Access: 60, 70ns Programming Time – 10µs per Word typical – 4 Words at-a-time Program Memory blocks – Quadruple Bank Memory Array: 8Mbit+24Mbit+24Mbit+8Mbit – Parameter Blocks (at Top and Bottom) Dual Operations – While Program or Erase in a group of banks (from 1 to 3), Read in any of the other banks Program/Erase Suspend and Resume modes – Read from any Block during Program Suspend – Read and Program another Block during Erase Suspend Unlock Bypass Program command – Faster Production/Batch Programming Common Flash Interface – 64 bit Security Code 100,000 Program/Erase cycles per block Low power consumption – Standby and Automatic Standby Extended Memory Block – Extra block used as security block or to store additional information ■ ■ ■ TSOP48 (N) 12 x 20mm ■ FBGA ■ TFBGA48 (ZE) 6 x 8mm ■ Hardware Block Protection – VPP/WP Pin for fast program and write protect of the four outermost parameter blocks Software Block Protection – Standard Protection – Password Protection Electronic Signature – Manufacturer code: 0020h – Device code: 227Eh + 2203h + 2200h ECOPACK® packages ■ ■ ■ ■ ■ ■ ■ ■ December 2007 Rev 5 1/80 www.numonyx.com 1 Contents M29DW641F Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCC Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Verify Extended Block Protection indicator . . . . . . . . . . . . . . . . . . . . . . 17 Verify Block Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Temporary Unprotection of High voltage Protected Blocks . . . . . . . . . . 18 4 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 4.2 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/80 M29DW641F Contents 5.1 Standard Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 5.1.2 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Non-volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Password Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.1 5.2.2 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Non-volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Set Extended Block Protection bit command . . . . . . . . . . . . . . . . . . . . . 33 Verify Extended Block Protection bit command . . . . . . . . . . . . . . . . . . . 34 Password Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Password Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Password Protection Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . 35 Set Password Protection mode command . . . . . . . . . . . . . . . . . . . . . . . 35 Verify Password Protection mode command . . . . . . . . . . . . . . . . . . . . . 35 Set Standard Protection mode command . . . . . . . . . . . . . . . . . . . . . . . 35 3/80 Contents 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 M29DW641F Verify Standard Protection mode command . . . . . . . . . . . . . . . . . . . . . 36 Set Non-Volatile Modify Protection bit command . . . . . . . . . . . . . . . . . . 36 Verify Non-volatile Modify Protection bit command . . . . . . . . . . . . . . . . 36 Clear Non-volatile Modify Protection bit command . . . . . . . . . . . . . . . . 36 Set Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clear Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Verify Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Set Lock-Down bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Verify Lock-Down bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 7.2 7.3 7.4 7.5 Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 9 10 11 12 Dual Operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 45 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 C.1 C.2 Factory Locked section of the Extended Block . . . . . . . . . . . . . . . . . . . . . 71 Customer Lockable section of the Extended Block . . . . . . . . . . . . . . . . . . 72 Appendix D High voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4/80 M29DW641F Contents D.2 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5/80 List of tables M29DW641F List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Protection command addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Program, Erase Times and Program, Erase Endurance cycles . . . . . . . . . . . . . . . . . . . . . 40 Status Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Dual Operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dual Operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Toggle and alternative toggle bits AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 58 TFBGA48 6x8mm - 6x8 Active Ball Array, 0.8mm pitch, package mechanical data . . . . . 59 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Primary Algorithm-specific extended Query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Programmer technique Bus Operations, 8-bit or 16-bit mode . . . . . . . . . . . . . . . . . . . . . . 74 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6/80 M29DW641F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Protection state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Software Protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Toggle and alternative toggle bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . . 54 Toggle and alternative toggle bits mechanism, Output Enable controlled . . . . . . . . . . . . . 55 Reset/Block Temporary Unprotect AC waveforms (no Program/Erase ongoing) . . . . . . . . 55 Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms . . . . 56 Accelerated Program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 58 TFBGA48 6x8mm - 6x8 Active Ball Array, 0.8mm pitch, package outline . . . . . . . . . . . . . 59 Programmer equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Programmer equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 In-System equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 In-System equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7/80 Summary description M29DW641F 1 Summary description The M29DW641F is a 64 Mbit (4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory default to its Read mode. The device features an asymmetrical block architecture, with 16 parameter and 126 main blocks, divided into four Banks, A, B, C and D, providing Multiple Bank Operations. While programming or erasing is underway in one group of banks (from 1 to 3), reading can be conducted in any of the other banks. Table 2 summarizes the bank architecture. Eight of the Parameter Blocks are at the top of the memory address space, and eight are at the bottom. Program and Erase commands are written to the Command Interface of the memory. An onchip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase Operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The Chip Enable, Output Enable and Write Enable signals control the Bus Operation of the memories. They allow simple connection to most microprocessors, often without additional logic. The M29DW641F has one extra 128 Word block (Extended Block) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently, so it is possible to preserve valid data while old data is erased. The device features different levels of hardware and software block protection to avoid unwanted program or erase (modify). The software block protection features are available in 16 bit memory organization only: ● Hardware Protection: – – The VPP/WP provides a hardware protection of the four outermost parameter blocks (two at the top and two at the bottom of the address space). The RP pin temporarily unprotects all the blocks previously protected using a High voltage Block Protection technique (see Appendix D: High voltage Block Protection). Standard Protection Password Protection ● Software Protection – – The memory is offered in TSOP48 (12x20mm) and TFBGA48 (6x8mm, 0.8mm pitch) packages. In order to meet environmental requirements, Numonyx offers the M29DW641F in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The memory is supplied with all the bits erased (set to ’1’). 8/80 M29DW641F Figure 1. Logic diagram VCC VPP/WP Summary description 22 A0-A21 W E G RP M29DW641F 15 DQ0-DQ15 RB VSS AI11505 Table 1. A0-A21 DQ0-DQ15 E G W RP RB VCC VPP/WP VSS NC Signal names Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Supply voltage VPP/Write Protect Ground Not Connected Internally Table 2. Bank A B C D Bank architecture Bank size 8 Mbit 24 Mbit 24 Mbit 8 Mbit Parameter Blocks No. of Blocks 8 — — 8 Block size 4 KWord — — 4 KWord Main Blocks No. of Blocks 15 48 48 15 Block size 32 KWord 32 KWord 32 KWord 32 KWord 9/80 Summary description Figure 2. TSOP connections (top view through package) M29DW641F A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 12 37 M29DW641F 13 36 24 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 1. Balls are shorted together via the substrate but not connected to the die. 10/80 M29DW641F Figure 3. TFBGA48 connections (top view through package) 1 2 3 4 5 6 Summary description A A3 A7 RB W A9 A13 B A4 A17 VPP/WP RP A8 A12 C A2 A6 A18 A21 A10 A14 D A1 A5 A20 A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 F E DQ8 DQ10 DQ12 DQ14 NC G G DQ9 DQ11 VCC DQ13 DQ15 H VSS DQ1 DQ3 DQ4 DQ6 VSS AI11252b 1. Balls are shorted together via the substrate but not connected to the die. 11/80 Summary description Figure 4. Block addresses Address lines A21-A0 M29DW641F 000000h 000FFFh 8 Kbyte or 4 KWord Total of 8 Parameter Blocks 200000h 207FFFh Bank C 64 Kbyte or 32 KWord Total of 48 Main Blocks 007000h Bank A 007FFFh 008000h 00FFFFh 8 Kbyte or 4 KWord 64 Kbyte or 32 KWord Total of 15 Main Blocks 378000h 37FFFFh 380000h 387FFFh 64 Kbyte or 32 KWord 64 Kbyte or 32 KWord Total of 15 Main Blocks 078000h 07FFFFh 080000h 087FFFh Bank B 64 Kbyte or 32 KWord Bank D 64 Kbyte or 32 KWord Total of 48 Main Blocks 3F0000h 3F7FFFh 3F8000h 3F8FFFh 64 Kbyte or 32 KWord 8 Kbyte or 4 KWord Total of 8 Parameter Blocks 1F8000h 1FFFFFh 64 Kbyte or 32 KWord 3FF000h 3FFFFFh 8 Kbyte or 4 KWord AI05555 1. Also see Appendix A, Table 28 for a full listing of the Block Addresses. 12/80 M29DW641F Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address Inputs (A0-A21) The Address Inputs select the cells in the memory array to access during Bus Read Operations. During Bus Write Operations they control the commands sent to the Command Interface of the internal state machine. 2.2 Data Inputs/Outputs (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read Operation. During Bus Write Operations they represent the commands sent to the Command Interface of the Program/Erase Controller. 2.3 Chip Enable (E) The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write Operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.4 Output Enable (G) The Output Enable, G, controls the Bus Read Operation of the memory. 2.5 Write Enable (W) The Write Enable, W, controls the Bus Write Operation of the memory’s Command Interface. 2.6 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin is both a power supply and a write protect pin. When VPP/Write Protect is Low, VIL, it is seen as a write protect pin protecting the four outermost parameter blocks (two at the top, and two at the bottom of the address space). Program and erase Operations in these blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection state of the four outermost parameter blocks. Program and Erase Operations can now modify the data in these blocks unless the blocks are protected using Block Protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the four outermost parameter blocks) using a High voltage Block Protection 13/80 Signal descriptions M29DW641F technique (In-System or Programmer technique). See Table 6: Hardware Protection for details. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. 2.7 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all the blocks previously protected using a High voltage Block Protection technique (In-System or Programmer technique). Note that if VPP/WP is at VIL, then the four outermost parameter blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. If RP is asserted during a Program or Erase Operation, the RB pin remains Low (busy), until the internal Reset Operation is completed, which requires a tPLYH time (see Figure 18: Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms). The RB signal can be monitored by the system microprocessor to determine whether the Reset Operation is completed or not. If RP is asserted when no Program or Erase Operation is ongoing, the RB pin remains high, VIH. A tPHEL or tPHGL delay elapses before the Reset Operation is completed and RP returns to High, VIH. After this delay, the memory is ready for Bus Read and Bus Write Operations. Holding RP at VID will temporarily unprotect all the blocks previously protected using a High voltage Block Protection technique. Program and Erase Operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. See the Ready/Busy Output section, Table 24: Reset/Block Temporary Unprotect AC characteristics and Figure 18: Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms for more details. 2.8 Ready/Busy Output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase Operation. During Program or Erase Operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write Operations cannot begin until Ready/Busy becomes high-impedance. See Table 24 and Figure 18: Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 14/80 M29DW641F Signal descriptions 2.9 VCC Supply voltage VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply voltage is less than the Lockout voltage, VLKO. This prevents Bus Write Operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase Operations, ICC3. 2.10 VSS Ground VSS is the reference for all voltage measurements. The device features two VSS pins both of which must be connected to the system ground. 15/80 Bus Operations M29DW641F 3 Bus Operations There are five standard Bus Operations that control the device. These are Bus Read (Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby. Dual Operations are possible in the M29DW641F, thanks to their multiple bank architecture. While programming or erasing in one banks, Read Operations are possible in any of the other banks. Write Operations are only allowed in one bank at a time. See Table 3: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the memory and do not affect Bus Operations. 3.1 Bus Read Bus Read Operations read from the memory cells, or specific registers in the Command Interface. To speed up the Read Operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 8 Words and is addressed by the address inputs A0-A2. A valid Bus Read Operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11: Random Read AC waveforms, Figure 12: Page Read AC waveforms, and Table 20: Read AC characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write Operations write to the Command Interface. A valid Bus Write Operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write Operation. See Figure 13 and Figure 14, Write AC Waveforms, and Table 21 and Table 22, Write AC Characteristics, for details of the timing requirements. 3.3 Output Disable The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to the Standby Supply current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 19: DC characteristics. During program or Erase Operations the memory will continue to use the Program/Erase Supply current, ICC3, for Program or Erase Operations until the operation completes. 16/80 M29DW641F Bus Operations 3.5 Automatic Standby If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply current is reduced to the Standby Supply current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read Operation is in progress. 3.6 Special Bus Operations Additional Bus Operations can be performed to read the Electronic Signature, verify the Protection status of the Extended Memory Block (second section), and apply or remove Block Protection. These Bus Operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.6.1 Read Electronic Signature The memory has two codes, the Manufacturer code and the Device code used to identify the memory. These codes can accessed by performing Read Operations with control signals and addresses set as shown in Table 3: Bus Operations. These codes can also be accessed by issuing an Auto Select command (see Section 6: Command interface, Section 6.1.2: Auto Select command). 3.6.2 Verify Extended Block Protection indicator The Extended Block is divided in two sections of which one is Factory Locked and the second one is either Customer Lockable or Customer Locked. The Protection status of the second section of the Extended Block (Customer Lockable or Customer Locked) can be accessed by reading the Extended Block Protection indicator. This is done by applying the signals listed in Table 5: Block Protection. The Protection status of the Extended Block is then output on bits DQ7 and DQ6 of the Data Input/Outputs. (see Table 3: Bus Operations). The Protection status of the Extended Block can also be accessed by issuing an Auto Select command (see Section 6: Command interface, Section 6.1.2: Auto Select command). 3.6.3 Verify Block Protection status The Protection status of a Block can be directly accessed by performing a Read Operation with control signals and addresses set as shown in Table 5: Block Protection. If the Block is protected, then 0001h is output on Data Input/Outputs, otherwise 0000h is output. 3.6.4 Hardware Block Protect The VPP/WP pin can be used to protect the four outermost parameter blocks. When VPP/WP is at VIL the four outermost parameter blocks are protected and remain protected regardless of the Block Protection status or the Reset/Block Temporary Unprotect pin state. 17/80 Bus Operations M29DW641F 3.6.5 Temporary Unprotection of High voltage Protected Blocks The RP pin can be used to temporarily unprotect all the blocks previously protected using the In-System or the Programmer Protection technique (High voltage techniques). Refer to Section 2.7: Reset/Block Temporary Unprotect (RP) in the Section 2: Signal descriptions. Table 3. Bus Operations(1) Address Inputs Operation Bus Read Bus Write Output Disable Standby 1. X = VIL or VIH. Data Inputs/Outputs DQ15-DQ0 Data Output Data Input Hi-Z Hi-Z E VIL VIL X VIH G VIL VIH VIH X W A21-A0 VIH VIL VIH X Cell Address Command Address X X Table 4. Read Electronic Signature(1) Address Inputs Data Inputs/Outputs DQ15-DQ0 0020h 227Eh 2203h 2200h (M29DW641F) Read cycle E G W A21A10 A9 A8 A7-A6 A5-A4 A3 A2 A1 A0 X VIL VIL VIL VIL VIL VIL VIL VIH Manufacturer code Device code (Cycle 1) Device code (Cycle 2) Device code (Cycle 3) 1. X = VIL or VIH. VIL VIL VIH X VID X VIL VIL VIH VIH VIH VIL VIH VIH VIH VIH 18/80 M29DW641F Table 5. Operation Bus Operations Block Protection(1) Address Inputs E G W RP VPP/WP A21- A11A5- A3A9 A8 A7 A6 A1 A0 A12 A10 A4 A2 Data Inputs/Outputs DQ15-DQ0 Verify Extended Block indicator (bits DQ6, DQ7) VIL VIL VIH VIH Verify Block Protection status Temporary Block Unprotect(4) 1. X = VIL or VIH. BA VIH BKA (3) X X VID X VIL VIL X VIL VIH VIL 0080h (Customer Lockable) VIH 00C0h (Customer Locked)(2) VIL 0001h (protected) 0000h (unprotected) X X X VID X Valid Data Input 2. This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block being always Factory Locked. 3. BKA Bank Address, BA Any Address in the Block. 4. The RP pin unprotects all the blocks that have been previously protected using a High voltage Protection Technique. 19/80 Hardware Protection M29DW641F 4 Hardware Protection The M29DW641F features hardware Protection/Unprotection. Refer to Table 6 for details on Hardware Block Protection/unprotection using VPP/WP and RP pins. 4.1 Write Protect The VPP/WP pin protects the four outermost parameter blocks (refer to Section 2: Signal descriptions for a detailed description of the signals). 4.2 Temporary Block Unprotect When held at VID, the Reset/Block Temporary Unprotect pin, RP, will temporarily unprotect all the blocks previously protected using a High voltage Block Protection technique. Table 6. VPP/WP Hardware Protection(1) RP VIH Function 4 outermost parameter blocks protected from Program/Erase Operations All blocks temporarily unprotected except the 4 outermost blocks All blocks temporarily unprotected All blocks temporarily unprotected VIL VID VIH or VID VPPH VID VIH or VID 1. The temporary unprotection is valid only for the blocks that have been protected using the High voltage Protection Technique (see Appendix D: High voltage Block Protection). The blocks protected using a Software Protection method (Standard or Password) do not follow this rules. 20/80 M29DW641F Software Protection 5 Software Protection The M29DW641F has two different Software Protection modes: the Standard and Password Protection modes. On first use all parts default to the Standard Protection mode and the customer is free to activate the Standard or the Password Protection mode. The desired protection mode is activated by setting one of two one-time programmable bits, the Standard Protection mode Lock bit or the Password Protection mode Lock bit. Programming the Standard or the Password Protection mode Lock bit to ‘1’ will permanently activate the Standard or the Password Protection mode, respectively. These two bits are one-time programmable and non-volatile, once the Protection mode has been programmed, it cannot be changed and the device will permanently operate in the selected Protection mode. It is recommended to activate the desired Software Protection mode when first programming the device. The device is shipped with all blocks unprotected. The Block Protection status can be read by issuing the Auto Select command (see Table 7: Block Protection status). The Standard and Password Protection modes offer two levels of protection, a Block Lock/Unlock protection and a Non-volatile Protection. For the four outermost parameter blocks, an even higher level of block protection can be achieved by locking the blocks using the Non-volatile Protection and then by holding the VPP/WP pin Low. 5.1 5.1.1 Standard Protection mode Block Lock/Unlock Protection It is a flexible mechanism to protect/unprotect a block or a group of blocks from Program or Erase Operations. A volatile Lock bit is assigned to each block or group of blocks. When the lock bit is set to ‘1’ the associated block or group of blocks is protected from Program/Erase Operations, when the Lock bit is set to ‘0’ the associated block or group of blocks is unprotected and can be programmed or erased. The Lock bits can be set (‘1’) and cleared (‘0’) individually as often as required by issuing a Set Lock bit command and Clear Lock bit command, respectively. After a Power-up or Hardware Reset, all the Lock bits are cleared to ‘0’ (block unlocked). The device is shipped with all the Lock bits set to ‘0’. 21/80 Software Protection M29DW641F 5.1.2 Non-volatile Protection A Non-Volatile Modify Protection bit is assigned to each block or group of blocks. When a Non-Volatile Modify Protection bit is set to ‘1’, the associated block or group of blocks is protected, preventing any Program or Erase Operations in this block or group of blocks. The Non-Volatile Modify Protection bits are set individually by issuing a Set Non-Volatile Modify Protection bit command. They are non-volatile and will remain set through a hardware reset or a power-down/power-up sequence. The Non-Volatile Modify Protection bits cannot be cleared individually, they can only be cleared all at the same time by issuing a Clear Non-Volatile Modify Protection bits command. The device features a volatile Lock-Down bit which can be used to prevent changing the state of the Non-Volatile Modify Protection bits. When set to ‘1’, the Non-Volatile Modify Protection bits can no longer be modified; when set to ‘0’, the Non-Volatile Modify Protection bits can be set and reset using the Set Non-Volatile Modify Protection bit command and the Clear Non-Volatile Modify Protection bits command, respectively. The Lock-Down bit is set by issuing the Set Lock-Down bit command. It is not cleared using a command, but through a hardware reset or a power-down/power-up sequence. The part is shipped with the Non-Volatile Modify Protection bits set to ‘0’. Locked blocks and Non-Volatile Locked blocks can co-exist in the same memory array. Refer to Table 7: Block Protection status and Figure 6: Software Protection scheme for details on the block protection mechanism. 5.2 Password Protection mode The Password Protection mode provides a more advanced level of software protection than the Standard Protection mode. Prior to entering the Password Protection mode, it is necessary to set a password and to verify it (see Section 6.3.5: Password Program command and Section 6.3.6: Password Verify command). The Password Protection mode is then activated by programming the Password Protection mode Lock bit to ‘1’. This operation is not reversible and once the bit is programmed the device will permanently remain in the Password Protection mode. The Password Protection mode uses the same protection mechanisms as the Standard Protection mode (Block Lock/Unlock, Non-volatile Protection). 5.2.1 Block Lock/Unlock Protection The Block Lock/Unlock Protection operates exactly in the same way as in the Standard Protection mode. 22/80 M29DW641F Software Protection 5.2.2 Non-volatile Protection The Non-Volatile Protection is more advanced in the Password Protection mode. In this mode, the Lock-Down bit is non-volatile and cannot be cleared through a hardware reset or a power-down/power-up sequence. The Lock-Down bit is cleared by issuing the Password Protection Unlock command along with the correct password. Once the correct Password has been provided, the Lock-Down bit is cleared and the Non-Volatile Modify Protection bits can be set or reset using the appropriate commands (the Set Non-Volatile Modify Protection bit command or the Clear Non-Volatile Modify Protection bits command, respectively). If the Password provided is not correct, the Lock-Down bit remains locked and the state of the NonVolatile Modify Protection bits cannot be modified. The Password is a 64-bit code located in the memory space. It must be programmed by the user prior to selecting the Password Protection mode. The Password is programmed by issuing a Password Program command and checked by issuing a Password Verify command. The Password should be unique for each part. Once the device is in Password Protection mode, the Password can no longer be read or retrieved. Moreover, all commands to the address where the password is stored, are disabled. Refer to Table 7 and Figure 6: Software Protection scheme for details on the block protection scheme. Table 7. Block Protection status Lock-Down bit 0 0000h 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0001h Block Program/Erase Protected Non-volatile Modify Protection bit can be modified(1) Block Protection status Block Unprotected Block Protection status Non-volatile Modify Protection bit can be modified(1) Non-volatile Modify Protection bit cannot be modified(1) Non-volatile Volatile Modify Protection Lock bit bit 0 0 Non-volatile Modify Protection bit cannot be modified(1) 1. The Lock bit can always be modified by issuing a Clear Lock bit command or by taking the device through a Power-up or Hardware Reset. 23/80 Software Protection Figure 5. Block Protection state diagram Default: Standard Protection M29DW641F Set Standard Protection Mode Set Password Protection Mode Standard Protection Password Protection ai11503 Figure 6. Software Protection scheme Parameter Block or Up to 4 Main Blocks Lock bit Non-Volatile Modify Protection bit Lock-Down bit Standard Protection mode Block Lock/Unlock Protection Non-Volatile Protection Password Protection mode AI11504 24/80 M29DW641F Command interface 6 Command interface All Bus Write Operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write Operations. Failure to observe a valid sequence of Bus Write Operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. 6.1 Standard commands See Table 8: Standard commands for a summary of the Standard commands. 6.1.1 Read/Reset command The Read/Reset command returns the memory to Read mode. It also resets the errors in the Status Register. Either one or three Bus Write Operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a Program or Erase Operation, to return the device to Read mode. If the Read/Reset command is issued during the time-out of a Block Erase Operation, the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase Operation when issued while in Erase Suspend. 6.1.2 Auto Select command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Protection status of each block (Block Protection status) and the Extended Block Protection indicator. It can be addressed to either Bank. Three consecutive Bus Write Operations are required to issue the Auto Select command. Once the Auto Select command is issued, Bus Read Operations to specific addresses output the Manufacturer Code, the Device Code, the Extended Block Protection indicator and a Block Protection status (see Table 8: Standard commands in relation with Table 4 and Table 5). The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. 25/80 Command interface M29DW641F 6.1.3 Read CFI Query command The Read CFI Query command is used to put the addressed bank in Read CFI Query mode. Once in Read CFI Query mode, Bus Read Operations to the same bank will output data from the Common Flash Interface (CFI) Memory Area. If the Read Operations are to a different bank from the one specified in the command then the Read Operations will output the contents of the memory array and not the CFI data. One Bus Write cycle is required to issue the Read CFI Query command. Care must be taken to issue the command to one of the banks (A21-A19) along with the address shown in Table 3 Once the command is issued subsequent Bus Read Operations in the same bank (A21-A19) to the addresses shown in Appendix B (A7-A0), will read from the Common Flash Interface Memory Area. This command is valid only when the device is in the Read Array or Auto Select mode. To enter Read CFI query mode from Auto Select mode, the Read CFI Query command must be issued to the same bank address as the Auto Select command, otherwise the device will not enter Read CFI Query mode. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command is required to put the device in Read Array mode from Auto Select mode. See Appendix B, Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 for details on the information contained in the Common Flash Interface (CFI) memory area. 6.1.4 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write Operations are required to issue the Chip Erase command and start the Program/Erase Controller. If any blocks are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase Operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Erase Operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 12. All Bus Read Operations during the Chip Erase Operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase Operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 26/80 M29DW641F Command interface 6.1.5 Block Erase command The Block Erase command can be used to erase a list of one or more blocks in one or more Banks. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Six Bus Write Operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write Operation using the address of the additional block. The Block Erase Operation starts the Program/Erase Controller after a time-out period of 50µs after the last Bus Write Operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. After the sixth Bus Write Operation a Bus Read Operation within the same Bank will output the Status Register. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase Operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase Operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase Operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50µs time-out period. Typical block erase times are given in Table 12. After the Erase Operation has started all Bus Read Operations to the Banks being erased will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase Operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read Operations to the Banks where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. 6.1.6 Erase Suspend command The Erase Suspend command may be used to temporarily suspend a Block or multiple Block Erase Operation. One Bus Write Operation specifying the Bank Address of one of the Blocks being erased is required to issue the command. Issuing the Erase Suspend command returns the whole device to Read mode. The Program/Erase Controller will suspend within the Erase Suspend Latency time (see Table 12 for value) of the Erase Suspend command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program Operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and 27/80 Command interface M29DW641F no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read Operation to the Extended Block will output the Extended Block data. Once in the Extended Block mode, the Exit Extended Block command must be issued before the Erase Operation can be resumed. 6.1.7 Erase Resume command The Erase Resume command is used to restart the Program/Erase Controller after an Erase Suspend. The command must include the Bank Address of the Erase-Suspended Bank, otherwise the Program/Erase Controller is not restarted. The device must be in Read Array mode before the Resume command will be accepted. An Erase can be suspended and resumed more than once. 6.1.8 Program Suspend command The Program Suspend command allows the system to interrupt a Program Operation so that data can be read from any block. When the Program Suspend command is issued during a Program Operation, the device suspends the Program Operation within the Program Suspend Latency time (see Table 12 for value) and updates the Status Register bits. The Bank Addresses of the Block being programmed must be specified in the Program Suspend command. After the Program Operation has been suspended, the system can read array data from any address. However, data read from Program-Suspended addresses is not valid. The Program Suspend command may also be issued during a Program Operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time Program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. 6.1.9 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the Program Operation using the DQ7 or DQ6 status bits, just as in the standard Program Operation. See Write Operation status for more information. The system must write the Program Resume command, specifying the Bank addresses of the Program-Suspended Block, to exit the Program Suspend mode and to continue the Programming Operation. 28/80 M29DW641F Command interface Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 6.1.10 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write Operations, the final Write Operation latches the address and data in the internal state machine and starts the Program/Erase Controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.8: Program Suspend command and Section 6.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. After programming has started, Bus Read Operations in the Bank being programmed output the Status Register content, while Bus Read Operations to the other Bank output the contents of the memory array. See the section on the Status Register for more details. Typical program times are given in Table 12. After the Program Operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read Operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 6.1.11 Verify command The Verify command is used to check if a block is blank or in other words, if it has been successfully erased and all its bits set to ’1’. It reads the value of the Error bit DQ5. If the Error bit is set to ’1’, it indicates that the operation failed. Three cycles are required to issue a Verify command: 1. 2. The command starts with two unlock cycles. The third Bus Write cycle sets up the Verify command code along with the address of the block to be checked. 29/80 Command interface Table 8. Standard commands Bus Operations(1)(2) Command Length 1st Add 1 Read/Reset 3 Manufacturer code Device code Auto Select Extended Block Protection indicator Block Protection status Program Verify Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 3 6 6+ 1 1 1 555 555 555 555 BKA BKA (BKA) 555 AA AA AA AA B0 30 98 2AA 2AA 2AA 2AA 55 55 55 55 555 BA 555 555 A0 BC 80 80 555 555 AA AA 2AA 2AA PA PD 3 555 AA 2AA 55 (BKA) 555 90 (3) (3) M29DW641F 2nd 3rd Add 4th 5th 6th Data Add Data F0 AA 2AA 55 Data Add Data Add Data Add Data X 555 X F0 55 55 555 BA 10 30 1. Grey cells represent Read cycles. The other cells are Write cycles. 2. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in hexadecimal. 3. The Auto Select addresses and data are given in Table 4: Read Electronic Signature, and Table 5: Block Protection, except for A9 that is ‘Don’t Care’. 30/80 M29DW641F Command interface 6.2 Fast Program commands The M29DW641F offers a set of Fast Program commands to improve the programming throughput: ● ● Double and Quadruple Word, Program Unlock Bypass When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast Program mode. The user can then choose to issue any of the Fast Program commands. Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any protected block. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. After programming has started, Bus Read Operations in the Bank being programmed output the Status Register content, while Bus Read Operations to the other Bank output the contents of the memory array. Fast Program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.8: Program Suspend command and Section 6.1.9: Program Resume command). After the Fast Program command has completed, the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read Operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 12: Program, Erase Times and Program, Erase Endurance cycles. See either Table 9: Fast Program commands, for a summary of the Fast Program commands. 6.2.1 Double Word Program command This is used to write two adjacent Words simultaneously. The addresses of the two Words must differ only in A0. Three bus write cycles are necessary to issue the command: 1. 2. 3. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written and starts the Program/Erase Controller. 6.2.2 Quadruple Word Program command This is used to write four adjacent Words simultaneously. The addresses of the four Words must differ only in A1 and A0. Five bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written. The fourth bus cycle latches the Address and the Data of the third Word to be written. The fifth bus cycle latches the Address and the Data of the fourth Word to be written and starts the Program/Erase Controller. 31/80 Command interface M29DW641F 6.2.3 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write Operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can then be issued to program addresses within the bank, or the Unlock Bypass Reset command can be issued to return the bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. 6.2.4 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write Operations, the final Write Operation latches the address and data and starts the Program/Erase Controller. The Program Operation using the Unlock Bypass Program command behaves identically to the Program Operation using the Program command. The operation cannot be aborted, a Bus Read Operation to the Bank where the command was issued outputs the Status Register. See the Program command for details on the behavior. 6.2.5 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write Operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode. Table 9. Fast Program commands Bus Write Operations(2) Command(1) Length 1st 2nd 3rd Add PA1 PA1 555 4th 5th 6th Add Data Add Data Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset 3 5 3 2 2 555 555 555 X X 50 56 AA A0 90 PA0 PA0 2AA PA X PD0 PD0 55 PD 00 Data Add Data Add Data Add Data PD1 PD1 PA2 PD2 PA3 PD3 20 1. The sequence consisting in 555 AA 2AA 55 X 25 is reserved and must not be issued. 2. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write Buffer Location. All values in the table are in hexadecimal. 32/80 M29DW641F Command interface 6.3 Block Protection commands Blocks or groups of blocks can be protected against accidental program, Erase or Read Operations. The Protection Groups are shown in Appendix A, Table 28: Block Addresses. The device block protection scheme is shown in Figure 6: Software Protection scheme and Figure 5: Block Protection state diagram. See Table 10: Block Protection commands, for a summary of the Block Protection commands. Only the commands related to the Extended Block Protection are available in both 8 bit and 16 bit memory configuration. The other block protection commands are available in 16-bit configuration only. 6.3.1 Enter Extended Block command The M29DW641F has one extra 128-Word block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus Write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Program Operations to the Extended Block Addresses (see Table 28: Block Addresses). The Extended Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode only array cell locations (Bank A) with the same addresses as the Extended Block are not accessible. In Extended Block mode Dual Operations are allowed and the Extended Block physically belongs to Bank A. In Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume commands are not allowed. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected by setting the Extended Block Protection bit to ‘1’; however once protected the protection cannot be undone. 6.3.2 Exit Extended Block command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write Operations are required to issue the command. 6.3.3 Set Extended Block Protection bit command The Set Extended Block Protection bit command programs the Extended Block Protection bit to ‘1’ thus preventing the second section of the Extended Block from being programmed. A Read/Reset command must be issued to abort a Set Extended Block Protection bit command. Six successive steps are required to issue the Set Extended Block Protection bit command. 1. 2. 3. The command starts with two unlock cycles. The third Bus Write cycle sets up the Set Extended Block Protection bit command. The last three cycles verify the value programmed at the Extended Block Protection bit address: if bit DQ0 of Data Inputs/Outputs is set to ’1’, it indicates that the Extended Block Protection bit has been successfully programmed. If DQ0 is ‘0’, the Set Extended Block Protection bit command must be issued and verified again. 33/80 Command interface M29DW641F 6.3.4 Verify Extended Block Protection bit command The Verify Extended Block Protection bit command reads the status of the Extended Block Protection bit on bit DQ0 of the Data Inputs/Outputs. If DQ0 is ‘1’, the second section of the Extended Block is protected from Program Operations. 6.3.5 Password Program command The Password Program command is used to program the 64-bit Password used in Password Protection mode. Four cycles are required to program the Password: 1. 2. 3. The first two cycles are unlock cycles. The third cycle issues the Password Program command. The fourth cycle inputs the 16-bit data required to program the Password. To program the 64-bit Password, the complete command sequence must be entered four times at four consecutive addresses selected by A1 to A0. Read Operations can be used to read the Status Register during a Password Program Operation. All other operations are forbidden. The Password can be checked by issuing a Password Verify command. Once Password Program Operation has completed, a Read/ Reset command must be issued to return the device to Read mode. The Password Protection mode can then be selected. By default, all Password bits are set to ‘1’. 6.3.6 Password Verify command The Password Verify command is used to verify the Password used in Password Protection mode. To verify the 64-bit Password, the complete command sequence must be entered four times at four consecutive addresses selected by A1 to A0. If this command is issued while the device is in Password Protection mode, it outputs ‘FFh’ and all Inputs/Outputs are high impedance. The Password is output regardless of the bank address. The user must issue a Read/reset command to return the device to Read mode. Dual Operations are not allowed during a Password Verify Operation. 34/80 M29DW641F Command interface 6.3.7 Password Protection Unlock command The Password Protection Unlock command is used to clear the Lock-Down bit in order to unprotect all Non-Volatile Modify Protection bits when the device is in Password Protection mode. The Password Protection Unlock command must be issued along with the correct Password. The complete command sequence must be entered for each 16 bits of the Password. There must be a 2µs delay between successive Password Protection Unlock commands in order to prevent hackers from cracking the Password by trying all possible 64-bit combinations. If this delay is not respected, the latest command will be ignored. 6.3.8 Set Password Protection mode command The Set Password Protection mode command puts the device in Password Protection mode by programming the Password Protection mode Lock bit to ‘1’. This command can be issued either with the Reset/Block Temporary Unprotect pin, RP, at VID or at VIH. Six cycles are required to issue a Set Password Protection mode command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the command. The fourth and fifth cycles select the address (see Table 11: Protection command addresses). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the device has successfully entered the Password Protection mode. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. Once the Password Protection mode is activated the device will permanently remain in this mode. 6.3.9 Verify Password Protection mode command The Verify Password Protection mode command reads the status of the Password Protection mode Lock bit. If it is ‘1’, the device is in Password Protection mode. 6.3.10 Set Standard Protection mode command The Set Standard Protection mode command puts the device in Standard Protection mode by programming the Standard Protection mode Lock bit to ‘1’. Six cycles are required to issue the Standard Protection mode command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the program command. The fourth and fifth cycles select the address (see Table 11: Protection command addresses). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the Standard Protection mode has been successfully activated. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. Once the Standard Protection mode is activated the device will permanently remain in this mode. 35/80 Command interface M29DW641F 6.3.11 Verify Standard Protection mode command The Verify Standard Protection mode command reads the status of the Standard Protection mode Lock bit. If it is ‘1’, the device is in Standard Protection mode. 6.3.12 Set Non-Volatile Modify Protection bit command A block or group of blocks can be protected from program or erase by issuing a Set NonVolatile Modify Protection bit command along with the block address. This command sets the Non-Volatile Modify Protection bit to ‘1’ for a given block or group of blocks. Six cycles are required to issue the command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the program command. The fourth and fifth cycles select the address (see Table 11: Protection command addresses). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the NonVolatile Modify Protection bit has been successfully programmed. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. The Non-Volatile Modify Protection bits are erased simultaneously by issuing a Clear NonVolatile Modify Protection bits command except if the Lock-Down bit is set to ‘1’. The Non-Volatile Modify Protection bits can be set a maximum of 100 times. 6.3.13 Verify Non-volatile Modify Protection bit command The status of a Non-Volatile Modify Protection bit for a given block or group of blocks can be read by issuing a Verify Non-Volatile Modify Protection bit command along with the block address. 6.3.14 Clear Non-volatile Modify Protection bit command This command is used to clear all Non-Volatile Modify Protection bits. No specific block address is required. If the Lock-Down bit is set to ‘1’, the command will fail. Six cycles are required to issue a Clear Non-Volatile Modify Protection bits command: 1. 2. 3. The first two cycles are unlock cycles. The third cycle issues the command. The last three cycles verify if the operation has been successful. If DQ0 is set to ’1’, all Non-Volatile Modify Protection bits have been successfully cleared. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 12ms delay between the fourth and fifth cycles. 6.3.15 Set Lock bit command The Set Lock bit command individually sets the Lock bit to ‘1’ for a given block or group of blocks. If the Non-Volatile Lock bit for the same block or group of blocks is set, the block is locked regardless of the value of the Lock bit. (see Table 7: Block Protection status). 36/80 M29DW641F Command interface 6.3.16 Clear Lock bit command The Clear Lock bit command individually clears (sets to ‘0’) the Lock bit for a given block or group of blocks. If the Non-Volatile Lock bit for the same block or group of blocks is set, the block or group of blocks remains locked (see Table 7: Block Protection status). 6.3.17 Verify Lock bit command The status of a Lock bit for a given block can be read by issuing a Verify Lock bit command along with the block address. 6.3.18 Set Lock-Down bit command This command is used to set the Lock-Down bit to ‘1’ thus protecting the Non-Volatile Modify Protection bits from program and erase. There is no Unprotect Lock-Down bit command. 6.3.19 Verify Lock-Down bit command This command is used to read the status of the Lock-Down bit. The status is output on bit DQ1. If DQ1 is ‘1’, all the Non-Volatile Modify Protection bits are protected from Program or Erase Operations. 37/80 Command interface Table 10. Block Protection commands Bus Write Operations(1)(2)(3) Command Length 1st 2nd 3rd 4th Data 68 Add OW 5th Data 48 Add OW 6th M29DW641F 7th Add Data Add Data Add Data Add Data Add Set Extended Block Protection bit(4) Verify Extended Block Protection bit Enter Extended Block Exit Extended Block Password Program(4) Password Verify Password Protection Unlock Set Password Protection mode(4)(5) Verify Password Protection mode Set NonVolatile Modify Protection bit (4)(5) Data DQ0 6 555 AA 2AA 55 555 60 OW 4 555 AA 2AA 55 555 60 OW DQ0 3 4 4 4 555 555 555 555 AA 2AA AA 2AA AA 2AA AA 2AA 55 55 55 55 555 555 555 555 88 90 38 C8 X X [0-3] 00 PW [0-3] PWA RPW [0-3] [0-3] PWA RPW PWA [0] [0] [1] RPW [1] PWA [2] RPW [2] PW RPW [3] [3] 7 555 AA 2AA 55 555 28 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL DQ0 4 555 AA 2AA 55 555 60 PL DQ0 6 555 AA 2AA 55 555 60 (BA)/ NVMP 68 (BA)/ NVMP 48 (BA)/ NVMP DQ0 Verify NonVolatile Modify Protection bit Clear NonVolatile Modify Protection bits(6)(7) Set Lock-Down bit Verify LockDown bit Set Lock bit Clear Lock bit 4 555 AA 2AA 55 555 60 (BA)/ NVMP 48 (BA)/ NVMP DQ0 6 555 AA 2AA 55 555 60 NVMP 60 (BA)/ NVMP 40 (BA)/ NVMP DQ0 3 4 4 4 555 555 555 555 AA 2AA AA 2AA AA 2AA AA 2AA 55 55 55 55 555 555 555 555 78 58 48 48 BA BA BA DQ1 X1h X0h 38/80 M29DW641F Table 10. Block Protection commands (continued) Bus Write Operations(1)(2)(3) Command Length 1st 2nd 3rd 4th Data DQ0 68 SL 48 SL Add 5th Data Command interface 6th Add Data 7th Add Data Add Data Add Data Add Data Add Verify Lock bit Set Standard Protection mode(5) Verify Standard Protection mode(4) 4 6 555 555 AA 2AA AA 2AA 55 55 555 555 58 60 BA SL DQ0 4 555 AA 2AA 55 555 60 SL DQ0 1. The grey cell represent Read cycles. The other cells are Write cycles. 2. SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection mode Lock bit Address, PL Password Protection mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X Don’t Care. All values in the table are in hexadecimal. 3. Refer to Table 11: Protection command addresses for addresses. 4. A Reset command must be issued to return to the Read mode. 5. The 4th Bus Write cycle programs a protection bit (Extended Block Protection bit, Password, Standard Protection mode Lock bits, and a block NVMP bit). The 5th and 6th cycles verify that the bit has been successively programmed when DQ0=1. If DQ0=0 in the 6th cycle, the program command must be issued again and verified again. A 100µs delay is required between the 4th and the 5th cycle. 6. Cycle 4 erases all Non-Volatile Modify Protection bits. Cycles 5 and 6 verify that the bits have been successfully cleared when DQ0=0. If DQ0=1 in the 6th cycle, the erase command must be issued again and verified again. Before issuing the erase command, all Non-Volatile Modify Protection bits should be programmed to prevent over erasure. 7. A 12ms timeout is required between cycles 4 and 5. Table 11. Protection command addresses Bit Condition RP at VIH RP at VID Address inputs A7-A0 00001010 10001010 00010010 00000010 00011010 Other Address Inputs X X X Block Protection Group Address X Password Protection mode Lock bit Address (PL) Standard Protection mode Lock bit Address (SL) Non-Volatile Modify Protection bit Address (NVMP) Extended Block Protection bit Address (OW) 39/80 Command interface Table 12. M29DW641F Program, Erase Times and Program, Erase Endurance cycles Parameter Min Typ(1)(2) 80 0.8 Max(2) 400(3) 6 (4) Unit s s µs µs s s s µs Cycles Years Chip Erase Block Erase (32 KWords) Erase Suspend Latency Time Word Program Single or Multiple Word Program (1, 2 or 4 Words at-a-time) 50(4) 10 40 20 10 200(3) 200(3) 100 (3) Chip Program (Word by Word) Chip Program (Double Word) Chip Program (Quadruple Word) Program Suspend Latency Time Program/Erase cycles (per Block) Data Retention 100,000 20 50(3) 4 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC. 40/80 M29DW641F Status Register 7 Status Register The M29DW641F has one Status Register. The Status Register provides information on the current or previous Program or Erase Operations executed in each bank. The various bits convey information and errors on the operation. Bus Read Operations from any address within the Bank, always read the Status Register during Program and Erase Operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 13: Status Register bits. 7.1 Data polling bit (DQ7) The Data Polling bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling bit is output on DQ7 when the Status Register is read. During Program Operations the Data Polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program Operation the memory returns to Read mode and Bus Read Operations from the address just programmed output DQ7, not its complement. During Erase Operations the Data Polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase Operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read Operation within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase Operation. Figure 7: Data polling flowchart, gives an example of how to use the Data Polling bit. A Valid Address is the address being programmed or an address within the block being erased. 7.2 Toggle bit (DQ6) The Toggle bit can be used to identify whether the Program/Erase Controller has successfully completed its Operation or if it has responded to an Erase Suspend. The Toggle bit is output on DQ6 when the Status Register is read. During Program and Erase Operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read Operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle bit will output when addressing a cell within a block being erased. The Toggle bit will stop toggling when the Program/Erase Controller has suspended the Erase Operation. Figure 8: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 15 and Figure 16 describe Toggle bit timing waveform. 41/80 Status Register M29DW641F 7.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase Controller. The Error bit is set to ’1’ when a Program, Block Erase or Chip Erase Operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read Operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 7.4 Erase timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase Controller Operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 7.5 Alternative toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase Operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase Operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read Operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within the blocks being erased. Bus Read Operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase Operation that causes the Error bit to be set the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. Figure 15 and Figure 16 describe Alternative Toggle bit timing waveform. 42/80 M29DW641F Table 13. Status Register bits(1) (2) Address Bank Address Bank Address Bank Address Any Address Erasing Block Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address 0 0 Data read as normal Toggle Toggle 1 1 1 1 0 1 Toggle No Toggle 0 0 1 – DQ7 DQ7 DQ7 DQ7 0 0 0 0 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 0 1 0 0 0 0 DQ3 – – – 1 0 0 1 Status Register Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout DQ2 – – – Toggle Toggle No Toggle Toggle No Toggle Toggle RB 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z No Toggle Toggle Hi-Z Hi-Z 1. Unspecified data bits should be ignored. 2. Figure 15 and Figure 16 describe Toggle and Alternative Toggle bits timing waveforms. Figure 7. Data polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO DQ5 = 1 YES YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI07760 43/80 Status Register Figure 8. Toggle flowchart START READ DQ6 ADDRESS = BA READ DQ5 & DQ6 ADDRESS = BA M29DW641F DQ6 = TOGGLE YES NO DQ5 =1 YES NO READ DQ6 TWICE ADDRESS = BA DQ6 = TOGGLE YES FAIL NO PASS AI08929b 1. BA = Address of Bank being Programmed or Erased. 44/80 M29DW641F Dual Operations and Multiple Bank architecture 8 Dual Operations and Multiple Bank architecture The Multiple Bank architecture of the M29DW641F gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, Read Operations are possible in another bank with zero latency. Only one bank at a time is allowed to be in program or erase mode. However, certain commands can cross bank boundaries, which means that during an operation only the banks that are not concerned with the cross bank operation are available for Dual Operations. For example, if a Block Erase command is issued to erase blocks in both Bank A and Bank B, then only Banks C or D are available for read operations while the erase is being executed. If a Read Operation is required in a bank, which is programming or erasing, the Program or Erase Operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. By using a combination of these features, Read Operations are possible at any moment. Figure 14 and Figure 15 show the Dual Operations possible in other banks and in the same bank. Note that only the commonly used commands are represented in these tables. Table 14. Dual Operations allowed in other banks Commands allowed in another bank(1) Status of bank(1) Read Array Yes Yes Yes Yes Yes Read Program Program/ Read Auto CFI Program Erase /Erase Erase Status Select Suspend Resume Register(2) Query Yes(3) No No No No Yes No No Yes Yes Yes No No Yes Yes Yes – – No Yes Yes – – No No Yes(3) No No – – Yes(4) No No Yes(5) Yes(6) Idle Programming Erasing Program Suspended Erase Suspended 1. If several banks are involved in a Program or Erase Operation, then only the banks that are not concerned with the operation are available for Dual Operations. 2. Read Status Register is not a command. The Status Register can be read during a block Program or Erase Operation. 3. Only after a program or Erase Operation in that bank. 4. Only after a Program or Erase Suspend command in that bank. 5. Only a Program Resume is allowed if the bank was previously in Program Suspend mode. 6. Only an Erase Resume is allowed if the bank was previously in Erase Suspend mode. 45/80 Dual Operations and Multiple Bank architecture Table 15. Dual Operations allowed in same bank Commands allowed in same bank Status of bank Read Array Yes No No Yes(6) Yes(6) M29DW641F Read Read Program/ Program/ Auto CFI Status Program Erase Erase Erase Select Register(1) Query Suspend Resume Yes Yes Yes No Yes(7) Yes No No Yes Yes Yes No No Yes Yes Yes – – No Yes(6) Yes – No – No Yes(2) Yes(4) Yes – – (5) Idle Programming Erasing Program Suspended Erase Suspended Yes(3) – – Yes Yes 1. Read Status Register is not a command. The Status Register can be read during a block Program or Erase Operation. 2. Only after a program or Erase Operation in that bank. 3. Only after a Program or Erase Suspend command in that bank. 4. Only a Program Suspend. 5. Only an Erase suspend. 6. Not allowed in the Block or Word that is being erased or programmed. 7. The Status Register can be read by addressing the block being erase suspended. 46/80 M29DW641F Maximum ratings 9 Maximum ratings Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 16. Symbol TBIAS TSTG VIO VCC VID VPP(3) Absolute maximum ratings Parameter Temperature Under Bias Storage Temperature Input or Output voltage Supply voltage Identification voltage Program voltage (1)(2) Min –50 –65 –0.6 –0.6 –0.6 –0.6 Max 125 150 VCC +0.6 4 13.5 13.5 Unit °C °C V V V V 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs. 47/80 DC and AC parameters M29DW641F 10 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 17: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 17. Operating and AC measurement conditions 60 Parameter Min VCC Supply voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse voltages Input and Output Timing Ref. voltages 0 to VCC VCC/2 2.7 –40 30 10 0 to VCC VCC/2 Max 3.6 85 Min 2.7 –40 30 10 Max 3.6 85 V °C pF ns V V 70 Unit Figure 9. AC measurement I/O waveform VCC VCC/2 0V AI05557 Figure 10. AC measurement load circuit VPP VCC VCC 25kΩ DEVICE UNDER TEST 25kΩ CL 0.1µF 0.1µF CL includes JIG capacitance AI05558 48/80 M29DW641F Table 18. Symbol CIN COUT DC and AC parameters Device capacitance Parameter(1) Input capacitance Output capacitance Test condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 19. Symbol ILI ILO ICC1(1) ICC2 DC characteristics Parameter Input Leakage current Output Leakage current Supply current (Read) Supply current (Standby) Test condition 0V ≤VIN ≤VCC 0V ≤VOUT ≤VCC E = VIL, G = VIH, f = 6MHz E = VCC ±0.2V, RP = VCC ±0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPPH –0.5 0.7VCC VCC = 2.7V ±10% VCC =2.7V ±10% IOL = 1.8mA IOH = –100µA VCC –0.4 11.5 1.8 12.5 2.3 11.5 Min Max ±1 ±1 10 100 20 20 0.8 VCC +0.3 12.5 15 0.45 Unit µA µA mA µA mA mA V V V mA V V V V ICC3 (1)(2) Supply current (Program/Erase) VIL VIH VPPH IPP VOL VOH VID VLKO Input Low voltage Input High voltage Voltage for Fast Program Acceleration Current for Fast Program Acceleration Output Low voltage Output High voltage Identification voltage Program/Erase Lockout Supply voltage 1. In Dual Operations the Supply current will be the sum of ICC1(read) and ICC3 (program/erase). 2. Sampled only, not 100% tested. 49/80 DC and AC parameters Figure 11. Random Read AC waveforms M29DW641F tAVAV A0-A21 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ15 tGHQX tGHQZ VALID AI05559b VALID tAXQX tEHQX tEHQZ 50/80 M29DW641F A3-A21 VALID A0-A2 VALID tAVQV VALID VALID VALID VALID VALID Figure 12. Page Read AC waveforms VALID VALID E tEHQX tEHQZ tELQV G tGLQV tAVQV1 VALID VALID VALID VALID VALID VALID VALID tGHQX tGHQZ VALID DQ0-DQ15 DC and AC parameters AI11267b 51/80 DC and AC parameters Table 20. Symbol tAVAV tAVQV tAVQV1 tELQX(1) tEHQZ(1) tELQV tGLQX(1) tGLQV tGHQZ(1) tEHQX tGHQX tAXQX M29DW641F Read AC characteristics Alt tRC tACC tPAGE tLZ tHZ tCE tOLZ tOE tDF tOH Parameter Address Valid to Next Address Valid Address Valid to Output Valid Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Test condition E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL G = VIL E = VIL E = VIL E = VIL Min Max Max Min Max Max Min Max Max Min 60 60 60 25 0 25 60 0 25 25 0 70 70 70 25 0 25 70 0 25 25 0 Unit ns ns ns ns ns ns ns ns ns ns 1. Sampled only, not 100% tested. Figure 13. Write AC waveforms, Write Enable controlled tAVAV A0-A21 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH VCC tVCHEL RB tWHRL AI05560 52/80 M29DW641F Table 21. Symbol tAVAV tAVWL tDVWH tELWL tGHWL tVCHEL tWLWH tWHDX tWHEH tWHWL tWLAX tWHGL tWHRL(1) tVCS tWP tDH tCH tWPH tAH tOEH tBUSY DC and AC parameters Write AC characteristics, Write Enable controlled Alt tWC tAS tDS tCS Parameter Address Valid to Next Address Valid Address Valid to Write Enable Low Input Valid to Write Enable High Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low VCC High to Chip Enable Low Write Enable Low to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Address Transition Write Enable High to Output Enable Low Program/Erase Valid to RB Low Min Min Min Min Min Min Min Min Min Min Min Min Max 60 60 0 45 0 0 50 45 0 0 30 45 0 30 70 70 0 45 0 0 50 45 0 0 30 45 0 30 Unit ns ns ns ns ns µs ns ns ns ns ns ns ns 1. Sampled only, not 100% tested. Figure 14. Write AC waveforms, Chip Enable controlled tAVAV A0-A21 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH VCC tVCHWL RB tEHRL AI05561 53/80 DC and AC parameters Table 22. Symbol tAVAV tAVEL tDVEH tELEH tEHDX tEHWH tEHEL tELAX tEHGL tEHRL(1) tGHEL tVCHWL tWLEL tVCS tWS M29DW641F Write AC characteristics, Chip Enable controlled Alt tWC tAS tDS tCP tDH tWH tCPH tAH tOEH tBUSY Parameter Address Valid to Next Address Valid Address Valid to Chip Enable Low Input Valid to Chip Enable High Chip Enable Low to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Chip Enable Low to Address Transition Chip Enable High to Output Enable Low Program/Erase Valid to RB Low Output Enable High Chip Enable Low VCC High to Write Enable Low Write Enable Low to Chip Enable Low Min Min Min Min Min Min Min Min Min Max Min Min Min 60 60 0 45 45 0 0 30 45 0 30 0 50 0 70 70 0 45 45 0 0 30 45 0 30 0 50 0 Unit ns ns ns ns ns ns ns ns ns ns ns µs ns 1. Sampled only, not 100% tested. Figure 15. Toggle and alternative toggle bits mechanism, Chip Enable controlled A0-A21 Address Outside the Bank Being Programmed or Erased Address in the Bank Being Programmed or Erased tAXEL E Address Outside the Bank Being Programmed or Erased G tELQV DQ2(1)/DQ6(2) Data Toggle/ Alternative Toggle Bit tELQV Toggle/ Alternative Toggle Bit Data Read Operation outside the Bank Being Programmed or Erased Read Operation in the Bank Being Programmed or Erased Read Operation Outside the Bank Being Programmed or Erased AI11302 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. 3. Refer to Table 20: Read AC characteristics for the value of tELQV. 54/80 M29DW641F DC and AC parameters Figure 16. Toggle and alternative toggle bits mechanism, Output Enable controlled A0-A21 Address Outside the Bank Being Programmed or Erased Address in the Bank Being Programmed or Erased tAXGL G Address Outside the Bank Being Programmed or Erased E tGLQV DQ2(1)/DQ6(2) Data Toggle/ Alternative Toggle Bit tGLQV Toggle/ Alternative Toggle Bit Data Read Operation outside the Bank Being Programmed or Erased Read Operation in the Bank Being Programmed or Erased Read Operation Outside the Bank Being Programmed or Erased AI11303 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. 3. Refer to Table 20: Read AC characteristics for the value of tGLQV. Table 23. Symbol tAXEL tAXGL Toggle and alternative toggle bits AC characteristics Alt Parameter Address Transition to Chip Enable Low Address Transition to Output Enable Low Min Min 60 10 10 70 10 10 Unit ns ns Figure 17. Reset/Block Temporary Unprotect AC waveforms (no Program/Erase ongoing) RB E, G tPHEL, tPHGL RP tPLPX AI11300b 55/80 DC and AC parameters M29DW641F Figure 18. Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931B Figure 19. Accelerated Program timing waveforms VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 56/80 M29DW641F Table 24. Symbol tPHEL, tPHWL, tPHGL(1) tRHEL, tRHWL tRHGL(1) tPLPX tPLYH(1) tPHPHH tVHVPP DC and AC parameters Reset/Block Temporary Unprotect AC characteristics Alt tRH tRB tRP tREADY Parameter RP High to Write Enable Low, Chip Enable Low, Output Enable Low RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width RP Low to Read mode, during Program or Erase RP Rise Time to VID VPP Rise and Fall Time Min Min Min Max Min Min 60 50 0 500 20 500 250 70 Unit ns ns ns µs ns ns 1. Sampled only, not 100% tested. 57/80 Package mechanical data M29DW641F 11 Package mechanical data Figure 20. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline 1 48 e D1 B 24 25 L1 A2 A E1 E DIE A1 C CP α L TSOP-G 1. Drawing is not to scale. Table 25. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 – 0.500 12.100 20.200 18.500 – 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 – 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.4764 0.7953 0.7283 – 0.0276 Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 α Min 58/80 M29DW641F Package mechanical data Figure 21. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.8mm pitch, package outline D FD FE SD D1 SE E E1 BALL "A1" ddd e e A A1 b A2 BGA-Z32 1. Drawing is not to scale. Table 26. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.8mm pitch, package mechanical data millimeters inches Max 1.200 0.260 0.900 0.350 6.000 4.000 5.900 – 0.450 6.100 – 0.100 8.000 5.600 0.800 1.000 1.200 0.400 0.400 7.900 – – – – – – 8.100 – – – – – – 0.3150 0.2205 0.0315 0.0394 0.0472 0.0157 0.0157 0.3110 – – – – – – 0.2362 0.1575 0.0138 0.2323 – 0.0102 0.0354 0.0177 0.2402 – 0.0039 0.3189 – – – – – – Typ Min Max 0.0472 Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE Min 59/80 Part numbering M29DW641F 12 Part numbering Table 27. Example: Device type M29 Architecture D = Dual or Multiple Bank Operating voltage W = VCC = 2.7 to 3.6V Device function 641F = 64 Mbit (x16), Multiple Bank, Page, Boot Block, 8+24+24+8 partitioning, Flash Memory Speed 60 = 60ns 70 = 70ns Package N = TSOP48, 12 x 20 mm ZE = TFBGA48 6 x 8mm, 0.8mm pitch Temperature range 1 = 0 to 70 °C 6 = –40 to 85 °C Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel 24mm Packing Ordering information scheme M29DW641F 70 N1 T Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest Numonyx sales office. The device is shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 60/80 M29DW641F Block addresses Appendix A Table 28. Bank Block addresses Block Addresses Block size (KWords) 4 4 4 4 4 4 4 4 32 32 32 32 32 Protection Group 13 14 15 16 17 18 19 20 21 22 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 070000h–077FFFh 078000h–07FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh Protection Block Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Addresses 000000h–000FFFh(1) 001000h–001FFFh(1) 002000h–002FFFh(1) 003000h–003FFFh((1) 004000h–004FFFh(1) 005000h–005FFFh(1) 006000h–006FFFh(1) 007000h–007FFFh(1) 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh Block 0 1 2 3 4 5 6 7 8 9 Bank A 10 11 12 61/80 Block addresses Table 28. Bank M29DW641F Block Addresses (continued) Block size (KWords) 32 32 Protection Group 25 26 27 28 29 30 31 32 33 34 35 36 37 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 41 42 43 44 45 46 47 48 49 50 51 52 53 54 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 170000h–177FFFh 178000h–17FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh Protection Block Group Addresses 080000h–087FFFh 088000h–08FFFFh Block 23 24 Bank B 38 39 40 62/80 M29DW641F Table 28. Bank Block addresses Block Addresses (continued) Block size (KWords) 32 32 Protection Group 57 58 59 60 61 Bank B 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Bank C 78 79 80 81 82 83 84 85 86 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 270000h–277FFFh 278000h–27FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh Protection Block Group Addresses 180000h–187FFFh 188000h–18FFFFh Block 55 56 63/80 Block addresses Table 28. Bank M29DW641F Block Addresses (continued) Block size (KWords) 32 32 Protection Group 89 90 91 92 93 94 95 96 97 98 99 100 101 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 105 106 107 108 109 110 111 112 113 114 115 116 117 118 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 370000h–377FFFh 378000h–37FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh Protection Block Group Addresses 280000h–287FFFh 288000h–28FFFFh Block 87 88 Bank C 102 103 104 64/80 M29DW641F Table 28. Bank Block addresses Block Addresses (continued) Block size (KWords) 32 32 Protection Group 121 122 123 124 125 126 127 128 Bank D 129 130 131 132 133 134 135 136 137 138 139 140 141 32 32 32 32 Protection Group 32 32 32 32 Protection Group 32 32 32 32 32 4 4 4 4 4 4 4 4 Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh Protection Block Group Addresses 380000h–387FFFh 388000h–38FFFFh Block 119 120 1. Used as the Extended Block Addresses in Extended Block mode. 65/80 Common Flash Interface (CFI) M29DW641F Appendix B Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued the addressed bank enters Read CFI Query mode and Read Operations in the same bank (A21-A19) output the CFI data. Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 show the addresses (A0-A10) used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 34: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 29. Address 10h 1Bh 27h 40h 61h Query structure overview Sub-section name CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Description Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number 1. Query data are always presented on the lowest order data outputs. Table 30. Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah CFI Query Identification String Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 33) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table Query Unique ASCII String "QRY" Description Value “Q” "R" "Y" AMD Compatible P = 40h NA NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 66/80 M29DW641F Table 31. Address Common Flash Interface (CFI) CFI Query System Interface Information Data Description VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Typical timeout per single byte/Word program = 2n µs Typical timeout for minimum size write buffer program = Typical timeout per individual block erase = Typical timeout for full Chip Erase = 2n ms Maximum timeout for byte/Word program = 2n times typical times typical times typical 2n ms 2n µs Value 1Bh 0027h 2.7V 1Ch 0036h 3.6V 1Dh 00B5h 11.5V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 00C5h 0004h 0000h 000Ah 0000h 0004h 0000h 0003h 0000h 12.5V 16µs NA 1s NA 256 µs NA 8s NA Maximum timeout for write buffer program = 2n Maximum timeout per individual block erase = 2n Maximum timeout for Chip Erase = 2n times typical 67/80 Common Flash Interface (CFI) Table 32. Address 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch M29DW641F Device Geometry Definition Data 0017h 0002h 0000h 0003h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions(1). It specifies the number of regions containing contiguous Erase Blocks of the same size. Erase Block Region 1 Information Number of Erase Blocks of identical size = 0007h+1 Erase Block Region 1 Information Block size in Region 1 = 0020h * 256 byte Erase Block Region 2 Information Number of Erase Blocks of identical size = 007Dh+1 Erase Block Region 2 Information Block size in Region 2 = 0100h * 256 byte Erase Block Region 3 information Number of Erase Blocks of identical size = 0007h + 1 Erase Block Region 3 information Block size in region 3 = 0020h * 256 bytes Erase Block Region 4 information Value 8 Mbytes x16 Async. 8 3 8 8 Kbytes 126 64 Kbytes 8 8 Kbytes 0 1. Erase Block Region 1 corresponds to addresses 000000h to 007FFFh; Erase block Region 2 corresponds to addresses 008000h to 3F7FFFh and Erase Block Region 3 corresponds to addresses 3F8000h to 3FFFFFh. 68/80 M29DW641F Table 33. Address 40h 41h 42h 43h 44h 45h Common Flash Interface (CFI) Primary Algorithm-specific extended Query table Data 0050h 0052h 0049h 0031h 0033h 0000h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of sectors in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 07 = M29DW641F Simultaneous Operations, x = number of blocks (excluding Bank A) Burst mode, 00 = not supported, 01 = supported Page mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page Word VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Top/Bottom Boot Block Flag 00h = uniform device 01h = 8 x8 Kbyte Blocks, Top and Bottom Boot with Write Protect 02h = Bottom boot device 03h = Top Boot Device 04h = Both Top and Bottom Program Suspend, 00 = not supported, 01 = supported Bank Organization, 00 = data at 4Ah is zero X = number of banks Bank A information X = number of blocks in Bank A Bank B information X = number of blocks in Bank B Primary Algorithm extended Query table unique ASCII string “PRI” Description Value "P" "R" "I" "1" "3" Yes 46h 47h 48h 49h 4Ah 4Bh 4Ch 0002h 0001h 0001h 0007h 0077h 0000h 0002h 2 1 Yes 7 119 No Yes 4Dh 00B5h 11.5V 4Eh 00C5h 12.5V 4Fh 0001h T/B 50h 57h 58h 59h 0001h 0004h 0017h 0030h Yes 4 23 48 69/80 Common Flash Interface (CFI) Table 33. Address 5Ah 5Bh M29DW641F Primary Algorithm-specific extended Query table (continued) Data 0030h 0017h Description Bank C information X = number of blocks in Bank C Bank D information X = number of blocks in Bank D Value 48 23 Table 34. Address 61h 62h 63h 64h Security Code Area Data XXXX XXXX 64 bit: unique device number XXXX XXXX Description 70/80 M29DW641F Extended Memory Block Appendix C Extended Memory Block The M29DW641F has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 128 Words. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is divided into two memory areas of 64 Words each: ● ● The first one is Factory Locked. The second one is Customer Lockable. It is up to the customer to protect it from Program Operations. Its status is indicated by bit DQ6 and DQ7. When DQ7 is set to ‘1’ and DQ6 to ‘0’, it indicates that this second memory area is Customer Lockable. When DQ7 and DQ6 are both set to ‘1’, it indicates that the second part of the Extended Block is Customer Locked and protected from Program Operations. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bits DQ6 and DQ7 are the most significant bits in the Extended Block Protection indicator and a specific procedure must be followed to read it. See Section 3.6.2: Verify Extended Block Protection indicator” in Table 5: Block Protection, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Section 6.1.10: Program command and Section 6.3.2: Exit Extended Block command, and to Table 10: Block Protection commands. C.1 Factory Locked section of the Extended Block The first section of The Extended Block is permanently protected from Program Operations and cannot be unprotected. The Random Number, Electronic Serial Number (ESN) and Security Identification Number (see Table 35: Extended Block Address and Data) are written in this section in the factory. 71/80 Extended Memory Block M29DW641F C.2 Customer Lockable section of the Extended Block The device is delivered with the second section of the Extended Block "Customer Lockable": bits DQ7 and DQ6 are set to '1' and '0' respectively. It is up to the customer to program and protect this section of the Extended Block but care must be taken because the protection is not reversible. There are three ways of protecting this section: ● Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID. Refer to Section D.2: In-system technique in Appendix D: High voltage Block Protection, and to the corresponding flowcharts Figure 24 and Figure 25 for a detailed explanation of the technique). Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique. Refer to Section D.1: Programmer technique in Appendix D: High voltage Block Protection, and to the corresponding flowcharts Figure 22 and Figure 23 for a detailed explanation of the technique). Issue a Set Extended Block Protection bit command to program the Extended Block Protection bit to ‘1’ thus preventing the second section of the Extended Block from being programmed. ● ● Bit DQ6 of the Extended Block Protection indicator is automatically set to '1' to indicate that the second section of the Extended Block is Customer Locked. Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. Table 35. Device Extended Block Address and Data Data Address(1) Factory Locked 000000h-00003Fh Random Number, Security Identification Number, ESN(2) Unavailable Customer Lockable Unavailable Determined by Customer M29DW641F 000040h-00007Fh 1. See Table 28: Block Addresses. 2. ENS = Electronic Serial Number. 72/80 M29DW641F High voltage Block Protection Appendix D High voltage Block Protection he High voltage Block Protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A, Table 28: Block Addresses for details of the Protection Groups. Once protected, Program and Erase Operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. To protect the Extended Block issue the Enter Extended Block command and then use either the Programmer or In-System technique. Once protected issue the Exit Extended Block command to return to read mode. The Extended Block protection is irreversible, once protected the protection cannot be undone. D.1 Programmer technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 22: Programmer equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 23: Programmer equipment Chip Unprotect flowchart. Figure 36: Programmer technique Bus Operations, 8-bit or 16-bit mode, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. D.2 In-system technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP (1). This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 24: In-System equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 25: In-System equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Note: RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 73/80 High voltage Block Protection Table 36. Programmer technique Bus Operations, 8-bit or 16-bit mode E G W Address Inputs A0-A21 A9 = VID, A12-A21 Block Address Others = X A6 = VIH, A9 = VID, A12 = VIH, A15 = VIH Others =X A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL, A6 = VIL, A9 = VID, A12- 21 Block Address, Others = X A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL, A6 = VIH, A9 = VID, A12-A21 Block Address Others = X M29DW641F Operation Data Inputs/Outputs DQ15-DQ0 X X Pass = xx01h Retry = xx00h. Block (Group) Protect(1) Chip Unprotect Block (Group) Protect Verify VIL VID VID VID VIL Pulse VIL Pulse VIL VIL VIH Block (Group) Unprotect Verify VIL VIL VIH Pass = xx00h Retry = xx01h. 1. Block Protection Groups are shown in Appendix D, Table 28. 74/80 M29DW641F Figure 22. Programmer equipment Group Protect flowchart START ADDRESS = GROUP ADDRESS Set-up High voltage Block Protection W = VIH n=0 G, A9 = VID, E = VIL Wait 4µs W = VIL Protect Wait 100µs W = VIH E, G = VIH, A1 = VIH A0, A2, A3, A6 = VIL E = VIL Wait 4µs Verify G = VIL Wait 60ns Read DATA DATA = 01h YES A9 = VIH E, G = VIH End PASS NO ++n = 25 YES A9 = VIH E, G = VIH FAIL NO AI07756 1. Block Protection Groups are shown in Appendix D, Table 28. 75/80 High voltage Block Protection Figure 23. Programmer equipment Chip Unprotect flowchart START PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 M29DW641F Set-up A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4µs Unprotect W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL A1, A6 = VIH E = VIL Wait 4µs INCREMENT CURRENT GROUP G = VIL Verify Wait 60ns Read DATA NO DATA = 00h YES NO ++n = 1000 YES LAST GROUP YES A9 = VIH E, G = VIH PASS NO End A9 = VIH E, G = VIH FAIL AI07757 1. Block Protection Groups are shown in Appendix D, Table 28. 76/80 M29DW641F Figure 24. In-System equipment Group Protect flowchart High voltage Block Protection START Set-up n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Wait 100µs WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH NO Protect DATA = 01h YES RP = VIH End ++n = 25 YES RP = VIH NO ISSUE READ/RESET COMMAND PASS ISSUE READ/RESET COMMAND FAIL AI07758 1. Block Protection Groups are shown in Appendix D, Table 28. 2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 77/80 High voltage Block Protection Figure 25. In-System equipment Chip Unprotect flowchart START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0 M29DW641F RP = VID WRITE 60h ANY ADDRESS WITH A0, A2, A3, A6 = VIL, A1 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0, A2, A3 = VIL, A1, A6 = VIH Wait 10ms WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1 = VIH, A6 = VIL Verify Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1 = VIH, A6 = VIL NO YES INCREMENT CURRENT GROUP DATA = 00h NO End ++n = 1000 YES RP = VIH LAST GROUP YES RP = VIH NO ISSUE READ/RESET COMMAND FAIL ISSUE READ/RESET COMMAND PASS AI07759c 1. Block Protection Groups are shown in Appendix D, Table 28. 78/80 M29DW641F Revision history Revision history Table 37. Date 02-Dec-2005 Document revision history Revision 1 First issue. DQ7 changed to DQ7 for Program, Program During Erase Suspend and Program Error in Table 13: Status Register bits. Converted to new template. Updated address values in Table 35: Extended Block Address and Data. Small text changes. NVMP address corrected in Table 11: Protection command addresses. Updated RB for Program Error and Erase Error in Table 13: Status Register bits; updated package mechanical data for TSOP48 package in Section 11. Applied Numonyx branding. Changes 10-Mar-2006 2 19-Jun-2006 3 24-Nov-2006 10-Dec-2007 4 5 79/80 M29DW641F Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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