M29W640GL90NA6F

M29W640GH M29W640GL M29W640GT M29W640GB 64 Mbit (8Mb x8 or 4Mb x16, Page) 3V supply Flash memory Feature ■ Supply Voltage – VCC = 2.7 to 3.6 V for Program/Erase/Read – VPP =12 V for Fast Program (optional) Asynchronous Random/Page Read – Page Width: 4 words – Page Access: 25 ns – Random Access: 60 ns, 70 ns, 90 ns Fast Program commands – 2 word/4 byte Program (without VPP=12 V) – 4 word/8 byte Program (with VPP=12 V) – 16 word/32 byte Write Buffer Programming time – 10 µs per byte/word typical – Chip Program time: 10 s (4-word Program) Memory organization – M29W640GH/L: 128 main blocks, 64 Kbytes each – M29W640GT/B Eight 8 Kbytes Boot blocks (top or bottom) 127 Main blocks, 64 Kbytes each Program/Erase controller – Embedded byte/word program algorithms Program/Erase Suspend and Resume – Read from any block during Program Suspend – Read and Program another block during Erase Suspend ECOPACK® packages Device summary Root Part Number M29W640GH: Uniform, last block protected by VPP/WP M29W640GL: Uniform, first block protected by VPP/WP M29W640GT: Top Boot Blocks M29W640GB: Bottom Boot Blocks FBGA ■ TSOP48 (NA) 12 x 20mm TFBGA48 (ZA) 6 x 8mm FBGA ■ TSOP56 (NB) ) 14 x 20mm(1 TBGA64 (ZF) 10 x 13mm(1) ■ 1. Packages only available upon request. ■ ■ 128 word Extended Memory block – Extra block used as security block or to store additional information Low power consumption:Standby and Automatic Standby Unlock Bypass Program command – Faster Production/Batch Programming Common Flash Interface: 64-bit Security Code VPP/WP pin for Fast Program and Write Protect Temporary Block Unprotection mode 100,000 Program/Erase cycles per block Electronic Signature – Manufacturer Code: 0020h – Device code (see Table 1) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Device code 227Eh + 220Ch + 2201h 227Eh + 220Ch + 2200h 227Eh + 2210h + 2201h 227Eh + 2210h + 2200h March 2008 Rev 5 1/90 www.numonyx.com 1 Contents M29W640GH, M29W640GL, M29W640GT, M29W640GB Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 14 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6.1 3.6.2 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 4.1.2 4.1.3 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 Contents Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 32 Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 32 4.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.1 4.3.2 4.3.3 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 33 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 5.2 5.3 5.4 5.5 5.6 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . 41 6 7 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3/90 Contents M29W640GH, M29W640GL, M29W640GT, M29W640GB 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 C.1 C.2 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 D.1 D.2 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Appendix E Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protection granularity on the M29W640GH and M29W640GL . . . . . . . . . . . . . . . . . . . . . . . 9 Protection granularity on the M29W640GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protection granularity on the M29W640GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Electronic Signature addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Write ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Reset/Block Temporary Unprotect ac Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Data polling and data toggle ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 56 TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 57 TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 58 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 59 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 M29W640GH and M29W640GL block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Top boot block addresses, M29W640GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Bottom boot block addresses, M29W640GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5/90 List of figures M29W640GH, M29W640GL, M29W640GT, M29W640GB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP56 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TBGA64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chip Enable controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chip/Block Erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Read Mode ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Page Read ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Write ac waveforms, Write Enable Controlled (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 50 Write ac waveforms, Chip Enable Controlled (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 51 Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Data Polling ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . 54 TSOP48 –48 lead Plastic Thin Small Outline, 12x20mm, top view package outline . . . . . 56 TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, top view package outline . . . . 57 TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 58 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 59 Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Write to Buffer and Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Description 1 Description The M29W640G is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M29W640GH and M29W640GL memory array is organized into 128 uniform Blocks of 64 Kbytes each (or 32 Kwords each). The M29W640GT and M29W640GB feature an asymmetric block architecture. The devices have an array of 135 blocks, divided into 8 Parameter Blocks of 8 Kbytes each (or 4 Kwords each), and 127 Main Blocks of 64 Kbytes each (or 32 Kwords each). The M29W640GT has the Parameter Blocks at the top of the memory address space while the M29W640GB locates the Parameter Blocks starting from the bottom. Blocks are protected by groups to prevent accidental Program or Erase commands from modifying the memory. ● ● Table 3, describes the protection granularity on the M29W640GH and M29W640GL. Table 4, and Table 5. describe the protection granularity on the M29W640GT and M29W640GB. The M29W640G support Asynchronous Random Read and Page Read from all blocks of the memory array. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The VPP/WP signal is used to enable faster programming of the device. Protection from Program/Erase operation can be obtained by holding VPP/WP to VSS: ● ● On the M29W640GH and M29W640GL, the last and the first block is protected, respectively. On the M29W640GT and M29W640GB, the first two and the last two boot blocks are protected. The devices feature a full set of Fast Program commands to improve the programming throughput: ● ● ● ● 2 Byte Program: it is not necessary to raise VPP/WP to 12V before issuing this command 2 Words/4 Bytes Program: it is not necessary to raise VPP/WP to 12V before issuing this command. 4 Words/8 Bytes Program: VPP/WP must be raised to 12V before issuing this command. Write to Buffer and Program, allowing to program in one shot a buffer of 16 words/32 bytes. 7/90 Description M29W640GH, M29W640GL, M29W640GT, M29W640GB The M29W640G has an extra block, the Extended Block, of 128 words in x16 mode or of 256 bytes in x8 mode that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. The M29W640GT, M29W640GB, M29W640GH and M29W640GL, are offered in TSOP48 (12x 20mm), TSOP56 (14x 20mm), TFBGA48 (6 x8mm, 0.8mm pitch), and TBGA64 (10x 13mm, 1mm pitch) packages. In order to meet environmental requirements, Numonyx offers the M29W640GH, M29W640GL, M29W640GT and M29W640GB in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The memory is delivered with all the bits erased (set to 1). Figure 1. Logic diagram VCC VPP/WP 22 A0-A21 W E G RP 15 DQ0-DQ14 DQ15A–1 BYTE RB M29W640GT M29W640GB M29W640GH M29W640GL VSS ai13694 8/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 2. Signal names(1) Name A0-A21 DQ0-DQ7 DQ8-DQ14 DQ15A–1 (or DQ15) E G W RP RB BYTE VCC VPP/WP VSS NC Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input (or Data Input/Output) Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Byte/Word Organization Select Supply Voltage Supply Voltage for Fast Program (optional) or Write Protect Ground Not Connected Internally Description Description Direction Inputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Input Input Input Input Output Input Supply voltage Supply voltage - 1. VPP/WP may be left floating since it is internally connected to an pull-up resistor to enable Program/Erase operations, Table 3. Block 0 to 3 4 to 7 -120 to 123 124 to 127 Protection granularity on the M29W640GH and M29W640GL Kbytes/Kwords 4 x 64/32 4 x 64/32 -4 x 64/32 4x 64/32 Protection Block Group Block level Protection Group -Protection Group Block level (x8) 000000h–03FFFFh(1) 040000h–07FFFFh -780000h–7BFFFFh 7C0000h–7FFFFFh (x16) 000000h–01FFFFh(1) 020000h–03FFFFh -3C0000h–3DFFFFh 3E0000h–3FFFFFh 1. Used as the Extended Block Addresses in Extended Block mode. Table 4. Block 0 to 3 4 to 7 -120 to 123 124 to 126 127 to 134 Protection granularity on the M29W640GT Kbytes/Kwords 4 x 64/32 4 x 64/32 -4 x 64/32 3 x 64/32 8x 8/4(2) Protection Block Group Protection Group Protection Group -Protection Group Protection Group Block level (x8) 000000h–03FFFFh(1) 040000h–07FFFFh -780000h–7BFFFFh 7C0000h–7EFFFFh 7F0000h–7FFFFFh (x16) 000000h–01FFFFh(1) 020000h–03FFFFh -3C0000h–3DFFFFh 3E0000h–3F7FFFh 3F8000h–3FFFFFh 1. Used as the Extended Block Addresses in Extended Block mode. 2. Boot blocks. 9/90 Description Table 5. Block 0 to 7 8 to 10 11 to 14 -127 to 130 131 to 134 1. Boot blocks. M29W640GH, M29W640GL, M29W640GT, M29W640GB Protection granularity on the M29W640GB Kbytes/Kwords 8x 8/4(1) 3 x 64/32 4 x 64/32 -4 x 64/32 4 x 64/32 Protection Block Group Block level Protection Group Protection Group -Protection Group Protection Group (x8) 000000h–00FFFFh(2) 010000h-03FFFFh 040000h-07FFFFh -780000h-7BFFFFh 7C0000h–7FFFFFh (x16) 000000h–007FFFh(2) 008000h-01FFFFh 020000h-03FFFFh -3C0000h-3DFFFFh 3E0000h–3FFFFFh 2. Used as the Extended Block Addresses in Extended Block mode. Figure 2. TSOP48 connections A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 12 13 M29W640GT M29W640GB M29W640GH M29W640GL 37 36 24 25 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI13695 10/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 3. TSOP56 connections Description NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 56 NC NC A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC VCC ai13696 14 M29W640GT M29W640GB M29W640GH M29W640GL 43 28 29 11/90 Description Figure 4. M29W640GH, M29W640GL, M29W640GT, M29W640GB TFBGA48 connections (top view through package) 1 2 3 4 5 6 A A3 A7 RB W A9 A13 B A4 A17 VPP/WP RP A8 A12 C A2 A6 A18 A21 A10 A14 D A1 A5 A20 A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 F E DQ8 DQ10 DQ12 DQ14 BYTE G G DQ9 DQ11 VCC DQ13 DQ15 A–1 H VSS DQ1 DQ3 DQ4 DQ6 VSS AI12718 12/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 5. TBGA64 connections (top view through package) 1 2 3 4 5 6 7 8 Description A NC A3 A7 RB W A9 A13 NC B NC A4 A17 VPP/WP RP A8 A12 NC C NC A2 A6 A18 A21 A10 A14 NC D NC A1 A5 A20 A19 A11 A15 VCC(1) E NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS F VCC(1) E DQ8 DQ10 DQ12 DQ14 BYTE NC G NC G DQ9 DQ11 VCC DQ13 DQ15 A–1 NC H NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC AI12719 1. Pads D8 and F1 are not connected (NC) on the M29W640GT and M29W640GB devices. 13/90 Signal descriptions M29W640GH, M29W640GL, M29W640GT, M29W640GB 2 Signal descriptions See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals connected to the device. 2.1 Address Inputs (A0-A21) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. 2.2 Data Inputs/Outputs (DQ0-DQ7) The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. 2.3 Data Inputs/Outputs (DQ8-DQ14) The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. 2.4 Data Input/Output or Address Input (DQ15A–1) When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the addressed word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.6 Output Enable (G) The Output Enable, G, controls the Bus Read operation of the memory. 14/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Signal descriptions 2.7 Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. 2.8 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Unlock Bypass Program operations. The Write Protect performs hardware protection: ● ● It protects the first and last block on M29W640GH and M29W640GL devices. It protects the first two and the last two boot blocks on M29W640GT and M29W640GB devices. The VPP/Write Protect pin may be left floating or unconnected (see Table 17: DC characteristics). When VPP/Write Protect is Low, VIL, the two outermost (M29W640GH and M29W640GL) or four outermost blocks (M29W640GT and M29W640GB) are protected. Program and Erase operations in this block are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the outermost blocks. Program and Erase operations can now modify the data in the outermost blocks unless the block is protected using Block Protection. Applying 12V to the VPP/WP pin will temporarily unprotect any block previously protected (including the outermost blocks) using a High Voltage Block Protection technique (InSystem or Programmer technique). See Table 6: Hardware Protection for details. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 18: Accelerated Program Timing waveforms. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. Table 6. VPP/WP Hardware Protection RP M29W640GT and M29W640GB VIH M29W640GH and M29W640GL M29W640GT and M29W640GB VID M29W640GH and M29W640GL Function 4 outermost parameter blocks protected from Program/Erase operations 2 outermost blocks protected from Program/Erase operations All blocks temporarily unprotected except the 4 outermost blocks All blocks temporarily unprotected except the 2 outermost blocks VIL 15/90 Signal descriptions Table 6. VPP/WP VIH or VID VPP M29W640GH, M29W640GL, M29W640GT, M29W640GB Hardware Protection RP VID VIH or VID Function All blocks temporarily unprotected All blocks temporarily unprotected 16/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Signal descriptions 2.9 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the two or four outermost blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 20: Reset/Block Temporary Unprotect ac Characteristics and Figure 17: Reset/Block Temporary Unprotect ac waveforms, for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. 2.10 Ready/Busy Output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 20: Reset/Block Temporary Unprotect ac Characteristics and Figure 17: Reset/Block Temporary Unprotect ac waveforms, for more details. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/Word Organization Select (BYTE) The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. 17/90 Signal descriptions M29W640GH, M29W640GL, M29W640GT, M29W640GB 2.12 VCC Supply Voltage VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3. 2.13 VSS Ground VSS is the reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground. 18/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Bus operations 3 Bus operations There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 13: Read Mode ac waveforms (8-bit mode), and Table 18: Read ac characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write to the Command Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 4 words and is addressed by the address inputs A0-A1. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 15: Write ac waveforms, Write Enable Controlled (8-bit mode), Figure 16: Write ac waveforms, Chip Enable Controlled (8-bit mode), and Table 19: Write ac characteristics and Table 19: Write ac characteristics, for details of the timing requirements. 3.3 Output Disable The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 17: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. 19/90 Bus operations M29W640GH, M29W640GL, M29W640GT, M29W640GB 3.5 Automatic Standby If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. 3.6 Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.6.1 Electronic Signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, with A9 set to VID. 3.6.2 Block Protect and Chip Unprotect Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A: Block addresses Table 28 and Table 29. The whole chip can be unprotected to allow the data inside the blocks to be changed. The VPP/Write Protect pin can be used to protect the two outermost blocks on the M29W640GH and M29W640GL, and the four outermost blocks on the M29W640GT and M29W640GB. When VPP/Write Protect is at VIL the outermost blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. Block Protect and Chip Unprotect operations are described in : Revision history. 20/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 7. Bus Operations, BYTE = VIL (1) Bus operations Data Inputs/Outputs Operation E G W Address Inputs DQ15A–1, A0-A21 Cell Address Command Address X X DQ14DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z 20h 7Eh M29W640GH, M29W640GL VIL VIL VIH Hi-Z M29W640GT, M29W640GB M29W640GH, M29W640GT Table 9 M29W640GL, M29W640GB M29W640GL, M29W640GT, M29W640GB VIL VIL VIH Hi-Z M29W640GH Read Block Protection Status 1. X = VIL or VIH. Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code (cycle 1) VIL VIL X VIH VIL VIL VIH VIH X VIL VIH VIL VIH X VIH 0Ch 10h 01h 00h 88h (Factory locked) 08h (Customer Lockable) 98h(Factory Locked) 18h (Customer Lockable) Read Device Code (cycle 2) Read Device Code (cycle 3) Read Extended Memory Block Verify Code VIL VIL VIH Hi-Z 01h (protected) 00h (unprotected) 21/90 Bus operations Table 8. Bus Operations, BYTE = VIH(1) E VIL VIL X VIH VIL G VIL VIH VIH X VIL W VIH VIL VIH X VIH M29W640GH, M29W640GL, M29W640GT, M29W640GB Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code (cycle 1) Address Inputs A0-A21 Cell Address Command Address X X Data Inputs/Outputs DQ15A–1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 227Eh M29W640GH, M29W640GL 220Ch 2210h 2201h 2200h 2288h (Factory locked) 2208h (Customer Lockable) 2298h(Factory Locked) 2218h (Customer Lockable) Read Device Code (cycle 2) VIL VIL VIH M29W640GT, M29W640GB M29W640GH, M29W640GT Table 9 M29W640GL, M29W640GB M29W640GL, M29W640GT, M29W640GB Read Device Code (cycle 3) Read Extended Memory Block Verify Code VIL VIL VIH M29W640GH Read Block Protection Status 1. X = VIL or VIH. VIL VIL VIH 0001h (protected) 0000h (unprotected) Table 9. Read Electronic Signature addresses(1) Code A7-A0 BYTE = VIH 00h 01h 0Eh 0Fh 03h 02h (2) A6-A0, DQ15A–1 BYTE = VIL 00h 02h 1Ch 1Eh 06h 04h(2) Manufacturer Code Device Code (cycle 1) Device Code (cycle 2) Device Code (cycle 3) Extended Memory Block Verify Code Block Protection Status 1. A9 = VID; other address bits set to VIL or VIH. 2. A12- A21 must be set to the block address. 22/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4 Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 10, or Table 11, depending on the configuration that is being used, for a summary of the commands. 4.1 4.1.1 Standard commands Read/Reset command The Read/Reset command returns the memory to its Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block Erase operation then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 4.1.2 Auto Select command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a Bus Read operation with addresses and control signals set as shown in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. The Block Protection Status of each block can be read using a Bus Read operation with addresses and control signals set as shown in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output (in 8-bit mode). The protection status of the Extended Memory block, or Extended Memory Block Verify code, can be read using a Bus Read operation with addresses and control signals set as shown in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode). 23/90 Command Interface M29W640GH, M29W640GL, M29W640GT, M29W640GB 4.1.3 Read CFI Query command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B: Common Flash Interface (CFI), Tables 30, 31, 32, 33, 34 and 35 for details on the information contained in the Common Flash Interface (CFI) memory area. 4.1.4 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 12: Program, Erase times and endurance cycles. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Refer to Figure 8: Chip/Block Erase waveforms (8-bit mode) for a description of Chip Erase ac waveforms. 24/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4.1.5 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 12: Program, Erase times and endurance cycles. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Refer to Figure 8: Chip/Block Erase waveforms (8-bit mode) for a description of Block Erase ac waveforms. 4.1.6 Erase Suspend command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. 25/90 Command Interface M29W640GH, M29W640GL, M29W640GT, M29W640GB It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. 4.1.7 Erase Resume command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. 4.1.8 Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend Latency time (see Table 12: Program, Erase times and endurance cycles for value) and updates the Status Register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from Program-Suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time Program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. 4.1.9 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 26/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4.1.10 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 12: Program, Erase times and endurance cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Refer to Figure 6: Write Enable controlled Program waveforms (8-bit mode) and Figure 7: Chip Enable controlled Program waveforms (8-bit mode) for a description of Program ac waveforms. 27/90 Command Interface M29W640GH, M29W640GL, M29W640GT, M29W640GB 4.2 Fast Program commands There are five Fast Program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel: ● ● ● Quadruple and Octuple Byte Program, available for x8 operations Double and Quadruple Word Program, available for x16 operations Write to Buffer and Program Fast Program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). 4.2.1 Double Byte Program command The Double Byte Program command is used to write a page of two adjacent bytes in parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the Double Byte Program command. 1. 2. 3. The first bus cycle sets up the Double Byte Program Command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. Note: It is not necessary to raise VPP/WP to 12V before issuing this command. 4.2.2 Quadruple Byte Program command The Quadruple Byte Program command is used to write a page of four adjacent bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command: 1. 2. 3. 4. 5. The first bus cycle sets up the Quadruple Byte Program Command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. The fourth bus cycle latches the Address and the Data of the third byte to be written. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller. Note: It is not necessary to raise VPP/WP to 12V before issuing this command. 28/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4.2.3 Octuple Byte Program command This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the eight bytes must differ only in A1, A0 and DQ15A-1. 12V must be applied to the VPP/Write Protect pin, VPP/WP, prior to issuing an Octuple Byte Program command. Care must be taken because applying a 12V voltage to the VPP/WP pin will temporarily unprotect any protected block. Nine bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. 6. 7. 8. 9. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. The fourth bus cycle latches the Address and the Data of the third byte to be written. The fifth bus cycle latches the Address and the Data of the fourth byte to be written. The sixth bus cycle latches the Address and the Data of the fifth byte to be written. The seventh bus cycle latches the Address and the Data of the sixth byte to be written. The eighth bus cycle latches the Address and the Data of the seventh byte to be written. The ninth bus cycle latches the Address and the Data of the eighth byte to be written and starts the Program/Erase Controller. 4.2.4 Double Word Program command The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. ● ● ● The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 12: Program, Erase times and endurance cycles. Note: It is not necessary to raise VPP/WP to 12V before issuing this command. 29/90 Command Interface M29W640GH, M29W640GL, M29W640GT, M29W640GB 4.2.5 Quadruple Word Program command This is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode, simultaneously. The addresses of the four words must differ only in A1 and A0. 12V must be applied to the VPP/Write Protect pin, VPP/WP, prior to issuing a Quadruple Byte Program command. Care must be taken because applying a 12V voltage to the VPP/WP pin will temporarily unprotect any protected block. Five bus write cycles are necessary to issue the command: ● ● ● ● ● The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. 4.2.6 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. When VPP is applied to the VPP/Write Protect pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately. 4.2.7 Unlock Bypass Program command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. The memory offers accelerated program operations through the VPP/Write Protect pin. When the system asserts VPP on the VPP/Write Protect pin, the memory automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The memory uses the higher voltage on the VPP/Write Protect pin, to accelerate the Unlock Bypass Program operation. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. 30/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4.2.8 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode. 4.2.9 Write to Buffer and Program command The Write to Buffer and Program command makes use of the device’s 32-byte Write Buffer to speed up programming. 16 words/32 bytes can be loaded into the Write Buffer. Each Write Buffer has the same A4-A22 addresses.The Write to Buffer and Program command dramatically reduces system programming time compared to the standard non-buffered Program command. When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held High, VIH or raised to VPPH. See Table 12 for details on typical Write to Buffer and Program times in both cases. Five successive steps are required to issue the Write to Buffer and Program command: 1. 2. 3. The Write to Buffer and Program command starts with two unlock cycles. The third Bus Write cycle sets up the Write to Buffer and Program command. The setup code can be addressed to any location within the targeted block. The fourth Bus Write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. n+1 must not exceed the size of the Write Buffer or the operation will abort. The fifth cycle loads the first address and data to be programmed. Use n Bus Write cycles to load the address and data for each word into the Write Buffer. Addresses must lie within the range from the start address+1 to the start address + n-1. Optimum performance is obtained when the start address corresponds to a 64 byte boundary. If the start address is not aligned to a 64 byte boundary, the total programming time is doubled. 4. 5. All the addresses used in the Write to Buffer and Program operation must lie within the same page. If an address is written several times during a Write to Buffer and Program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the Buffer. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write to Buffer and Program. The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a Write to Buffer and Program operation. It is possible to detect Program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. To program the content of the Write Buffer, this command must be followed by a Write to Buffer and Program Confirm command. A Write to Buffer and Program Abort and Reset command must be issued to abort the Write to Buffer and Program operation and reset the device in Read mode. 31/90 Command Interface M29W640GH, M29W640GL, M29W640GT, M29W640GB The Write Buffer Programming Sequence can be aborted in the following ways: ● ● ● ● Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a block different than the one specified during the Write-BufferLoad command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-toBuffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. See Appendix E: Flowchart, Figure 29: Write to Buffer and Program flowchart and pseudo code, for a suggested flowchart on using the Write to Buffer and Program command. 4.2.10 Write to Buffer and Program Confirm command The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and Program command and to program the n+1 words loaded in the Write Buffer by this command. 4.2.11 Write to Buffer and Program Abort and Reset command The Write to Buffer and Program Abort and Reset command is used to reset the device after a Write to Buffer and Program command has been aborted. 4.3 4.3.1 Block Protection commands Enter Extended Block command The device has an extra 256 byte block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Write operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone. 4.3.2 Exit Extended Block command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. 32/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Command Interface 4.3.3 Block Protect and Chip Unprotect commands Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A: Block addresses, Table 28: Top boot block addresses, M29W640GT and Table 29: Bottom boot block addresses, M29W640GB. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in : Revision history. 33/90 Command Interface Table 10. M29W640GH, M29W640GL, M29W640GT, M29W640GB Commands, 16-bit mode, BYTE = VIH(1) Bus Write Operations Length Command 1st 2nd 3rd Addr 4th 5th 6th Addr Data Addr Data 1 Read/Reset 3 Auto Select Program Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Chip Erase Block Erase Program/Erase Suspend Program/Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 5 3 2 2 N+5 555 555 555 555 555 555 X X 555 AA AA AA 50 56 AA A0 90 AA 2AA 2AA 2AA PA0 PA0 2AA PA X 2AA 55 55 55 PD0 PD0 55 PD 00 55 X F0 Data Addr Data Addr Data Addr Data X 555 555 PA1 PA1 555 F0 90 A0 PD1 PD1 20 PA2 PD2 PA3 PD3 PA PD BA 25 BA N(2) PA(3) PD WBL (4) PD 3 555 AA 2AA 55 555 F0 1 6 6+ 1 1 1 3 4 BA(5) 555 555 X X 55 555 555 29 AA AA B0 30 98 AA AA 2AA 2AA 55 55 555 555 88 90 X 00 2AA 2AA 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 1. X Don’t Care, PA Program Address, PD Program Data, BA any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the Write to Buffer and Program operation. 3. Each buffer has the same A4-A22 addresses. A0-A3 are used to select a word within the N+1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles. 34/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 11. Command Command Interface Commands, 8-bit mode, BYTE = VIL Length Bus Write Operations(1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data X F0 X F0 PA PD Read/Reset Auto Select Program Double Byte Program Quadruple Byte Program Octuple Byte Program 1 3 AAA AA 555 55 3 AAA AA 555 55 AAA 90 4 AAA AA 555 55 AAA A0 3 AAA 50 PA0 PD0 PA1 PD1 5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass 2 Program Unlock Bypass 2 Reset X X A0 90 PA X PD 00 BA 25 BA N(2) PA (3) Write to Buffer N+ AAA AA 555 55 and Program 5 Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Chip Erase Block Erase PD WBL (4) PD 3 AAA AA 555 55 AAA F0 1 BA (5) 29 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 X X AA B0 30 98 BA 30 Program/Erase 1 Suspend Program/Erase 1 Resume Read CFI Query Enter Extended Block Exit Extended Block 1 3 AAA AA 555 55 AAA 88 4 AAA AA 555 55 AAA 90 X 00 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. 2. 3. 4. 5. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer and Program operation. Each buffer has the same A4-A22 addresses. A0-A3 and DQ15A-1 are used to select a byte within the N+1 byte page. The 6th cycle has to be issued N time. WBL scans the byte inside the page. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles. 35/90 Command Interface Table 12. M29W640GH, M29W640GL, M29W640GT, M29W640GB Program, Erase times and endurance cycles Parameter Symbol Min Typ(1)(2) 80 (4)(5) Max(2) 400(3) Unit s s Chip Erase Block Erase (64 Kbytes) tWHWH2 0.5 50 10 10 10 10 (6) Erase Suspend Latency Time Program (byte or word) Double Byte Double Word /Quadruple Byte Program Quadruple Word / Octuple Byte Program Single Byte and Word Program(7) 32 Byte/16 Word Program using Write to Buffer and Program 32 Byte/16 Word Program using Write to Buffer and Program (VPP/WP = 12V) Chip Program (byte by byte) Chip Program (word by word) Chip Program (Double Word/Quadruple Byte Program) Chip Program (Quadruple Word/Octuple Byte Program) Program Suspend Latency Time Program/Erase Cycles (per Block) Data Retention 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. µs µs µs µs µs µs µs µs 200(3) 200 (3) (3) 200 200(3) tWHWH1 10 180 45 80 40 20 10 400(3) 200 (3) s s s s µs cycles years 100(3) 50(3) 4 100,000 20 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. This time does not include the pre-programming time. 5. Block erase polling cycle time (see Figure 19). 6. Maximum value measured at worst case conditions for both temperature and VCC. 7. Program polling cycle time (see Figure 6, Figure 7 and Figure 19). 36/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 6. Write Enable controlled Program waveforms (8-bit mode) 3rd cycle tAVAV A0-A20/ A–1 555h tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7/ DQ8-DQ15 AOh PD tWHDX tWHWH1 DQ7 DOUT tGHQZ DOUT tWHWL tWHEH PA tWLAX tELQV PA 4th cycle Data Polling tAVAV Read cycle Command Interface tGLQV tAXQX AI12779 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 5.1: Data Polling Bit (DQ7)). 4. 5. Addresses differ in x8 mode. See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings. 37/90 Command Interface Figure 7. M29W640GH, M29W640GL, M29W640GT, M29W640GB Chip Enable controlled Program waveforms (8-bit mode) 3rd cycle tAVAV A0-A20/ A–1 555h tAVEL tWLEL W tGHEL G tELEH E tDVEH DQ0-DQ7/ DQ8-DQ15 AOh PD tEHDX AI12780 4th cycle Data Polling PA tELAX tEHWH PA tEHEL1 tWHWH1 DQ7 DOUT 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status register Data Polling bit. 2. PA is address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 5.1: Data Polling Bit (DQ7)). 4. 5. Addresses differ in x8 mode. See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings. 38/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 8. Chip/Block Erase waveforms (8-bit mode) Command Interface tAVAV A0-A20/ A–1 555h tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7/ DQ8-DQ15 AAh 55h tWHDX AI12781 2AAh 555h tWLAX 555h 2AAh 555h/BA (1) tWHEH tWHWL 80h AAh 55h 10h/ 30h 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BA and 30h for a Block Erase command. 2. BA is the block address. 3. See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings. 39/90 Status Register M29W640GH, M29W640GL, M29W640GT, M29W640GB 5 Status Register Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 13: Status Register bits. 5.1 Data Polling Bit (DQ7) The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 9: Data polling flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Table 20: Reset/Block Temporary Unprotect ac Characteristics gives a description of the data polling operation and timings. 5.2 Toggle Bit (DQ6) The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 10: Data toggle flowchart, gives an example of how to use the Data Toggle Bit. Figure 20: Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) gives a description of the data polling operation and timings. 40/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Status Register 5.3 Error Bit (DQ5) The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 5.4 Erase Timer Bit (DQ3) The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. 5.5 Alternative Toggle Bit (DQ2) The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. Figure 20: Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) gives a description of the data polling operation and timings. 5.6 Write to Buffer and Program Abort Bit (DQ1) The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and Program operation aborts. Otherwise, DQ1 bit is set to ‘0’. The Write to Buffer and Program Abort and Reset command must be issued to return the device to Read mode (see Write to Buffer and Program in COMMANDS section). 41/90 Status Register Table 13. Status Register bits(1) Address Any Address Any Address Any Address Any Address Any Address Any Address Erasing Block Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address 1. Unspecified data bits should be ignored. M29W640GH, M29W640GL, M29W640GT, M29W640GB Operation Program Program During Erase Suspend Write to Buffer and Program Abort Write to Buffer and Program Program Error Chip Erase Block Erase before timeout DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 0 0 1 0 0 0 0 0 0 DQ3 – – – – – 1 0 0 1 1 – DQ2 – – – – – Toggle Toggle No Toggle Toggle No Toggle Toggle DQ1 0 – 1 0 – – – – – – – – RB 0 0 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle – – 42/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 9. Data polling flowchart START Status Register READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI90194 43/90 Status Register M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 10. Data toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ6 TWICE DQ6 = TOGGLE YES FAIL NO PASS AI90195B 44/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Maximum rating 6 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 14. Symbol TBIAS TSTG VIO VCC VID VPP(3) Absolute maximum ratings Parameter Temperature Under Bias Storage Temperature Input or Output Supply Voltage Identification Voltage Program Voltage Voltage(1)(2) Min –50 –65 –0.6 –0.6 –0.6 –0.6 Max 125 150 VCC +0.6 4 13.5 13.5 Unit °C °C V V V V 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs. 45/90 DC and ac parameters M29W640GH, M29W640GL, M29W640GT, M29W640GB 7 DC and ac parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 15. Operating and ac measurement conditions Parameter M29W640GT, M29W640GB, M29W640GH, M29W640GL Min VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VCC VCC/2 2.7 –40 30 10 Max 3.6 85 V °C pF ns V V Unit Figure 11. AC measurement I/O waveform VCC VCC/2 0V AI05557 Figure 12. AC measurement load circuit VPP VCC VCC 25kΩ DEVICE UNDER TEST 25kΩ CL 0.1µF 0.1µF CL includes JIG capacitance AI05558 46/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 16. Symbol CIN COUT DC and ac parameters Device capacitance Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 17. Symbol ILI(1) ILO ICC1 ICC2 DC characteristics Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test Condition 0V ≤VIN ≤VCC 0V ≤VOUT ≤VCC E = VIL, G = VIH, f = 6MHz E = VCC ±0.2V, RP = VCC ±0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPP Min Max ±1 ±1 10 100 20 20 –0.5 0.7VCC VCC = 2.7V ±10% VCC = 2.7V ±10% IOL = 1.8mA IOH = –100µA VCC –0.4 11.5 1.8 12.5 2.3 11.5 0.8 VCC +0.3 12.5 15 0.45 Unit µA µA mA µA mA mA V V V mA V V V V ICC3 VIL VIH VPP IPP VOL VOH VID VLKO(2) Supply Current (Program/Erase) Input Low Voltage Input High Voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low Voltage Output High Voltage Identification Voltage Program/Erase Lockout Supply Voltage 1. The maximum input leakage current is ± 5µA on the VPP/WP pin. 2. Sampled only, not 100% tested. 47/90 DC and ac parameters M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 13. Read Mode ac waveforms (8-bit mode) tAVAX A0-A20/ A–1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ AI05559 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID 1. Data are output on DQ0-DQ7. DQ8-DQ15 are Hi-Z. Figure 14. Page Read ac waveforms (8-bit mode) A2-A20 VALID ADDRESS A–1-A1 VALID tAVQV VALID VALID VALID E tELQV tEHQX tEHQZ G tGHQX tGLQV DQ0-DQ7 VALID DATA tAVQV1 VALID DATA VALID DATA tGHQZ VALID DATA AI12796b 48/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 18. Read ac characteristics DC and ac parameters Symbol Alt Parameter Test Condition M29W640GT, M29W640GB, M29W640GH, M29W640GL 60 70 70 70 30 0 70 0 30 30 30 90 90 90 30 0 90 0 30 30 30 Unit tAVAX tAVQV tAVQV1 tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ tEHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tRC tACC Address Valid to Next Address Valid Address Valid to Output Valid E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Max Min Max Min Max Max Max 60 60 25 0 60 0 25 25 25 ns ns ns ns ns ns ns ns ns tPAGE Address Valid to Output Valid (Page) tLZ tCE tOLZ tOE tHZ tDF Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z tOH tELFL tELFH tFLQZ Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 0 ns Chip Enable to BYTE Low or High BYTE Low to Output Hi-Z Max Max Max 5 25 25 5 25 30 5 25 30 ns ns ns tFHQV BYTE High to Output Valid 1. Sampled only, not 100% tested. 49/90 DC and ac parameters M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 15. Write ac waveforms, Write Enable Controlled (8-bit mode) tAVAX A0-A20/ A–1 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL1 tWHEH VCC tVCHEL RB tWHRL AI05560 50/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 16. Write ac waveforms, Chip Enable Controlled (8-bit mode) tAVAV A0-A20/ A–1 VALID tELAX tAVEL W tWLEL G tGHEL E tELEH tEHWH DC and ac parameters tEHGL1 tEHEL1 tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX VCC tVCHWL RB tEHRL AI05561 51/90 DC and ac parameters Table 19. Symbol M29W640GH, M29W640GL, M29W640GT, M29W640GB Write ac characteristics Alt Parameter M29W640GT, M29W640GB, M29W640GH, M29W640GL 60 70 70 0 0 35 35 30 0 0 0 25 0 25 0 45 0 0 0 50 90 90 0 0 35 35 30 0 0 0 25 0 25 0 45 0 0 0 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs Unit tAVAX tELWL tWLEL tWLWH tELEH tDVWH tDVEH tWHDX tEHDX tWHEH tEHWH tWHWL tWHGL1 tEHGL1 tEHEL1 tAVWL tAVEL tWLAX tELAX tGHWL tGHEL tWHRL(1) tEHRL tVCHEL tVCHWL tWC tCS tWS tWP tCP tDS tDH tCH tWH tWPH tOEH tCPH tAS tAH tGHWL tGHEL tBUSY tVCS Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Write Enable High Chip Enable Low to Chip Enable High Input Valid to Write Enable or Chip Enable High Write Enable or Chip Enable High to Input Transition Write Enable High to Chip Enable High Chip Enable High to Write Enable High Write Enable High to Write Enable Low Output Enable Hold time Chip Enable High to Chip Enable Low Address Valid to Write Enable or Chip Enable Low Write Enable or Chip Enable Low to Address Transition Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 0 35 35 30 0 0 0 25 0 25 0 45 0 0 0 50 1. Sampled only, not 100% tested. 52/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 17. Reset/Block Temporary Unprotect ac waveforms DC and ac parameters W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931B Figure 18. Accelerated Program Timing waveforms VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 Table 20. Symbol tPHWL(1) tPHEL tPHGL(1) tRHWL(1) tRHEL(1) tRHGL(1) tPLPX tPLYH tPHPHH(1)(2) tVHVPP(1) Reset/Block Temporary Unprotect ac Characteristics Alt Parameter M29W640GT, M29W640GB, M29W640GH, M29W640GL Unit tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 200 ns tRB tRP RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width Min Min Max Min Min 0 500 50 500 500 ns ns µs ns ns tREADY RP Low to Read Mode tVIDR RP Rise Time to VID VPP Rise and Fall Time 1. Sampled only, not 100% tested. 2. For Fast program operations using VPP/WP at 12V. 53/90 DC and ac parameters Figure 19. Data Polling ac waveforms tWHEH E tGLQV G tWHGL2 W M29W640GH, M29W640GL, M29W640GT, M29W640GB tELQV tEHQZ tGHQZ tWHWH1 or tWHWH2 DQ7 DATA DQ7 DQ7= Valid data Hi-Z DQ6-DQ0 DATA tWHRL DQ6-DQ0= Output flag DQ6-DQ0= Valid data Hi-Z R/B AI12782 1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed. 2. See Table 21: Data polling and data toggle ac characteristics and Table 18: Read ac characteristics for details on the timings. Figure 20. Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) A0-A20/ A–1 tGHAX E tWHGL2 W tGHGL2 G tWHDX DQ6/DQ2 Data tWHRL R/B AI12783 tAXGL tEHAX tEHEL2 tAVEL tGHGL2 tGLQV Toggle Toggle tELQV Toggle Stop toggling Output Valid 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing Chip Erase or Block Erase command is completed. 2. See Table 21: Data polling and data toggle ac characteristics and Table 18: Read ac characteristics for details on the timings. 54/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 21. Symbol DC and ac parameters Data polling and data toggle ac characteristics Alt Parameter M29W640GT, M29W640GB, M29W640GH, M29W640GL 60 70 10 10 10 20 90 10 10 10 20 ns ns ns ns Unit tAXGL tGHAX tEHAX tEHEL2 tWHGL2 tGHGL2 tASO tAHT Address setup time to Output Enable Low during Toggle bit polling Address hold time from Output Enable during Toggle bit polling Min Min Min Min 10 10 10 20 tCEPH Chip Enable High during Toggle bit polling tOEH Output Hold time during Data and Toggle bit Polling 55/90 Package mechanical M29W640GH, M29W640GL, M29W640GT, M29W640GB 8 Package mechanical Figure 21. TSOP48 –48 lead Plastic Thin Small Outline, 12x20mm, top view package outline 1 48 e D1 B 24 25 L1 A2 A E1 E DIE A1 C CP α L TSOP-G 1. Drawing is not to scale. Table 22. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 12.000 20.000 18.400 0.500 0.600 0.800 3° 0° 5° 11.900 19.800 18.300 – 0.500 12.100 20.200 18.500 – 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3° 0° 5° 0.4685 0.7795 0.7205 – 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.4764 0.7953 0.7283 – 0.0276 Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 α Min 56/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Package mechanical Figure 22. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, top view package outline 1 56 e D1 B 28 29 L1 A2 A E1 E DIE A1 C CP α L TSOP-K 1. Drawing is not to scale. Table 23. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data millimeters inches Max 1.20 0.10 1.00 0.22 0.05 0.95 0.17 0.10 0.15 1.05 0.27 0.21 0.10 14.00 20.00 18.40 0.50 0.60 3° 13.90 19.80 18.30 – 0.50 0° 14.10 20.20 18.50 – 0.70 5° 0.551 0.787 0.724 0.020 0.024 3° 0.547 0.780 0.720 – 0.020 0° 0.004 0.039 0.009 0.002 0.037 0.007 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.004 0.555 0.795 0.728 – 0.028 5° Symbol Typ A A1 A2 B C CP D1 E E1 e L α Min 57/90 Package mechanical M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 23. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline D FD FE SD D1 SE E E1 BALL "A1" ddd e e A A1 b A2 BGA-Z32 1. Drawing is not to scale. Table 24. Symbol TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data millimeters Typ Min Max 1.200 0.260 0.900 0.350 6.000 4.000 5.900 – 0.450 6.100 – 0.100 8.000 5.600 0.800 1.000 1.200 0.400 0.400 7.900 – – – – – – 8.100 – – – – – – 0.3150 0.2205 0.0315 0.0394 0.0472 0.0157 0.0157 0.3110 – – – – – – 0.2362 0.1575 0.0138 0.2323 – 0.0102 0.0354 0.0177 0.2402 – 0.0039 0.3189 – – – – – – Typ inches Min Max 0.0472 A A1 A2 b D D1 ddd E E1 e FD FE SD SE 58/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Package mechanical Figure 24. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline D FD FE D1 SD E E1 SE ddd BALL "A1" A e b A1 A2 BGA-Z23 1. Drawing is not to scale. Table 25. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data millimeters inches Max 1.200 0.300 0.800 0.350 10.000 7.000 9.900 – 0.500 10.100 – 0.100 1.000 13.000 7.000 1.500 3.000 0.500 0.500 – 12.900 – – – – – – 13.100 – – – – – 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 – 0.5079 – – – – – 0.3937 0.2756 0.200 0.350 0.0118 0.0315 0.0138 0.3898 – 0.0197 0.3976 – 0.0039 – 0.5157 – – – – – 0.0079 Typ Min Max 0.0472 0.0138 Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE Min 59/90 Part numbering M29W640GH, M29W640GL, M29W640GT, M29W640GB 9 Part numbering Table 26. Example: Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6 V Device Function 640G = 64 Mbit (x8/x16), Boot Block, Uniform or Boot Block Array Matrix T = Top Boot B = Bottom Boot H = Last Block protected by VPP/WP L = First Block protected by VPP/WP Speed 60 = 60 ns 70 = 70 ns 90 = 90 ns Package NA = TSOP48: 12 x 20mm NB = TSOP56: 14 x 20mm(1) ZA= TFBGA48: 6 x 8mm - 0.8mm pitch ZF = TBGA64: 10x13mm -1mm pitch(1) Temperature Range 6 = − to 85 °C 40 Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing 1. Packages only available upon request. Ordering information scheme M29W640GT 70 N 6 F Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 60/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Block addresses Appendix A Table 27. Block addresses M29W640GH and M29W640GL block addresses (x8) (x16) Block Kbytes/Kwords Protection Block Group 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 Protection Group Protection Group Protection Group Protection Group 000000h–00FFFFh(1) 000000h–007FFFh(1) 010000h–01FFFFh(1) 020000h–02FFFFh (1) 008000h–00FFFFh 010000h–017FFFh(1) 030000h–03FFFFh(1) 018000h–01FFFFh(1) 040000h–04FFFFh 050000h–05FFFFh 060000h–06FFFFh 070000h–07FFFFh 080000h–08FFFFh 090000h–09FFFFh 0A0000h–0AFFFFh 0B0000h–0BFFFFh 0C0000h–0CFFFFh 0D0000h–0DFFFFh 0E0000h–0EFFFFh 0F0000h–0FFFFFh 100000h–10FFFFh 110000h–11FFFFh 120000h–12FFFFh 130000h–13FFFFh 140000h–14FFFFh 150000h–15FFFFh 160000h–16FFFFh 170000h–17FFFFh 180000h–18FFFFh 190000h–19FFFFh 1A0000h–1AFFFFh 1B0000h–1BFFFFh 1C0000h–1CFFFFh 1D0000h–1DFFFFh 1E0000h–1EFFFFh 1F0000h–1FFFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 61/90 Block addresses Table 27. M29W640GH, M29W640GL, M29W640GT, M29W640GB M29W640GH and M29W640GL block addresses (continued) (x8) 200000h–20FFFFh 210000h–21FFFFh Protection Group 220000h–22FFFFh 230000h–23FFFFh 240000h–24FFFFh 250000h–25FFFFh Protection Group 260000h–26FFFFh 270000h–27FFFFh 280000h–28FFFFh 290000h–29FFFFh Protection Group 2A0000h–2AFFFFh 2B0000h–2BFFFFh 2C0000h–2CFFFFh 2D0000h–2DFFFFh Protection Group 2E0000h–2EFFFFh 2F0000h–2FFFFFh 300000h–30FFFFh 310000h–31FFFFh Protection Group 320000h–32FFFFh 330000h–33FFFFh 340000h–34FFFFh 350000h–35FFFFh Protection Group 360000h–36FFFFh 370000h–37FFFFh 380000h–38FFFFh 390000h–39FFFFh Protection Group 3A0000h–3AFFFFh 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh Protection Group 3E0000h–3EFFFFh 3F0000h–3FFFFFh (x16) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh Block Kbytes/Kwords Protection Block Group 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 62/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 27. Block addresses M29W640GH and M29W640GL block addresses (continued) (x8) 400000h–40FFFFh 410000h–41FFFFh Protection Group 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh Protection Group 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh Protection Group 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh Protection Group 4E0000h–4EFFFFh 4F0000h–4FFFFFh 500000h–50FFFFh 510000h–51FFFFh Protection Group 520000h–52FFFFh 530000h–53FFFFh 540000h–54FFFFh 550000h–55FFFFh Protection Group 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh Protection Group 5A0000h–5AFFFFh 5B0000h–5BFFFFh 5C0000h–5CFFFFh 5D0000h–5DFFFFh Protection Group 5E0000h–5EFFFFh 5F0000h–5FFFFFh (x16) 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh Block Kbytes/Kwords Protection Block Group 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 63/90 Block addresses Table 27. M29W640GH, M29W640GL, M29W640GT, M29W640GB M29W640GH and M29W640GL block addresses (continued) (x8) 600000h–60FFFFh 610000h–61FFFFh Protection Group 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh Protection Group 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh Protection Group 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh Protection Group 6E0000h–6EFFFFh 6F0000h–6FFFFFh 700000h–70FFFFh 710000h–71FFFFh Protection Group 720000h–72FFFFh 730000h–73FFFFh 740000h–74FFFFh 750000h–75FFFFh Protection Group 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh Protection Group 7A0000h–7AFFFFh 7B0000h–7BFFFFh Protection Group Protection Group Protection Group Protection Group 7C0000h–7CFFFFh 7D0000h–7DFFFFh 7E0000h–7EFFFFh 7F0000h–7FFFFFh (x16) 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh Block Kbytes/Kwords Protection Block Group 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 1. Used as the Extended Block Addresses in Extended Block mode. 64/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 28. Top boot block addresses, M29W640GT (x8) 000000h–00FFFFh(1) 010000h–01FFFFh(1) Protection Group 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 1E0000h–1EFFFFh 1F0000h–1FFFFFh 1A0000h–1AFFFFh 1B0000h–1BFFFFh 1C0000h–1CFFFFh 1D0000h–1DFFFFh 160000h–16FFFFh 170000h–17FFFFh 180000h–18FFFFh 190000h–19FFFFh 120000h–12FFFFh 130000h–13FFFFh 140000h–14FFFFh 150000h–15FFFFh 0E0000h–0EFFFFh 0F0000h–0FFFFFh 100000h–10FFFFh 110000h–11FFFFh 0A0000h–0AFFFFh 0B0000h–0BFFFFh 0C0000h–0CFFFFh 0D0000h–0DFFFFh 060000h–06FFFFh 070000h–07FFFFh 080000h–08FFFFh 090000h–09FFFFh 020000h–02FFFFh(1) 030000h–03FFFFh(1) 040000h–04FFFFh 050000h–05FFFFh Block addresses Block Kbytes/Kwords Protection Block Group 0 1 64/32 64/32 (x16) 000000h–007FFFh(1) 008000h–00FFFFh(1) 010000h–017FFFh(1) 018000h–01FFFFh(1) 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 65/90 Block addresses Table 28. M29W640GH, M29W640GL, M29W640GT, M29W640GB Top boot block addresses, M29W640GT (continued) (x8) 200000h–20FFFFh 210000h–21FFFFh Protection Group 220000h–22FFFFh 230000h–23FFFFh 240000h–24FFFFh 250000h–25FFFFh Protection Group 260000h–26FFFFh 270000h–27FFFFh 280000h–28FFFFh 290000h–29FFFFh Protection Group 2A0000h–2AFFFFh 2B0000h–2BFFFFh 2C0000h–2CFFFFh 2D0000h–2DFFFFh Protection Group 2E0000h–2EFFFFh 2F0000h–2FFFFFh 300000h–30FFFFh 310000h–31FFFFh Protection Group 320000h–32FFFFh 330000h–33FFFFh 340000h–34FFFFh 350000h–35FFFFh Protection Group 360000h–36FFFFh 370000h–37FFFFh 380000h–38FFFFh 390000h–39FFFFh Protection Group 3A0000h–3AFFFFh 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh Protection Group 3E0000h–3EFFFFh 3F0000h–3FFFFFh (x16) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh Block Kbytes/Kwords Protection Block Group 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 66/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 28. Top boot block addresses, M29W640GT (continued) (x8) 400000h–40FFFFh 410000h–41FFFFh Protection Group 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 5E0000h–5EFFFFh 5F0000h–5FFFFFh 5A0000h–5AFFFFh 5B0000h–5BFFFFh 5C0000h–5CFFFFh 5D0000h–5DFFFFh 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh 520000h–52FFFFh 530000h–53FFFFh 540000h–54FFFFh 550000h–55FFFFh 4E0000h–4EFFFFh 4F0000h–4FFFFFh 500000h–50FFFFh 510000h–51FFFFh 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh Block addresses Block Kbytes/Kwords Protection Block Group 64 65 64/32 64/32 (x16) 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 67/90 Block addresses Table 28. M29W640GH, M29W640GL, M29W640GT, M29W640GB Top boot block addresses, M29W640GT (continued) (x8) 600000h–60FFFFh 610000h–61FFFFh Protection Group 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh Protection Group 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh Protection Group 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh Protection Group 6E0000h–6EFFFFh 6F0000h–6FFFFFh 700000h–70FFFFh 710000h–71FFFFh Protection Group 720000h–72FFFFh 730000h–73FFFFh 740000h–74FFFFh 750000h–75FFFFh Protection Group 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh Protection Group 7A0000h–7AFFFFh 7B0000h–7BFFFFh 7C0000h–7CFFFFh Protection Group 7D0000h–7DFFFFh 7E0000h–7EFFFFh Protection Group Protection Group Protection Group Protection Group 7F0000h–7F1FFFh 7F2000h–7F3FFFh 7F4000h–7F5FFFh 7F6000h–7F7FFFh (x16) 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh Block Kbytes/Kwords Protection Block Group 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 68/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 28. Top boot block addresses, M29W640GT (continued) (x8) 7F8000h–7F9FFFh 7FA000h–7FBFFFh 7FC000h–7FDFFFh 7FE000h–7FFFFFh Block addresses Block Kbytes/Kwords Protection Block Group 131 132 133 134 8/4 8/4 8/4 8/4 Protection Group Protection Group Protection Group Protection Group (x16) 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh 1. Used as the Extended Block Addresses in Extended Block mode. Table 29. Bottom boot block addresses, M29W640GB Protection Block Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group (x8) (x16) Block Kbytes/Kwords 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 000000h-001FFFh(1) 000000h–000FFFh(1) 002000h-003FFFh(1) 001000h–001FFFh(1) 004000h-005FFFh(1) 002000h–002FFFh(1) 006000h-007FFFh(1) 003000h–003FFFh(1) 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh Protection Group 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 120000h-12FFFFh 130000h-13FFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 69/90 Block addresses Table 29. M29W640GH, M29W640GL, M29W640GT, M29W640GB Bottom boot block addresses, M29W640GB (continued) Protection Block Group (x8) 140000h-14FFFFh 150000h-15FFFFh Protection Group 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh Protection Group 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh Protection Group 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh Protection Group 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh Protection Group 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh Protection Group 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh Protection Group 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh Protection Group 320000h-32FFFFh 330000h-33FFFFh (x16) 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh Block Kbytes/Kwords 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 70/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 29. Bottom boot block addresses, M29W640GB (continued) Protection Block Group (x8) 340000h-34FFFFh 350000h-35FFFFh Protection Group 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 520000h-52FFFFh 530000h-53FFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh Block addresses Block Kbytes/Kwords 59 60 64/32 64/32 (x16) 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 71/90 Block addresses Table 29. M29W640GH, M29W640GL, M29W640GT, M29W640GB Bottom boot block addresses, M29W640GB (continued) Protection Block Group (x8) 540000h-54FFFFh 550000h-55FFFFh Protection Group 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh Protection Group 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh Protection Group 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh Protection Group 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh Protection Group 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh Protection Group 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh Protection Group 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh Protection Group 720000h-72FFFFh 730000h-73FFFFh (x16) 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh Block Kbytes/Kwords 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 72/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 29. Bottom boot block addresses, M29W640GB (continued) Protection Block Group (x8) 740000h-74FFFFh 750000h-75FFFFh Protection Group 125 126 127 128 129 130 131 132 133 134 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 7E0000h-7EFFFFh 7F0000h-7FFFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh Block addresses Block Kbytes/Kwords 123 124 64/32 64/32 (x16) 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh 1. Used as the Extended Block Addresses in Extended Block mode. 73/90 Common Flash Interface (CFI) M29W640GH, M29W640GL, M29W640GT, M29W640GB Appendix B Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 30, 31, 32, 33, 34, and 35, show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 35: Security code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 30. Address Sub-section Name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description Query structure overview(1) 1. Query data are always presented on the lowest order data outputs. Table 31. Address CFI query identification string(1) Data Description Value “Q” "R" "Y" AMD Compatible P = 40h x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h Query Unique ASCII String "QRY" 0059h 0002h Primary Algorithm Command Set and Control Interface ID code 0000h 16 bit ID code defining a specific algorithm 0040h Address for Primary Algorithm extended Query table (see 0000h Table 34) 0000h Alternate Vendor Command Set and Control Interface ID Code 0000h second vendor - specified algorithm supported 0000h Address for Alternate Algorithm extended Query table 0000h NA NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 74/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 32. Address Data x16 x8 VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV Description Common Flash Interface (CFI) CFI query system interface information Value 1Bh 36h 0027h 2.7V 1Ch 38h 0036h 3.6V 1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Typical timeout per single Byte/Word program = 2n µs Typical timeout for minimum size write buffer program = 2n µs Typical timeout per individual Block Erase = 2n ms Typical timeout for full Chip Erase = 2 ms Maximum timeout for Byte/Word program = 2 times typical Maximum timeout for write buffer program = 2 times typical Maximum timeout per individual Block Erase = 2n times typical Maximum timeout for Chip Erase = 2n times typical n n n 11.5V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 00C5h 0004h 0000h 000Ah 0000h 0004h 0000h 0003h 0000h 12.5V 16µs NA 1s NA 256µs NA 8s NA 75/90 Common Flash Interface (CFI) Table 33. Address Data x16 27h 28h 29h 2Ah 2Bh x8 4Eh 50h 52h 54h 56h 0017h 0002h 0000h 0005h 0000h M29W640GH, M29W640GL 2Ch 58h M29W640GT, M29W640GB 2Dh 2Eh 2Fh 30h 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 5Ah 5Ch 5Eh 60h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h M29W640GT, M29W640GB only M29W640GH, M29W640GL, M29W640GT, M29W640GB Device geometry definition(1) Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n 0001h Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same 0002h size. Value 8 Mbytes x8, x16 Async. 32 bytes 1 2 128 64Kbytes 8 8Kbyte 127 64Kbytes 007Fh Region 1 Information M29W640GH, 0000h Number of Erase Blocks of identical size = 007Fh+1 M29W640GL 0000h Region 1 Information 0001h Block size in Region 1 = 0100h * 256 byte 0007h Region 1 Information 0000h Number of Erase Blocks of identical size = 0007h+1 0020h Region 1 Information 0000h Block size in Region 1 = 0020h * 256 byte 007Eh Region 2 Information 0000h Number of Erase Blocks of identical size= 007Eh+1 0000h Region 2 Information 0001h Block size in Region 2 = 0100h * 256 byte 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Region 3 Information Number of Erase Blocks of identical size=007Fh+1 Region 3 Information Block size in Region 3 = 0000h * 256 byte Region 4 Information Number of Erase Blocks of Identical size=007Fh+1 Region 4 Information Block size in Region 4 = 0000h * 256 byte M29W640GT, M29W640GB 0 0 0 0 1. For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2 from address 008000h to 3FFFFFh. For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from address 3F8000h to 3FFFFFh. 76/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Table 34. Primary algorithm-specific extended query table Data x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h Description Common Flash Interface (CFI) Address Value "P" "R" "I" “1” "3" Yes 0052h Primary Algorithm extended Query table unique ASCII string “PRI” 0049h 0031h Major version number, ASCII 0033h Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 0000h 00h = required, 01h = not required Silicon Revision Number (bits 7 to 2) 0002h 0004h 0001h Erase Suspend 00h = not supported, 01h = Read only, 02 = Read and Write Block Protection 00h = not supported, x = number of blocks per protection group Temporary Block Unprotect 00h = not supported, 01h = supported 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 2 4 Yes 04 No No Yes 11.5V 0004h Block Protect /Unprotect 0000h Simultaneous Operations, 00h = not supported 0000h Burst Mode: 00h = not supported, 01h = supported 0001h Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8 page word VPP Supply Minimum Program/Erase voltage 00B5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Maximum Program/Erase voltage 00C5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 0002h 0003h 0004h 0005h M29W640GB M29W640GT M29W640GL M29W640GH Top/Bottom Boot Block Flag 02h = Bottom Boot device 03h = Top Boot device 04h = Uniform blocks bottom VPP/WP protect 05h = Uniform blocks top VPP/WP protect 4Eh 9Ch 12.5V 4Fh 9Eh - 50h A0h Program Suspend 0001h 00h = Not Supported 01h = Supported Support ed 77/90 Common Flash Interface (CFI) Table 35. Security code area M29W640GH, M29W640GL, M29W640GT, M29W640GB Address Data x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX Description 78/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Extended Memory Block Appendix C Extended Memory Block The M29W640G has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 128 words in x16 mode and 256 bytes in x8 mode. It is used as a security block to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See “Extended Memory Block Verify Code” in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Section 4.3.1: Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to Table 10 and Table 11: Commands, 8-bit mode, BYTE = VIL. C.1 Factory Locked Extended Block In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 36: Extended block address and data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected. C.2 Customer Lockable Extended Block A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: ● Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID (refer to Section D.2: In-System Technique and to the corresponding flowcharts, Figure 27 and Figure 28, for a detailed explanation of the technique). Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to, Section D.1: Programmer Technique and to the corresponding flowcharts, Figure 25 and Figure 26, for a detailed explanation of the technique). ● Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. 79/90 Extended Memory Block Table 36. M29W640GH, M29W640GL, M29W640GT, M29W640GB Extended block address and data Address Data x16 000000h-00003Fh 000040h-00007Fh Factory Locked Security Identification Number Unavailable Customer Lockable Determined by Customer x8 000000h-00007Fh 000080h-0000FFh 80/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Block Protection Appendix D Block Protection Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 28 and Table 29 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. D.1 Programmer Technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 25: Programmer Equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 26: Programmer Equipment Chip Unprotect flowchart. Table 37: Programmer technique bus operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. D.2 In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 27: In-System Equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 28: In-System Equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Note: RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 81/90 Block Protection Table 37. M29W640GH, M29W640GL, M29W640GT, M29W640GB Programmer technique bus operations, BYTE = VIH or VIL E G W Address Inputs A0-A21 A9 = VID, A12-A21 = Block Address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0, A2, A3 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A21 = Block Address Others = X A0, A2, A3 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A21 = Block Address Others = X Data Inputs/Outputs DQ15A–1, DQ14DQ0 X X Pass = XX01h Retry = XX00h Retry = XX01h Pass = XX00h Operation Block (Group) Protect(1) Chip Unprotect Block (Group) Protection Verify VIL VID VIL Pulse VID VID VIL Pulse VIL VIL VIH Block (Group) VIL Unprotection Verify VIL VIH 1. Block Protection Groups are shown in Appendix A, Tables 28 and 29. 82/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 25. Programmer Equipment Group Protect flowchart START Block Protection ADDRESS = GROUP ADDRESS Set-up W = VIH n=0 G, A9 = VID, E = VIL Wait 4µs Protect W = VIL Wait 100µs W = VIH E, G = VIH, A0, A2, A3 = VIL, A1 =VIH, A6 =VIL, A9 = VID, Others = X E = VIL Wait 4µs G = VIL Wait 60ns Read DATA Verify DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL AI11555 NO 1. Block Protection Groups are shown in Appendix A, Tables 28 and 29. 83/90 Block Protection M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 26. Programmer Equipment Chip Unprotect flowchart START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4µs Unprotect W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1 =VIH, A6 =VIH, A9 = VID, Others = X E = VIL Wait 4µs G = VIL Verify Wait 60ns Read DATA INCREMENT CURRENT GROUP NO DATA = 00h YES NO ++n = 1000 YES LAST GROUP YES A9 = VIH E, G = VIH PASS NO End A9 = VIH E, G = VIH FAIL AI11556b 1. Block Protection Groups are shown in Appendix A, Tables 28 and 29. 84/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 27. In-System Equipment Group Protect flowchart START Set-up n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Block Protection Protect WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Wait 100µs WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO PASS FAIL AI11563 2. Block Protection Groups are shown in Appendix A, Tables 28 and 29. 3. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 85/90 Block Protection M29W640GH, M29W640GL, M29W640GT, M29W640GB Figure 28. In-System Equipment Chip Unprotect flowchart START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0, A2, A3, A6 = VIL, A1 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0, A2, A3 = VIL, A1, A6 = VIH Wait 10ms WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH Verify Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH INCREMENT CURRENT GROUP NO DATA = 00h YES NO ++n = 1000 YES RP = VIH LAST GROUP YES RP = VIH NO End ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI11564 1. Block Protection Groups are shown in Appendix A, Tables 28 and 29. 86/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Flowchart Appendix E Flowchart Figure 29. Write to Buffer and Program flowchart and pseudo code Start Write to Buffer F0h Command, Block Address Write n(1), Block Address First Part of the Write to Buffer and Program Command Write Buffer Data, Start Address X=n X=0 NO Abort Write to Buffer NO YES YES Write to a Different Block Address Write Next Data,(3) Program Address Pair Write to Buffer and Program Aborted(2) X = X-1 Program Buffer to Flash Block Address Read Status Register (DQ1, DQ5, DQ7) at Last Loaded Address YES DQ7 = Data NO DQ1 = 1 YES NO NO DQ5 = 1 YES Check Status Register (DQ5, DQ7) at Last Loaded Address DQ7 = Data (4) YES NO FAIL OR ABORT(5) END AI12777 87/90 Flowchart 1. n+1 is the number of addresses to be programmed. M29W640GH, M29W640GL, M29W640GT, M29W640GB 2. A Write to Buffer and Program Abort and Reset must be issued to return the device in Read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However when loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page. 4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer and Program command failed. If this flowchart location is reached because DQ1=’1’, then the Write to Buffer and Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to Buffer and Program Abort and Reset command if the operation aborted. 6. See Table 10 and Table 11, for details on Write to Buffer and Program command sequence. 88/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Revision history Revision history Table 38. Date 20-Jul-2006 Document revision history Version 1 Initial release. Datasheet status updated to full datasheet; added an explanation of how to abort the Write Buffer Programming Sequence in Section 4.2.9: Write to Buffer and Program command; amended text of 4.2.11: Write to Buffer and Program Abort and Reset command. Table 13: Status Register bitsupdated. 90ns access time added. Applied Numonyx branding. Changes 21-Aug-2006 2 25-Oct-2006 22-Feb-2007 27-Mar-2008 3 4 5 89/90 M29W640GH, M29W640GL, M29W640GT, M29W640GB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 90/90