NAND08GW3B2BN6E

NAND04GW3B2B NAND08GW3B2A 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories Features ■ High density NAND Flash Memory – up to 8 Gbit memory array – Up to 256 Mbit spare area – Cost effective solution for mass storage applications NAND Interface – x8 bus width – Multiplexed Address/ Data Supply voltage – 3.0V device: VDD = 2.7 to 3.6V Page size – (2048 + 64 spare) Bytes Block size – (128K + 4K spare) Bytes Page Read/Program – Random access: 25µs (max) – Sequential access: 30ns (min) – Page program time: 200µs (typ) Copy Back Program mode – Fast page copy without external buffering Cache Program and Cache Read modes – Internal Cache Register to improve the program and read throughputs Fast Block Erase – Block erase time: 2ms (typ) Status Register Electronic Signature Chip Enable ‘don’t care’ – for simple interface with microcontroller Serial Number option ■ ■ ■ ■ TSOP48 12 x 20mm ■ ■ ■ ■ Data protection – Hardware and Software Block Locking – Hardware Program/Erase locked during Power transitions Data integrity – 100,000 Program/Erase cycles (with ECC) – 10 years Data Retention ECOPACK® package Development tools – Error Correction Code software and hardware models – Bad Blocks Management and Wear Leveling algorithms – File System OS Native reference software – Hardware simulation models ■ ■ ■ ■ ■ ■ ■ ■ December 2007 Rev 5 1/58 www.numonyx.com 1 Contents NAND04GW3B2B, NAND08GW3B2A Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Up Read Enable, Lock/Unlock Enable (PRL) . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 4.4 4.5 4.6 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 6 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.1 6.1.2 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/58 NAND04GW3B2B, NAND08GW3B2A Contents 6.2 6.3 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.1 6.3.2 Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Data Input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 6.5 6.6 6.7 6.8 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 28 P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.9 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 7.2 7.3 7.4 Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 8.2 8.3 8.4 8.5 8.6 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.1 8.6.2 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 40 3/58 Contents NAND04GW3B2B, NAND08GW3B2A 10 11 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1 11.2 Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 53 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12 13 14 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4/58 NAND04GW3B2B, NAND08GW3B2A List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Copy Back Program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AC Characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 55 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5/58 List of figures NAND04GW3B2B, NAND08GW3B2A List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Block Lock Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bad Block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43 Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Page Read operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Program/Erase Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Program/Erase Disable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . . . 54 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 55 6/58 NAND04GW3B2B, NAND08GW3B2A Description 1 Description The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The NAND04GW3B2B and NAND08GW3B2A have a density of 4 Gbits and 8 Gbits, respectively. They operate from a 3V voltage supply. The size of a Page is 2112 Bytes (2048 + 64 spare). The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. The device has hardware and software security features: ● ● A Write Protect pin is available to give a hardware protection against program and erase operations. A Block Locking scheme is available to provide user code and/or data protection. The device features an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed. The NAND04GW3B2B and NAND08GW3B2A have Cache Program and Cache Read features which improve the program and read throughputs for large files. During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read. The device has the Chip Enable Don’t Care feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. The devices have the option of a Unique Identifier (serial number), which allows each device to be uniquely identified. The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office. The device is available in a TSOP48 (12 x 20mm) package. In order to meet environmental requirements, Numonyx offers the NAND04GW3B2B and NAND08GW3B2A in ECOPACK® package. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an Numonyx trademark. 7/58 Description NAND04GW3B2B, NAND08GW3B2A For information on how to order these options refer to Table 23: Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 1: Product Description, for all the devices available in the family. Table 1. Product Description Timings Part Number Density Bus Width Page Size Block Memor Operating Random Block Package Page Sequential access Size y Array Voltage Program Erase access time (typ) (typ) time (min) (max) 64 Pages x 4096 128K Blocks +4K 64 Bytes Pages x 8192 Blocks NAND04GW3B2B 4 Gb x8 2048+ 64 Bytes 25µs 2.7 to 3.6V 25µs 30ns 200µs 2ms TSOP48 NAND08GW3B2A 8 Gb x8 30ns 200µs 2ms TSOP48 (1) 1. The NAND08GW3B2A is composed of two 4 Gbit dice. Figure 1. Logic Block Diagram Address Register/Counter AL CL W E WP R PRL X Decoder Command Interface Logic P/E/R Controller, High Voltage Generator NAND Flash Memory Array Page Buffer Command Register Cache Register Y Decoder I/O Buffers & Latches RB I/O0-I/O7 AI12465 8/58 NAND04GW3B2B, NAND08GW3B2A Figure 2. Logic Diagram VDD Description E I/O0-I/O7 R W AL CL WP PRL NAND FLASH RB VSS AI12466b Table 2. Signal Names I/O0-7 AL CL E R RB W WP PRL VDD VSS NC DU Data Input/Outputs, Address Inputs, or Command Inputs Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) Write Enable Write Protect Power-Up Read Enable, Lock/Unlock Enable Supply Voltage Ground Not Connected Internally Do Not Use 9/58 Description Figure 3. TSOP48 Connections NAND04GW3B2B, NAND08GW3B2A NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC 1 48 12 37 NAND FLASH 13 36 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC PRL VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC 24 25 AI12467b 10/58 NAND04GW3B2B, NAND08GW3B2A Memory array organization 2 Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification. The pages are split into a 2048 Byte main area and a spare area of 64 Bytes. Refer to Figure 4: Memory Array Organization. 2.1 Bad Blocks The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block Management for more details). Table 3 shows the minimum number of valid blocks. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to Section 8: Software algorithms). Table 3. Valid Blocks Density of Device 4 Gbits 8 Gbits(1) Min 4016 8032 Max 4096 8192 1. The NAND08GW3B2A is composed of two 4 Gbit dice. 11/58 Memory array organization Figure 4. Memory Array Organization NAND04GW3B2B, NAND08GW3B2A x8 bus width Block = 64 Pages Page = 2112 Bytes (2,048 + 64) a Sp re Are a Main Area Block Page 8 bits 2048 Bytes 64 Bytes Page Buffer, 2112 Bytes 2,048 Bytes 64 Bytes 8 bits AI12468 12/58 NAND04GW3B2B, NAND08GW3B2A Signal descriptions 3 Signal descriptions See Figure 2: Logic Diagram, and Table 2: Signal Names, for a brief overview of the signals connected to this device. 3.1 Inputs/Outputs (I/O0-I/O7) Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled. 3.2 Address Latch Enable (AL) The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable. 3.3 Command Latch Enable (CL) The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. 3.4 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, vIH, while the device is busy, the device remains selected and does not go into standby mode. 3.5 Read Enable (R) The Read Enable pin, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one. 3.6 Power-Up Read Enable, Lock/Unlock Enable (PRL) The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable the lock mechanism. When PRL is High, VIH, the device is in Block Lock mode. If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should be left unconnected (Not Connected) or connected to VSS. 13/58 Signal descriptions NAND04GW3B2B, NAND08GW3B2A 3.7 Write Enable (W) The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10µs (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time. 3.8 Write Protect (WP) The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down. 3.9 Ready/Busy (RB) The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Section 11.1: Ready/Busy Signal Electrical Characteristics for details on how to calculate the value of the pull-up resistor. 3.10 VDD Supply Voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below VLKO (see Table 19) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1µF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents 3.11 VSS Ground Ground, VSS, is the reference for the power supply. It must be connected to the system ground. 14/58 NAND04GW3B2B, NAND08GW3B2A Bus operations 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see Table 4: Bus Operations, for a summary. Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. 4.1 Command Input Command Input bus operations are used to give commands to the memory. The Commands are input on I/O0-I/O7. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. See Figure 21 and Table 20 for details of the timings requirements. 4.2 Address Input Address Input bus operations are used to input the memory addresses. Addresses are input on I/O0-I/O7. Five bus cycles are required to input the addresses (refer to Table 5: Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. See Figure 22 and Table 20 for details of the timings requirements. 4.3 Data Input Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 23 and Table 20 and Table 21 for details of the timings requirements. 4.4 Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the lock status, the Electronic Signature and the Unique Identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 24 and Table 21 for details of the timings requirements. 15/58 Bus operations NAND04GW3B2B, NAND08GW3B2A 4.5 Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. 4.6 Standby When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced. Table 4. Bus Operations E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(1) X VIH X VIL VIL/VDD I/O0 - I/O7 Command Address Data Input Data Output X X Bus Operation Command Input Address Input Data Input Data Output Write Protect Standby 1. WP must be VIH when issuing a program or erase command. Table 5. Bus Cycle(1) 1st 2nd 3rd 4 th Command set Address Insertion I/O7 A7 VIL A19 A27 VIL I/O6 A6 VIL A18 A26 VIL I/O5 A5 VIL A17 A25 VIL I/O4 A4 VIL A16 A24 VIL I/O3 A3 A11 A15 A23 VIL I/O2 A2 A10 A14 A22 A30(2) I/O1 A1 A9 A13 A21 A29 I/O0 A0 A8 A12 A20 A28 5th 1. Any additional address input cycles will be ignored. 2. A30 is only valid for the NAND08GW3B2A. Table 6. Address Definition Address A0 - A11 A12 - A17 A18 - A29 A18 - A30 Definition Column Address Page Address Block Address (NAND04GW3B2B) Block Address (NAND08GW3B2A) 16/58 NAND04GW3B2B, NAND08GW3B2A Command set 5 Command set All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 7. Table 7. Commands Bus Write Operations(1) Command 1st cycle 00h 05h 00h 34h 80h 85h 00h 80h 60h FFh 90h 70h 7Ah 23h 2Ah 2Ch 2nd cycle 30h E0h 31h – 10h – 35h 15h D0h – – – – 24h – – 3rd cycle – – – – – – 85h – – – – – – – – – 4th cycle – – – – – – 10h – – – – – – – – – Yes Yes Yes(2) Commands accepted during busy Read Random Data Output Cache Read Exit Cache Read Page Program (Sequential Input default) Random Data Input Copy Back Program Cache Program Block Erase Reset Read Electronic Signature Read Status Register Read Block Lock Status Blocks Unlock Blocks Lock Blocks Lock-Down 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Only during Cache Read busy. 17/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6 Device operations The following section gives the details of the device operations. 6.1 Read Memory Array At Power-Up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see Table 7: Commands. Once a Read command is issued, subsequent consecutive Read commands only require the confirm command code (30h). Once a Read command is issued two types of operations are available: Random Read and Page Read. 6.1.1 Random Read Each time the Read command is issued the first read is Random Read. 6.1.2 Page Read After the first Random Read access, the page data (2112 Bytes) are transferred to the Page Buffer in a time of tWHBH (refer to Table 21 for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during Cache Read operations. 18/58 NAND04GW3B2B, NAND08GW3B2A Figure 5. CL Device operations Read Operations E W AL R tBLBH1 RB I/O 00h Command Code Address Input 30h Command Code Data Output (sequentially) Busy ai12469 19/58 Device operations Figure 6. NAND04GW3B2B, NAND08GW3B2A Random Data Output During Sequential Data Output tBLBH1 (Read Busy time) RB Busy R I/O 00h Cmd Code Address Inputs 30h Cmd Code Data Output 05h Cmd Code Address Inputs E0h Cmd Code Data Output 5 Add cycles Row Add 1,2,3 Col Add 1,2 Spare Area 2Add cycles Col Add 1,2 Spare Area Main Area Main Area ai08658 20/58 NAND04GW3B2B, NAND08GW3B2A Device operations 6.2 Cache Read The Cache Read operation is used to improve the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page into the Cache Register. An Cache Read operation consists of three steps (see Table 7: Commands): 1. 2. 3. One bus cycle is required to setup the Cache Read command (the same as the standard Read command). Five (refer to Table 5: Address Insertion) bus cycles are then required to input the Start Address. One bus cycle is required to issue the Cache Read confirm command to start the P/E/R Controller. The Start Address must be at the beginning of a page (Column Address = 00h, see Table 6: Address Definition). This allows the data to be output uninterrupted after the latency time (tBLBH1), see Figure 7: Cache Read Operation. The Ready/Busy signal can be used to monitor the start of the operation. During the latency period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if the device is internally downloading page n+1. Once the Cache Read operation has started, the Status Register can be read using the Read Status Register command. During the operation, SR5 can be read, to find out whether the internal reading is ongoing (SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register is ready to download new data. To exit the Cache Read operation an Exit Cache Read command must be issued (see Table 7: Commands). If the Exit Cache Read command is issued while the device is internally reading page n+1, page n will still be output, but not page n+1. Figure 7. Cache Read Operation (Read Busy time) tBLBH1 tBLBH4 RB tRHRL2 R Busy I/O 00h tRHRL2 Address Inputs 31h 1st page 2nd page 3rd page last page(1) 34h Read Setup Code Cache Read Confirm Code Block N Data Output Exit Cache Read Code ai8661c 1. For NAND08GW3B2A, A30 can not be changed during the Cache Read Operation. 21/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6.3 Page Program The Page Program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however the device does support Random Input within a page. It is recommended to address pages sequentially within a given block. The memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 2112) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is four. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. 6.3.1 Sequential Input To input data sequentially the addresses must be sequential and remain in one block. For Sequential Input each Page Program operation consists of five steps (see Figure 8: Page Program Operation): 1. 2. 3. 4. 5. One bus cycle is required to setup the Page Program (Sequential Input) command (see Table 7: Commands). Five bus cycles are then required to input the program address (refer to Table 5: Address Insertion). The data is then loaded into the Data Registers. One bus cycle is required to issue the Page Program confirm command to start the P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3. the P/E/R Controller then programs the data into the array. 6.3.2 Random Data Input in page During a Sequential Input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required to issue the command: 1. 2. One bus cycle is required to setup the Random Data Input command (see Table 7: Commands) Two bus cycles are then required to input the new column address (refer to Table 5: Address Insertion) Random Data Input can be repeated as often as required in any given page. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface. 22/58 NAND04GW3B2B, NAND08GW3B2A Figure 8. Page Program Operation (Program Busy time) Device operations tBLBH2 RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0 Read Status Register ai08659 Figure 9. Random Data Input During Sequential Data Input (Program Busy time) tBLBH2 RB Busy I/O 80h Cmd Code Address Inputs Data Intput 85h Cmd Code Address Inputs 2 Add cycles Col Add 1,2 Data Input 10h Confirm Code 70h SR0 Read Status Register 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area Spare Area Main Area Spare Area ai08664 23/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6.4 Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external ECC cannot be used with the Copy Back Program operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of Copy Back Program operations on the same data and or to improve the performance of the ECC. The Copy Back Program operation requires four steps: 1. The first step reads the source page. The operation copies all 2112 Bytes from the page into the Data Buffer. It requires: – – – 2. One bus write cycle to setup the command 5 bus write cycles to input the source page address One bus write cycle to issue the confirm command code When the device returns to the ready state (Ready/Busy High), the next bus write cycle of the command is given with the 5 bus cycles to input the target page address. See Table 8 for the addresses that must be the same for the source and target page. Then the confirm command is issued to start the P/E/R Controller. 3. To see the Data Input cycle for modifying the source page and an example of the Copy Back Program operation refer to Figure 10: Copy Back Program. A data input cycle to modify a portion or a multiple distant portion of the source page, is shown in Figure 11: Page Copy Back Program with Random Data Input. Table 8. Copy Back Program addresses Density 4 Gbits 8 Gbits Source and target page addresses no constraint same A30 Figure 10. Copy Back Program I/O 00h Read Code Source Add Inputs 35h 85h Copy Back Code Target Add Inputs 10h 70h SR0 Read Status Register tBLBH2 (Program Busy time) tBLBH1 (Read Busy time) RB Busy Busy ai09858b 1. Copy back program is only permitted between odd address pages or even address pages. 24/58 NAND04GW3B2B, NAND08GW3B2A Figure 11. Page Copy Back Program with Random Data Input Device operations I/O 00h Read Code Source Add Inputs 35h 85h Copy Back Code Target Add Inputs Data 85h 2 Cycle Add Inputs Data 10h 70h SR0 Unlimited number of repetitions tBLBH1 (Read Busy time) tBLBH2 (Program Busy time) RB Busy Busy ai11001 25/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6.5 Cache Program The Cache Program operation is used to improve the programming throughput by programming data using the Cache Register. The Cache Program operation can only be used within one block. The Cache Register allows new data to be input while the previous data that was transferred to the Page Buffer is programmed into the memory array. The following sequence is required to perform a Cache Program operation (refer to Figure 12): 1. First of all the program setup command is issued (one bus cycle to issue the program setup command then five bus write cycles to input the address), the data is then input (up to 2112 Bytes) and loaded into the Cache Register. One bus cycle is required to issue the confirm command to start the P/E/R Controller. The P/E/R Controller then transfers the data to the Page Buffer. During this the device is busy for a time of tBLBH5. Once the data is loaded into the Page Buffer the P/E/R Controller programs the data into the memory array. As soon as the Cache Registers are empty (after tBLBH5) a new Cache program command can be issued, while the internal programming is still executing. 2. 3. 4. Once the program operation has started the Status Register can be read using the Read Status Register command. During Cache Program operations SR5 can be read to find out whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while SR6 indicates whether the Cache Register is ready to accept new data. If any errors have been detected on the previous page (Page N-1), the Cache Program Error Bit SR1 will be set to ‘1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1’. When the next page (Page N) of data is input with the Cache Program command, tBLBH5 is affected by the pending internal programming. The data will only be transferred from the Cache Register to the Page Buffer when the pending program cycle is finished and the Page Buffer is available. If the system monitors the progress of the operation using only the Ready/Busy signal, the last page of data must be programmed with the Page Program confirm command (10h). If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must be polled to find out if the last programming is finished before starting any other operations. Figure 12. Cache Program Operation (Cache Busy time) tBLBH5 tBLBH5 tCACHEPG RB Busy I/O 80h Busy 80h Busy 80h Address Inputs Data Inputs 15h Address Inputs Data Inputs 15h Address Inputs Data Inputs 10h 70h SR0 Page Program Code First Page Cache Program Code Page Program Code Cache Program Confirm Code Second Page Page Read Status Program Register Confirm Code Last Page(3) ai08672 (can be repeated up to 63 times) 1. Up to 64 pages can be programmed in one Cache Program operation. 2. tCACHEPG is the program time for the last page + the program time for the (last −1)th page −(Program command cycle time + Last page data loading time). 3. For NAND08GW3B2A, A30 can not be changed during the Cache Program operation. 26/58 NAND04GW3B2B, NAND08GW3B2A Device operations 6.6 Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 13: Block Erase Operation): 1. 2. 3. One bus cycle is required to setup the Block Erase command. Only addresses A18A29 are used, the other address inputs are ignored. Three bus cycles are then required to load the address of the block to be erased. Refer to Table 6: Address Definition for the block addresses of each device. One bus cycle is required to issue the Block Erase confirm command to start the P/E/R Controller. The operation is initiated on the rising edge of write Enable, W, after the confirm command is issued. The P/E/R Controller handles Block Erase and implements the verify process. During the Block Erase operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit SR0 is ‘0’, otherwise it is set to ‘1’. Figure 13. Block Erase Operation tBLBH3 (Erase Busy time) RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0 Read Status Register ai07593 6.7 Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued, refer to Table 21 for the values. 27/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6.8 Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new Read command must be issued to continue with a Page Read operation. The Status Register bits are summarized in Table 9: Status Register Bits,. Refer to Table 9: Status Register Bits in conjunction with the following text descriptions. 6.8.1 Write Protection Bit (SR7) The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to ‘1’ the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed. 6.8.2 P/E/R Controller and Cache Ready/Busy Bit (SR6) Status Register bit SR6 has two different functions depending on the current operation. During Cache operations SR6 acts as a Cache Ready/Busy bit, which indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to accept new data. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready). 6.8.3 P/E/R Controller Bit (SR5) The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready). 6.8.4 Cache Program Error Bit (SR1) The Cache Program Error bit can be used to identify if the previous page (page N-1) has been successfully programmed or not in a Cache Program operation. SR1 is set to ’1’ when 28/58 NAND04GW3B2B, NAND08GW3B2A Device operations the Cache Program operation has failed to program the previous page (page N-1) correctly. If SR1 is set to ‘0’ the operation has completed successfully. The Cache Program Error bit is only valid during Cache Program operations, during other operations it is Don’t Care. 6.8.5 Error Bit (SR0) The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error Bit SR0, in a Cache Program operation, indicates a failure on Page N. 6.8.6 Table 9. Bit SR7 SR4, SR3 and SR2 are Reserved Status Register Bits Name Write Protection '0' Program/ Erase/ Read Controller '1' '0' '1' Cache Ready/Busy '0' Cache Register busy (Cache only) P/E/R C inactive, device ready P/E/R C active, device busy Program/ Erase/ Read Controller(1) Reserved Cache Program Error(2) '1' '0' Don’t Care '1' '0' ‘1’ Generic Error ‘0’ No Error – operation successful Page N failed in Cache Program operation Page N programmed successfully Page N-1 failed in Cache Program operation Page N-1 programmed successfully Error – operation failed Protected P/E/R C inactive, device ready P/E/R C active, device busy Cache Register ready (Cache only) Logic Level '1' Not Protected Definition SR6 SR5 SR4, SR3, SR2 SR1 SR0 ‘1’ Cache Program Error ‘0’ 1. Only valid for Cache operations, for other operations it is same as SR6. 2. Only valid for Cache Program operations, for other operations it is Don’t Care. 29/58 Device operations NAND04GW3B2B, NAND08GW3B2A 6.9 Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes three steps are required: 1. 2. 3. One Bus Write cycle to issue the Read Electronic Signature command (90h) One Bus Write cycle to input the address (00h) Four Bus Read Cycles to sequentially output the data (as shown in Table 10: Electronic Signature). Table 10. Electronic Signature Byte 1 Manufacturer Code 20h 20h Byte 2 Device code DCh D3h Byte 3 (see Table 11) 80h 81h Byte 4 (see Table 12) 95h 95h Root Part Number NAND04GW3B2B NAND08GW3B2A Table 11. I/O Electronic Signature Byte 3 Definition Value 00 01 10 11 00 01 10 11 00 01 10 11 0 1 0 1 Description 1 2 4 8 2-level cell 4-level cell 8-level cell 16-level cell 1 2 4 8 Not supported Supported Not supported Supported I/O1-I/O0 Internal Chip number I/O3-I/O2 Cell Type I/O5-I/O4 Number of simultaneously programmed pages I/O6 I/O7 Interleaved Programming between multiple devices Cache Program 30/58 NAND04GW3B2B, NAND08GW3B2A Table 12. I/O Device operations Electronic Signature Byte 4 Definition Value 00 01 10 11 0 1 00 10 01 11 00 01 10 11 0 1 Description 1 KBytes 2 KBytes Reserved Reserved 8 16 50ns 30ns Reserved Reserved 64 KBytes 128 KBytes 256 KBytes Reserved x8 x16 I/O1-I/O0 Page Size (Without Spare Area) Spare Area Size (Byte / 512 Byte) I/O2 I/O7, I/O3 Minimum sequential access time I/O5-I/O4 Block Size (without Spare Area) I/O6 Organization 31/58 Data Protection NAND04GW3B2B, NAND08GW3B2A 7 Data Protection The device has both hardware and software features to protect against program and erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations. It is recommended to keep WP at VIL during power-up and powerdown. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever VDD is below VLKO (see Table 19: DC Characteristics). The device features a Block Lock mode, which is enabled by setting the Power-Up Read Enable, Lock/Unlock Enable, PRL, signal to High. The Block Lock mode has two levels of software protection. ● ● Blocks Lock/Unlock Blocks Lock-down Refer to Figure 16: Block Protection State Diagram for an overview of the protection mechanism. 7.1 Blocks Lock All the blocks are locked simultaneously by issuing a Blocks Lock command (see Table 7: Commands). All blocks are locked after power-up and when the Write Protect signal is Low. Once all the blocks are locked, one sequence of consecutive blocks can be unlocked by using the Blocks Unlock command. Refer to Figure 21: Command Latch AC Waveforms for details on how to issue the command. 7.2 Blocks Unlock A sequence of consecutive locked blocks can be unlocked, to allow program or erase operations, by issuing an Blocks Unlock command (see Table 7: Commands). The Blocks Unlock command consists of four steps: ● ● ● ● One bus cycle to setup the command. Three bus cycles to give the Start Block Address (refer to Table 6: Address Definition, and Figure 14: Blocks Unlock Operation). One bus cycle to confirm the command. Three bus cycles to give the End Block Address (refer to Table 6: Address Definition, and Figure 14: Blocks Unlock Operation). The Start Block Address must be nearer the logical LSB (Least Significant Bit) than End Block Address. 32/58 NAND04GW3B2B, NAND08GW3B2A Data Protection If the Start Block Address is the same as the End Block Address, only one block is unlocked. Only one consecutive area of blocks can be unlocked at any one time. It is not possible to unlock multiple areas. Figure 14. Blocks Unlock Operation WP I/O 23h Blocks Unlock Command Add1 Add2 Add3 24h Add1 Add2 Add3 Start Block Address, 3 cycles End Block Address, 3 cycles ai08670 7.3 Blocks Lock-Down The Lock-Down feature provides an additional level of protection. A Locked-down block cannot be unlocked by a software command. Locked-Down blocks can only be unlocked by setting the Write Protect signal to Low for a minimum of 100ns. Only locked blocks can be locked-down. The command has no affect on unlocked blocks. Refer to Figure 21: Command Latch AC Waveforms for details on how to issue the command. 7.4 Block Lock Status In Block Lock mode (PRL High) the Block Lock Status of each block can be checked by issuing a Read Block Lock Status command (see Table 7: Commands). The command consists of: ● ● One bus cycle to give the command code Three bus cycles to give the block address After this, a read cycle will then output the Block Lock Status on the I/O pins on the falling edge of Chip Enable or Read Enable, whichever occurs last. Chip Enable or Read Enable do not need to be toggled to update the status. The Read Block Lock Status command will not be accepted while the device is busy (RB Low). The device will remain in Read Block Lock Status mode until another command is issued. 33/58 Data Protection Figure 15. Read Block Lock Status Operation NAND04GW3B2B, NAND08GW3B2A W tWHRL R I/O 7Ah Read Block Lock Status Command Add1 Add2 Add3 Dout Block Lock Status Block Address, 3 cycles ai08669 Table 13. Block Lock Status(1) I/O7-I/O3 X X X X I/O2 0 1 0 1 I/O1 1 1 0 0 I/O0 0 0 1 1 Status Locked Unlocked Locked-Down Unlocked in LockedDown Area 1. X = Don’t Care. 34/58 NAND04GW3B2B, NAND08GW3B2A Figure 16. Block Protection State Diagram Data Protection Power-Up Block Unlock Command (start + end block address) Locked Blocks Lock-Down Command Blocks Lock Command WP VIL >100ns Unlocked in Locked Area WP VIL >100ns WP VIL >100ns Locked-Down Blocks Lock-Down Command Unlocked in Locked-Down Area AI08663c 1. PRL must be High for the software commands to be accepted. 35/58 Software algorithms NAND04GW3B2B, NAND08GW3B2A 8 Software algorithms This section gives information on the software algorithms that Numonyx recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunnelling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 15: Program, Erase Times and Program Erase Endurance Cycles for value) and it is recommended to implement Garbage Collection, a Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application Numonyx can provide a File System OS Native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. 8.1 Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block, where the 1st and 6th Bytes, or 1st Word, in the spare area of the 1st page, does not contain FFh, is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 17: Bad Block management flowchart. 8.2 NAND Flash memory failure modes Over the lifetime of the device additional Bad Blocks may develop. To implement a highly reliable system, all the possible failure modes must be considered: ● Program/Erase failure: in this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a Page Program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See Section 6.4: Copy Back Program for more details. Read failure: in this case, ECC correction must be implemented. To efficiently use the memory space, it is recommended to recover single-bit error in read by ECC, without replacing the whole block. ● Refer to Table 14 for the procedure to follow if an error occurs during an operation. 36/58 NAND04GW3B2B, NAND08GW3B2A Table 14. Block failure Operation Erase Program Read Procedure Software algorithms Block Replacement Block Replacement or ECC ECC Figure 17. Bad Block management flowchart START Block Address = Block 0 Increment Block Address Update Bad Block table Data = FFh? YES NO Last block? YES NO END AI07588C 37/58 Software algorithms NAND04GW3B2B, NAND08GW3B2A 8.3 Garbage Collection When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm. In a Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 18: Garbage Collection). Figure 18. Garbage Collection Old Area New Area (After GC) Valid Page Invalid Page Free Page (Erased) AI07599B 8.4 Wear-leveling algorithm For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm to monitor and spread the number of write cycles per block. In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: ● ● First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles. Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. The Second Level Wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. 8.5 Error Correction Code An Error Correction Code (ECC) can be implemented in the NAND Flash memories to identify and correct errors in the data. For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). 38/58 NAND04GW3B2B, NAND08GW3B2A Software algorithms An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details. Figure 19. Error Detection New ECC generated during read XOR previous ECC with new ECC All results = zero? YES 22 bit data = 0 NO >1 bit = zero? YES 11 bit data = 1 NO 1 bit data = 1 No Error Correctable Error ECC Error ai08332 8.6 8.6.1 Hardware simulation models Behavioral simulation models Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. 8.6.2 IBIS simulations models IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS. 39/58 Program and Erase times and endurance cycles NAND04GW3B2B, NAND08GW3B2A 9 Program and Erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 15. Table 15. Program, Erase Times and Program Erase Endurance Cycles NAND Flash Parameters Min Page Program Time Block Erase Time Program/Erase Cycles per block (with ECC) Data Retention 100,000 10 Typ 200 2 Max 700 3 µs ms cycles years Unit 40/58 NAND04GW3B2B, NAND08GW3B2A Maximum rating 10 Maximum rating Stressing the device above the ratings listed in Table 16: Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 16. Symbol TBIAS TSTG VIO(1) VDD Absolute Maximum Ratings Value Parameter Min Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage – 50 – 65 – 0.6 – 0.6 Max 125 150 4.6 4.6 °C °C V V Unit 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins. 41/58 DC and AC parameters NAND04GW3B2B, NAND08GW3B2A 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 17. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 17. Operating and AC Measurement Conditions NAND Flash Parameter Min Supply Voltage (VDD) Grade 1 Ambient Temperature (TA) Load Capacitance (CL) (1 TTL GATE and CL) Input Pulses Voltages Input and Output Timing Ref. Voltages Output Circuit Resistor Rref Input Rise and Fall Times Grade 6 2.7 0 –40 50 0 VDD/2 8.35 5 VDD Max 3.6 70 85 V °C °C pF V V kΩ ns Units Table 18. Symbol CIN CI/O Capacitance(1) Parameter Input Capacitance Input/Output Capacitance(2) Test Condition VIN = 0V VIL = 0V Typ Max 10 10 Unit pF pF 1. TA = 25°C, f = 1MHz. CIN and CI/O are not 100% tested. 2. Input/output capacitances double in stacked devices. 42/58 NAND04GW3B2B, NAND08GW3B2A DC and AC parameters Figure 20. Equivalent Testing Circuit for AC Characteristics Measurement VDD 2Rref NAND Flash CL 2Rref GND GND Ai11085 Table 19. Symbol IDD1 IDD2 IDD3 IDD4 DC Characteristics Parameter Sequential Read Program Erase Standby current (TTL)(1) Standby Current (CMOS)(1) Input Leakage Current(1) Output Leakage Current(1) Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) VDD Supply Voltage (Erase and Program lockout) Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VIH, WP=0/VDD E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT= 0 to VDDmax IOH = -400µA IOL = 2.1mA VOL = 0.4V 0.8VDD -0.3 2.4 8 10 10 1.7 Min Typ 15 15 15 Max 30 30 30 1 50 ±10 ±10 VDD+0.3 0.2VDD 0.4 Unit mA mA mA mA µA µA µA V V V V mA V Operating Current IDD5 ILI ILO VIH VIL VOH VOL IOL (RB) VLKO 1. leakage current and standby current double in stacked devices. 43/58 DC and AC parameters Table 20. Symbol tALLWH tALHWH tCLHWH tCLLWH tDVWH tELWH tWHALH tWHALL tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL NAND04GW3B2B, NAND08GW3B2A AC Characteristics for Command, Address, Data Input Alt. Symbol tALS Parameter Address Latch Low to Write Enable high AL Setup time Address Latch High to Write Enable high Command Latch High to Write Enable high tCLS tDS tCS tALH CL Setup time Min Command Latch Low to Write Enable high Data Valid to Write Enable High Chip Enable Low to Write Enable high Write Enable High to Address Latch High AL Hold time Write Enable High to Address Latch Low Write Enable High to Command Latch High tCLH tDH tCH tWH tWP tWC CL hold time Write Enable High to Command Latch Low Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data Hold time E Hold time W High Hold time W Pulse Width Write Cycle time Min Min Min Min Min 5 5 10 15 30 ns ns ns ns ns Min 5 ns Min 5 ns Data Setup time E Setup time Min Min 15 25 ns ns 15 ns Min 15 ns NAND04GW3B2B, Unit NAND08GW3B2A Table 21. Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 AC Characteristics for operations(1) Alt. Symbol tAR tRR Address Latch Low to Read Enable Low Parameter Read Electronic Signature Read cycle Min Min Min Max Max Max Max Max Max Max Typ NAND04GW3B2B, Unit NAND08GW3B2A 15 15 20 25 700 3 5 5 10 500 3 700 ns ns ns µs µs ms µs µs µs µs µs µs Ready/Busy High to Read Enable Low Read Busy time tPROG tBERS Ready/Busy Low to Ready/Busy High Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read Reset Busy time, during program Reset Busy time, during erase tBLBH4 tRST tBLBH5 tCBSY Cache Busy time Max 44/58 NAND04GW3B2B, NAND08GW3B2A Table 21. tCLLRL tDZRL tEHQZ tRHQZ tELQV tRHRL1 tEHQX tRHQX tRLRH tRLRL tRLQV tWHBH tWHBL tWHRL tRHRL2 tWHWH tVHWH tVLWH DC and AC parameters AC Characteristics for operations(1) (continued) tCLR tIR tCHZ tRHZ tCEA tREH tOH tRP tRC tREA tR tWB tWHR tCRRH tADL(3) tWW(4) Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Output Hi-Z Read Enable High to Output Hi-z Chip Enable Low to Output Valid Read Enable High to Read Enable Low Read Enable High Hold time Min Min Max Max Max Min 15 0 50 50 30 10 ns ns ns ns ns ns Chip Enable high to Output Hold Min Read Enable high to Output Hold Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time(2) Read Busy time Max 25 ns Min Min 15 30 ns ns 15 ns Max Max Min Min Min Min 25 100 60 100 100 100 µs ns ns ns ns ns Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Read Enable High hold time during Cache Read operation Last Address latched to Data Loading Time during Program operations Write Protection time 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figure 33, Figure 34 and Figure 35. 2. ES = Electronic Signature. 3. tADL is the time from W rising edge during the final address cycle to W rising edge during the first data cycle. 4. During a Program/Erase Enable Operation, tWW is the delay from WP high to W High. During a Program/Erase Disable Operation, tWW is the delay from WP Low to W High. Figure 21. Command Latch AC Waveforms CL tCLHWH (CL Setup time) tWHCLL (CL Hold time) tELWH H(E Setup time) tWHEH (E Hold time) E tWLWH W tALLWH (ALSetup time) tWHALH (AL Hold time) AL tDVWH (Data Setup time) 45/58 tWHDX (Data Hold time) I/O Command ai12470b DC and AC parameters Figure 22. Address Latch AC Waveforms NAND04GW3B2B, NAND08GW3B2A (CL Setup time) tCLLWH CL tELWH (E Setup time) tWLWL tWLWL tWLWL tWLWL E tWLWH W tWHWL tALHWH (AL Setup time) tWLWH tWLWH tWLWH tWLWH tWHWL tWHWL tWHWL tWHALL (AL Hold time) tWHALL tWHALL tWHALL AL tDVWH tDVWH tWHDX (Data Hold time) (Data Setup time) tDVWH tWHDX Adrress cycle 2 Adrress cycle 3 tDVWH tWHDX Adrress cycle 4 tDVWH tWHDX Adrress cycle 5 ai12471 tWHDX I/O Adrress cycle 1 46/58 NAND04GW3B2B, NAND08GW3B2A Figure 23. Data Input Latch AC Waveforms DC and AC parameters tWHCLH (CL Hold time) CL tWHEH (E Hold time) E (ALSetup time) tALLWH tWLWL AL tWLWH W tDVWH (Data Setup time) tWLWH tWLWH tDVWH tWHDX (Data Hold time) tDVWH tWHDX tWHDX I/O Data In 0 Data In 1 Data In Last ai12472 1. Data In Last is 2112. Figure 24. Sequential Data Output after Read AC waveforms tRLRL1 (Read Cycle time) E tRHRL1 (R High Holdtime) tEHQZ tEHQX R tRHQZ tRLQV (R Accesstime) tRHQZ tRLQV tRLQV I/O tBHRL RB Data Out Data Out Data Out ai08031c 1. CL = Low, AL = Low, W = High. 47/58 DC and AC parameters Figure 25. Read Status Register AC Waveform tCLLRL CL tWHCLL tCLHWH E tELWH tWLWH W tWHRL R tDZRL tDVWH (Data Setup time) NAND04GW3B2B, NAND08GW3B2A tWHEH tELQV tEHQZ tWHDX (Data Hold time) tRLQV tRHQZ I/O 70h Status Register Output ai12473 Figure 26. Read Electronic Signature AC Waveform CL E W AL tALLRL1 R (Read ES Access time) tRLQV I/O 90h Read Electronic Signature Command 00h 1st Cycle Address Byte1 Man. code Byte2 Device code Byte3 Byte4 see Note.1 ai08667 1. Refer to Table 10 for the values of the Manufacturer and Device Codes, and to Table 11 and Table 12 for the information contained in Byte 3 and Byte 4. 48/58 NAND04GW3B2B, NAND08GW3B2A Figure 27. Page Read operation AC Waveform DC and AC parameters CL E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL (Read Cycle time) tEHQZ tRHQZ R tRLRH tBLBH1 RB tEHQX tRHQX I/O 00h Add.N cycle 1 Add.N cycle 2 Add.N cycle 3 Add.N cycle 4 Add.N cycle 5 30h Data N Data N+1 Data N+2 Data Last Command Code Address N Input Busy Data Output from Address N to Last Byte or Word in Page ai12474c 49/58 DC and AC parameters Figure 28. Page Program AC waveform NAND04GW3B2B, NAND08GW3B2A CL E tWLWL (Write Cycle time) tWLWL tWLWL W tWHWH tWHBL tBLBH2 (Program Busy time) AL R I/O 80h Add.N cycle 1 Add.N cycle 2 Add.N Add.N Add.N cycle 3 cycle 4 cycle 5 N Last 10h 70h SR0 RB Page Program Setup Code Confirm Code Address Input Data Input Page Program Read Status Register ai12475b 50/58 NAND04GW3B2B, NAND08GW3B2A Figure 29. Block Erase AC Waveform DC and AC parameters CL E tWLWL (Write Cycle time) W tWHBL AL (Erase Busy time) tBLBH3 R I/O 60h Add. Add. Add. cycle 1 cycle 2 cycle 3 D0h 70h SR0 RB Block Erase Setup Command Confirm Code Block Erase Read Status Register ai08038c Block Address Input Figure 30. Reset AC Waveform W AL CL R I/O FFh tBLBH4 (Reset Busy time) RB ai08043 51/58 DC and AC parameters Figure 31. Program/Erase Enable Waveform NAND04GW3B2B, NAND08GW3B2A W tVHWH WP RB I/O 80h 10h ai12477 Figure 32. Program/Erase Disable Waveform W tVLWH WP High RB I/O 80h 10h ai12478 52/58 NAND04GW3B2B, NAND08GW3B2A DC and AC parameters 11.1 Ready/Busy Signal Electrical Characteristics Figure 34, Figure 33 and Figure 35 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation: (V – ) DDmax V OLmax R P min = ------------------------------------------------------------+ IL I OL So, 1,85V R P min ( 1,8V ) = -------------------------3mA + I L 3,2V R P min ( 3V ) = -------------------------8mA + I L where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 33. Ready/Busy AC Waveform ready VDD VOH VOL busy tf tr AI07564B Figure 34. Ready/Busy Load Circuit VDD RP ibusy DEVICE RB Open Drain Output VSS AI07563B 53/58 DC and AC parameters NAND04GW3B2B, NAND08GW3B2A Figure 35. Resistor Value Versus Waveform Timings For Ready/Busy Signal VDD = 3.3V, CL = 100pF 400 400 4 300 tr, tf (ns) 2.4 300 3 ibusy (mA) 200 200 2 1.2 100 100 3.6 3.6 0.8 1 0.6 0 3.6 3.6 1 2 RP (KΩ) tf tr 3 4 ibusy ai12476 1. T = 25°C. 11.2 Data Protection The Numonyx NAND device is designed to guarantee Data Protection during Power Transitions. A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold. In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept low (VIL) to guarantee hardware protection during power transitions as shown in the below figure. Figure 36. Data Protection VDD Nominal Range VLKO Locked Locked W Ai11086 54/58 NAND04GW3B2B, NAND08GW3B2A Package mechanical 12 Package mechanical Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline 1 48 e D1 B 24 25 L1 A2 A E1 E DIE A1 C CP α L TSOP-G 1. Drawing is not to scale. Table 22. Symbol TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data millimeters Typ Min Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.080 12.000 20.000 18.400 0.500 0.600 0.800 3° 0° 5° 11.900 19.800 18.300 – 0.500 12.100 20.200 18.500 – 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3° 0° 5° 0.4685 0.7795 0.7205 – 0.0197 0.0276 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283 A A1 A2 B C CP D1 E E1 e L L1 a 55/58 Part numbering NAND04GW3B2B, NAND08GW3B2A 13 Part numbering Table 23. Example: Device Type NAND Flash Memory Density 04G = 4Gb 08G = 8Gb Operating Voltage W = VDD = 2.7 to 3.6V Bus Width 3 = x8 Family Identifier B = 2112 Byte Page Device Options 2 = Chip Enable Don't Care Enabled Product Version A = First Version (NAND08GW3B2A) B= Second Version (NAND04GW3B2B) Package N = TSOP48 12 x 20mm (all devices) Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing Ordering Information Scheme NAND04GW3B2B N 6 E Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 56/58 NAND04GW3B2B, NAND08GW3B2A Revision history 14 Revision history Table 24. Date 14-Feb-2006 Document revision history Revision 1.0 Initial release. NAND08GW3B2A added, and Table 1: Product Description, Table 3: Valid Blocks, Table 5: Address Insertion, Table 6: Address Definition, Table 9: Status Register Bits and Table 23: Ordering Information Scheme updated. tBLBH4 timing added in Figure 7: Cache Read Operation. Table 8: Copy Back Program addresses added in Section 6.4: Copy Back Program. Definition of Status Register bit SR6 updated in Table 8: Copy Back Program addresses. tEHEL, tEHBL, tRHBL removed fromFigure 27: Page Read operation AC Waveform. Data integrity of 100,000 specified for ECC implemented. Note 2 removed below Table 7: Commands. Note 1 added below Figure 7: Cache Read Operation. tWHBH2 changed into tBLBH5 in Section 6.5: Cache Program, and Note 3 added below Figure 12: Cache Program Operation. Section 8.2: NAND Flash memory failure modes added in Section 8: Software algorithms. tWHALL added in Table 20: AC Characteristics for Command, Address, Data Input. tWHBH1 removed from Table 21: AC Characteristics for operations. tEHQX added in Figure 24: Sequential Data Output after Read AC waveforms. tRHQX added in Table 21: AC Characteristics for operations. Figure 27: Page Read operation AC Waveform updated for Ready/busy and tRHQX and tEHQX added. Figure 28: Page Program AC waveform updated for CL and Chip Enable. Datasheet status upgraded to Full Datasheet. Applied Numonyx branding. Changes 30-May-2006 2 08-Feb-2007 3 15-Feb-2007 10-Dec-2007 4 5 57/58 NAND04GW3B2B, NAND08GW3B2A Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 58/58