NP5Q128AE3ESFC0E

Numonyx® OmneoTM P5Q PCM 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface Features SPI bus compatible serial interface Maximum Clock Frequency – 66MHz (0 to +70 oC) – 33MHz (-30 to +85 oC) 2.7 V to 3.6 V single supply voltage Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol Quad I/O frequency of 50MHz, resulting in an equivalent clock frequency up to 200 MHz: Dual I/O frequency of 66MHz, resulting in an equivalent clock frequency up to 132 MHz: Continuous read of entire memory via single instruction: – Quad & Dual Output Fast Read – Quad & Dual Input Fast Program Uniform 128-Kbyte sectors (flash emulation) Write Operations – 128-Kbyte sectors erase (emulated) – Legacy Flash Page Program – Bit-alterable Page Writes – Page Program on all 1s (PreSet Writes) Write protections – Protected area size defined by four nonvolatile bits (BP0, BP1, BP2, and BP3) Electronic signature – JEDEC standard two-byte signature (DA18h) Density and Packaging – 128 Mbit density with SOIC16 package More than 1,000,000 write cycles Phase Change Memory (PCM) – Chalcogenide phase change storage element – Bit alterable write operation SO16 (MF) 300 mils width July 2010 Rev 4 1/56 www.numonyx.com 1 Contents Numonyx® Omneo™ P5Q Datasheet Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial data input (D/DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial data output (Q/DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hold (HOLD/DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Write protect (W/DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 4 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Quad input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 15 Active power and standby power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/56 Numonyx® Omneo™ P5Q Datasheet Contents 6.2 6.3 6.4 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Top/bottom bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 32 Dual output fast read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Quad output fast read (QOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Dual input fast program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Quad input fast program (QIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 8 9 10 11 12 13 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3/56 List of tables Numonyx® Omneo™ P5Q Datasheet List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Organization of Super Page regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Endurance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 53 Active Line Item Ordering Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4/56 Numonyx® Omneo™ P5Q Datasheet List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 26 Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 28 Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 31 Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dual output fast read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Quad output fast read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Page program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Dual input fast program (DIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Quad input fast program (QIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 51 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 53 5/56 Description Numonyx® Omneo™ P5Q Datasheet 1 1.1 Description Introduction Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the best attributes from other memory types in a new, highly scalable and flexible technology. Omneo™ P5Q PCM is a new type of nonvolatile semiconductor memory that stores information through a reversible structural phase change in a chalcogenide material. The material exhibits a change in material properties, both electrical and optical, when changed from the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the case of Phase Change Memory, information is stored via the change in resistance the chalcogenide material experiences upon undergoing a phase change. The material also changes optical properties after experiencing a phase change, a characteristic that has been successfully mastered for use in current rewritable optical storage devices such as rewritable CDs and DVDs. The Omneo™ P5Q PCM storage element consists of a thin film of chalcogenide contacted by a resistive heating element. In PCM, the phase change is induced in the memory cell by highly localized Joule heating caused by an induced current at the material junction. During a write operation, a small volume of the chalcogenide material is made to change phase. The phase change is a reversible process, and is modulated by the magnitude of injected current, the applied voltage, and the duration of the heating pulse. Omneo™ P5Q PCM combines the benefits of traditional floating gate flash, both NOR-type and NAND-type, with some of the key attributes of RAM and EEpROM. Like NOR flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM has the ability to write moderately fast. And like RAM and EEpROM, PCM supports bit alterable writes (overwrite). Unlike flash, no separate erase step is required to change information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile with data retention comparable NOR flash. However, at the current time, PCM technology appears to have a write cycling endurance better than that of NAND or NOR flash, but less than that of RAM. Unlike other proposed alternative memories, Omneo™ P5Q PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory storage element. Overall, the basic memory manufacturing process used to make PCM is less complex than that of NAND, NOR or DRAM. Historically, systems have adopted many different types of memory to meet different needs within a design. Some systems might include boot memory, configuration memory, data storage memory, high speed execution memory, and dynamic working memory. The demands of many of today’s designs require better performance from the memory subsystem and a reduction in the overall component count. PCM provides many of the attributes of different kinds of memory found in a typical design, enabling the opportunity to consolidate or eliminate of different types of memory. 6/56 Numonyx® Omneo™ P5Q Datasheet Description 1.2 Product Description The Omneo™ P5Q PCM s a 128-Mbit (16 Mb x 8) SPI phase change memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. Omneo™ P5Q PCM product supports four new, high-performance dual and quad input/output instructions: – – – – Dual output fast read (DOFR) instruction used to read data at up to 66 MHz by using both DQ0 and DQ1 pins as outputs Quad output fast read (QOFR) instruction used to read data at up to 50 MHz by using DQ0, DQ1, DQ2(W) and DQ3(HOLD) pins as outputs Dual input fast program (DIFP) instruction used to program data at up to 66 MHz by using both DQ0 and DQ1 pins as inputs Quad input fast program (QIFP) instruction used to program data at up to 50 MHz by using DQ0, DQ1, DQ2(W) and DQ3(HOLD) pins as inputs These new instructions double or quadruple the transfer bandwidth for read and program operations. The memory can be programmed 1 to 64 bytes at a time, using the page program, dual input fast program and quad input fast program instructions. The memory is organized as 128 sectors that are further divided into 1,024 pages each (131,072 pages in total). For compatibility with flash memory devices, Omneo™ P5Q PCM supports sector erase (128-Kbyte sector) and bulk erase instructions. It can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 128 Kbytes (sector granularity). 7/56 Description Figure 1. Logic diagram Numonyx® Omneo™ P5Q Datasheet VCC D C S W HOLD Q VSS AI05762 Signal names Signal Name C D (DQ0) Q (DQ1) S W (DQ2) HOLD (DQ3) VCC VSS 1. Standard x1 Mode Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Direction Input Input Output Input Input Input Dual Mode Function Serial Clock Serial Data Input/Output Serial Data Input/Output Chip Select Write Protect Hold Direction Input I/O(1) I/O(1) Input Input Input Supply voltage Ground Quad Mode Function Serial Clock Serial Data Input/Output Serial Data Input/Output Chip Select Serial Data Input/Output Serial Data Input/Output Direction Input I/O(1) I/O(1) Input I/O(1) I/O(1) 1. Serves as an input during Dual Input Fast Program (DIFP) and Quad Input Fast Program (QIFP) instructions. Serves as an output during Dual Output Fast Read (DOFR) and Quad Output Fast Read (QOFR) instructions. 8/56 Numonyx® Omneo™ P5Q Datasheet Figure 2. SO16 connections Description HOLD#/DQ3 VCC DU DU DU DU S DQ1 1. DU = don’t use. User must float this pins. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C DQ0 DU DU DU DU VSS W#/VPP/DQ2 AI13721c 2. See Package mechanical section for package dimensions, and how to identify pin-1. 3. For SO8 packing solutions please contact you local Numonyx field representative. 9/56 Signal descriptions Numonyx® Omneo™ P5Q Datasheet 2 2.1 Signal descriptions Serial data input (D/DQ0) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this pin is used as an output (DQ0). Data is shifted out on the falling edge of the Serial Clock (C). 2.2 Serial data output (Q/DQ1) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). During the dual input fast program (DIFP) and quad input fast program (QIFP) instructions, this pin is used for data input (DQ1). It is latched on the rising edge of the Serial Clock (C). During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this pin is used as data output (DQ1). Data is shifted out on the falling edge of Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on serial data output (DQ1) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is High, the device is deselected and serial data output (DQ1) is at high impedance. Unless an internal program, erase, or write status register cycle is in progress, the device will be in the standby power mode. Driving Chip Select (S) Low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 10/56 Numonyx® Omneo™ P5Q Datasheet Signal descriptions 2.5 Hold (HOLD/DQ3) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (DQ1) is high impedance, and serial data input (DQ0) and Serial Clock (C) are don’t care. To start the hold condition, the device must be selected, with Chip Select (S) driven Low. During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ3). It is latched on the rising edge of the Serial Clock (C). During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ3). Data is shifted out on the falling edge of Serial Clock (C). 2.6 Write protect (W/DQ2) This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP3, BP2, BP1 and BP0 bits of the status register). During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ2). It is latched on the rising edge of the Serial Clock (C). During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ2). Data is shifted out on the falling edge of Serial Clock (C). 2.7 VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 11/56 SPI modes Numonyx® Omneo™ P5Q Datasheet 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in standby mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1) Figure 3. Bus master and memory devices on the SPI bus VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK C SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD DQ1DQ0 SPI memory device VCC VSS R C DQ1 DQ0 SPI memory device VCC VSS R C DQ1DQ0 SPI memory device VCC VSS AI13725b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the serial data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the Omneo™ P5Q PCM is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 kΩ, assuming that the time constant R*Cp 12/56 Numonyx® Omneo™ P5Q Datasheet SPI modes (Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the SPI bus in high impedance. Example: Cp = 50 pF, that is R*Cp = 5 µs the application must ensure that the bus master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 MSB AI13730 13/56 Operating features Numonyx® Omneo™ P5Q Datasheet 4 Note: Operating features Definition of ‘Program’, ‘Bit-alterable Write’ and ‘Program on All 1s’: – Program on Omneo™ P5Q PCM devices writes only 0s of the user data to the array and treats 1s as data masks. This is similar to programming on a floating gate flash device. – Bit-alterable Write on Omneo™ P5Q PCM devices involves writing both 0s and 1s of the user data to the array. – Program on all 1s is similar to ‘program’ where only 0s are written to the array and 1s are treated as data masks. Program on all 1s also requires that the entire page being written is previously set to all 1s. Program on all 1s is also referred to as PreSET Write. 4.1 Page programming To program/write one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data byte. This is followed by the internal program cycle (of duration tPP). To spread this overhead, the page program (PP) instruction allows up to 64 bytes to be programmed/written at a time, provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Page program (PP) and Table 15: AC characteristics). 4.2 Dual input fast program The dual input fast program (DIFP) instruction makes it possible to program/write up to 64 bytes using two input pins at the same time. For optimized timings, it is recommended to use the dual input fast program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather than using several dual input fast program (DIFP) sequences each containing only a few bytes (see Section 6.11: Dual input fast program (DIFP)). 4.3 Quad input fast program The quad input fast program (QIFP) instruction makes it possible to program/write up to 64 bytes using four input pins at the same time. For optimized timings, it is recommended to use the quad input fast program (QIFP) instruction to program all consecutive targeted bytes in a single sequence rather than using several quad input fast program (QIFP) sequences each containing only a few bytes (see Section 6.12: Quad input fast program (QIFP)). 14/56 Numonyx® Omneo™ P5Q Datasheet Operating features 4.4 Sector erase and bulk erase A sector can be erased to all 1s (FFh) at a time using the sector erase (SE) instruction. The entire memory can be erased using the bulk erase (BE) instruction. This starts an internal erase cycle (of duration tSE or tBE). The erase instruction must be preceded by a write enable (WREN) instruction. 4.5 Polling during a write, program or erase cycle A further improvement in the time to write status register (WRSR), page program (PP), dual input fast program (DIFP), quad input fast program (QIFP), or erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSMEN, tSMEX, tSE, or tBE). The write in progress (WIP) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle, or erase cycle is complete. 4.6 Active power and standby power When Chip Select (S) is Low, the device is selected, and in the active power mode. When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The device consumption drops to ICC1. 4.7 Status register The status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read status register (RDSR) for a detailed description of the status register bits. 15/56 Operating features Numonyx® Omneo™ P5Q Datasheet 4.8 Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 4.8.1 Protocol-related protections The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the Omneo™ P5Q PCM features the following data protection mechanisms: n Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification Program, erase, and write status register are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following events: – Power-up – Write disable (WRDI) instruction completion – Write status register (WRSR) instruction completion – Page program (PP) instruction completion – Dual input fast program (DIFP) instruction completion – Quad input fast program (QIFP) instruction completion – Sector erase (SE) instruction completion – Bulk erase (BE) instruction completion The Block Protect bits (see Section 6.4.3: BP3, BP2, BP1, BP0 bits) and top/bottom bit (see Section 6.4.4: Top/bottom bit) allow part of the memory to be configured as readonly. This is the Software Protect Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits, Top/Bottom (TB) bit and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). For more details, see Section 6.5: Write status register (WRSR). n n n n 16/56 Numonyx® Omneo™ P5Q Datasheet Table 1. Protected area sizes Memory content Protected area none Upper 128th (Sector 127) Upper 64th (Sectors 126 to 127) Upper 32nd (Sectors 124 to 127) Upper 16th (Sectors 120 to 127) Upper 8th (Sectors 112 to 127) Upper quarter (Sectors 96 to 127) Upper half (Sectors 64 to 127) All sectors (Sectors 0 to 127) none Lower 128th (Sector 0) Lower 64th (Sectors 0 to 1) Lower 32nd (Sectors 0 to 3) Lower 16th (Sectors 0 to 7) Lower 8th (Sectors 0 to15) Lower 4th (Sectors 0 to 31) Lower half (Sectors 0 to 63) All sectors (Sectors 0 to 127) Operating features Status register contents TB bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 BP bit 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 BP bit 2 0 0 0 0 1 1 1 1 X(2) 0 0 0 0 1 1 1 1 X (2) BP bit 1 0 0 1 1 0 0 1 1 X(2) 0 0 1 1 0 0 1 1 X(2) BP bit 0 0 1 0 1 0 1 0 1 X(2) 0 1 0 1 0 1 0 1 X(2) Unprotected area All sectors(1) (Sectors 0 to 127) Sectors 0 to 126 Sectors 0 to 125 Sectors 0 to 123 Sectors 0 to 119 Sectors 0 to 111 Sectors 0 to 95 Sectors 0 to 63 None All sectors(1) (Sectors 0 to 127) Sectors 1 to 127 Sectors 2 to 127 Sectors 4 to 127 Sectors 8 to 127 Sectors 16 to 127 Sectors 32 to 127 Sectors 64 to 127 None 1. The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP3, BP2, BP1, BP0) are 0 2. X can be 0 or 1 1. 17/56 Operating features Numonyx® Omneo™ P5Q Datasheet 4.9 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress. To enter the hold condition, the device must be selected, with Chip Select (S) Low. The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 5). The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes Low (this is shown in Figure 5). During the hold condition, the serial data output (DQ1) is high impedance, and serial data input (DQ0) and Serial Clock (C) are don’t care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the hold condition. Figure 5. Hold condition activation C HOLD Hold condition (standard use) Hold condition (non-standard use) AI02029D 18/56 Numonyx® Omneo™ P5Q Datasheet Memory organization 5 Memory organization The memory is organized as: – 16,772,216 bytes (8 bits each) – 8 Super Page programming regions (16 sectors each) – 128 sectors (128 Kbytes each) – 262,144 pages (64 bytes each) Each page can be individually programmed (bits are programmed from ‘1’ to ‘0’) or written (bit alterable: ‘1’ can be altered to ‘0’ and ‘0’ can be altered to ‘1’). The device is sector or bulk erasable (bits are erased from ‘0’ to ‘1’). Table 2. Sector 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 Memory organization Address range FE0000 FC0000 FA0000 F80000 F60000 F40000 F20000 F00000 EE0000 EC0000 EA0000 E80000 E60000 E40000 E20000 E00000 DE0000 DC0000 DA0000 D80000 D60000 D40000 D20000 D00000 CE0000 FFFFFF FDFFFF FBFFFF F9FFFF F7FFFF F5FFFF F3FFFF F1FFFF EFFFFF EDFFFF EBFFFF E9FFFF E7FFFF E5FFFF E3FFFF E1FFFF DFFFFF DDFFFF DBFFFF D9FFFF D7FFFF D5FFFF D3FFFF D1FFFF CFFFFF Sector 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 Address range CC0000 CA0000 C80000 C60000 C40000 C20000 C00000 BE0000 BC0000 BA0000 B80000 B60000 B40000 B20000 B00000 AE0000 AC0000 AA0000 A80000 A60000 A40000 A20000 A00000 9E0000 9C0000 CDFFFF CBFFFF C9FFFF C7FFFF C5FFFF C3FFFF C1FFFF BFFFFF BDFFFF BBFFFF B9FFFF B7FFFF B5FFFF B3FFFF B1FFFF AFFFFF ADFFFF ABFFFF A9FFFF A7FFFF A5FFFF A3FFFF A1FFFF 9FFFFF 9DFFFF 19/56 Memory organization Table 2. Sector 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Numonyx® Omneo™ P5Q Datasheet Memory organization (continued) Address range 9A0000 980000 960000 940000 920000 900000 8E0000 8C0000 8A0000 880000 860000 840000 820000 800000 7E0000 7C0000 7A0000 780000 760000 740000 720000 700000 6E0000 6C0000 6A0000 680000 660000 640000 620000 600000 5E0000 5C0000 5A0000 580000 560000 9BFFFF 99FFFF 97FFFF 95FFFF 93FFFF 91FFFF 8FFFFF 8DFFFF 8BFFFF 89FFFF 87FFFF 85FFFF 83FFFF 81FFFF 7FFFFF 7DFFFF 7BFFFF 79FFFF 77FFFF 75FFFF 73FFFF 71FFFF 6FFFFF 6DFFFF 6BFFFF 69FFFF 67FFFF 65FFFF 63FFFF 61FFFF 5FFFFF 5DFFFF 5BFFFF 59FFFF 57FFFF Sector 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Address range 540000 520000 500000 4E0000 4C0000 4A0000 480000 460000 440000 420000 400000 3E0000 3C0000 3A0000 380000 360000 340000 320000 300000 2E0000 2C0000 2A0000 280000 260000 240000 220000 200000 1E0000 1C0000 1A0000 180000 160000 140000 120000 100000 55FFFF 53FFFF 51FFFF 4FFFFF 4DFFFF 4BFFFF 49FFFF 47FFFF 45FFFF 43FFFF 41FFFF 3FFFFF 3DFFFF 3BFFFF 39FFFF 37FFFF 35FFFF 33FFFF 31FFFF 2FFFFF 2DFFFF 2BFFFF 29FFFF 27FFFF 25FFFF 23FFFF 21FFFF 1FFFFF 1DFFFF 1BFFFF 19FFFF 17FFFF 15FFFF 13FFFF 11FFFF 20/56 Numonyx® Omneo™ P5Q Datasheet Table 2. Sector 7 6 5 4 Memory organization Memory organization (continued) Address range 0E0000 0C0000 0A0000 080000 0FFFFF 0DFFFF 0BFFFF 09FFFF Sector 3 2 1 0 Address range 060000 040000 020000 000000 07FFFF 05FFFF 03FFFF 01FFFF Table 3. Organization of Super Page regions Sectors 112 to 127 96 to 111 80 to 95 64 to 79 48 to 63 32 to 47 16 to 31 0 to 15 Address Range E00000 to FFFFFF C00000 to DFFFFF A00000 to BFFFFF 800000 to 9FFFFF 600000 to 7FFFFF 400000 to 5FFFFF 200000 to 3FFFFF 000000 to 1FFFFF Programming Region 7 6 5 4 3 2 1 0 21/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input DQ0 is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input DQ0, each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ), dual output fast read (DOFR), quad output fast read (QOFR), read status register (RDSR) or read identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a page program (PP), dual input fast program (DIFP), quad input fast program (QIFP), sector erase (SE), bulk erase (BE), write status register (WRSR), write enable (WREN), write disable (WRDI), Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write status register cycle, program cycle erase cycle are ignored, and the internal write status register cycle, program cycle, erase cycle continues unaffected. Note: Output Hi-Z is defined as the point where data out is no longer driven. 22/56 Numonyx® Omneo™ P5Q Datasheet Table 4. Instruction WREN WRDI RDID RDSR WRSR READ Write enable Write disable Read identification 1001 1110 Read status register Write status register Read data bytes 0000 0101 0000 0001 0000 0011 0000 1011 0011 1011 0110 1011 0000 0010 0010 0010 1101 0001 1010 0010 1101 0011 1101 0101 0011 0010 1101 0111 1101 1001 1101 1000 1100 0111 9Eh 05h 01h 03h 0Bh 3Bh 6Bh 02h 22h D1h A2h D3h D5h 32h D7h D9h D8h C7h 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Instructions Instruction set Description One-byte instruction code 0000 0110 0000 0100 1001 1111 06h 04h 9Fh Address Dummy bytes bytes 0 0 0 0 0 0 Data bytes 0 0 1 to 3 1 to 3 1 to ∞ 1 1 to ∞ 1 to ∞ 1 to ∞ 1 to ∞ 1 to 64 1 to 64 1 to 64 1 to 64 1 to 64 1 to 64 1 to 64 1 to 64 1 to 64 0 0 FAST_READ Read data bytes at higher speed DOFR QOFR Dual output fast read Quad output fast read Page program (Legacy Program) PP Page program (Bit-alterable write) Page program (On all 1s) Dual input fast program (Legacy Program) DIFP Dual input fast program (Bit-alterable write) Dual input fast program (On all 1s) Quad input fast program (Legacy Program) QIFP Quad input fast program (Bit-alterable write) Quad input fast program (On all 1s) SE BE Sector erase Bulk erase (2) 23/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.1 Write enable (WREN) The write enable (WREN) instruction (Figure 6) sets the write enable latch (WEL) bit. The write enable latch (WEL) bit must be set prior to every page program (PP), dual input fast program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR) instruction. The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 6. Write enable (WREN) instruction sequence S 0 C Instruction DQ0 High Impedance DQ1 AI13731 1 2 3 4 5 6 7 24/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.2 Write disable (WRDI) The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit. The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions: – Power-up – Write disable (WRDI) instruction completion – Write status register (WRSR) instruction completion – Page program (PP) instruction completion – Dual input fast program (DIFP) instruction completion – Quad input fast program (QIFP) instruction completion – Sector erase (SE) instruction completion – Bulk erase (BE) instruction completion Figure 7. Write disable (WRDI) instruction sequence S 0 C Instruction DQ0 High Impedance DQ1 AI13732 1 2 3 4 5 6 7 25/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.3 Read identification (RDID) The read identification (RDID) instruction allows to read the device identification data: – Manufacturer identification (1 byte) – Device identification (2 bytes) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. Any read identification (RDID) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification stored in the memory will be shifted out on serial data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8. The read identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the standby power mode. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read identification (RDID) data-out sequence Device identification Manufacturer identification Memory Type (Upper Byte) DAh Memory Capacity (Lower Byte) 18h 20h Figure 8. S Read identification (RDID) instruction sequence and data-out sequence 0 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 Instruction D Manufacturer identification High Impedance Q MSB 15 14 13 MSB AI06809c Device identification 3 2 1 0 26/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase, write status register cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the status register continuously, as shown in Figure 9. RDSR is the only instruction accepted by the device while a program, erase, write status register operation is in progress. Table 6. b7 SRWD BP3 TB BP2 BP1 BP0 WEL Status register format b0 WIP Status register write protect Top/bottom bit Block protect bits Write enable latch bit Write in progress bit The status and control bits of the status register are as follows: 6.4.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program, erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is in progress. While WIP is ‘1’, RDSR is the only instruction the device will accept; all other instructions are ignored. 6.4.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is reset and no write status register, program, erase instruction is accepted. 6.4.3 BP3, BP2, BP1, BP0 bits The block protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against program (or write) and erase instructions. These bits are written with the write status register (WRSR) instruction. When one or more of the block protect (BP3, BP2, BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 1) becomes protected against page program (PP), dual input fast program (DIFP),quad input fast program (QIFP), and sector erase (SE) instructions. The block protect (BP3, BP2, BP1, BP0) bits can be written provided that the hardware protected mode has not been set.The bulk erase (BE) instruction is executed if, and only if, all block protect (BP3, BP2, BP1, BP0) bits are 0. 27/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.4.4 Top/bottom bit The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register (WRSR) instruction provided that the write enable (WREN) instruction has been issued. The top/bottom (TB) bit is used in conjunction with the block protect (BP0, BP1, BP2, BP3) bits to determine if the protected area defined by the block protect bits starts from the top or the bottom of the memory array: – When top/bottom bit is reset to ‘0’ (default value), the area protected by the block protect bits starts from the top of the memory array (see Table 1: Protected area sizes) – When top/bottom bit is set to ‘1’, the area protected by the block protect bits starts from the bottom of the memory array (see Table 1: Protected area sizes). The top/bottom bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low. 6.4.5 SRWD bit The status register write disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The status register write disable (SRWD) bit and the write protect (W) signal allow the device to be put in the hardware protected mode (when the status register write disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the nonvolatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only bits and the write status register (WRSR) instruction is no longer accepted for execution. Figure 9. S 0 C Instruction DQ0 Status register out High Impedance DQ1 7 MSB 6 5 4 3 2 1 0 7 MSB AI13734 Read status register (RDSR) instruction sequence and data-out sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Status register out 6 5 4 3 2 1 0 7 28/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.5 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). The write status register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data input (DQ0). The instruction sequence is shown in Figure 10. The write status register (WRSR) instruction has no effect on b1 and b0 of the status register. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The write status register (WRSR) instruction allows the user to change the values of the block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1. The write status register (WRSR) instruction also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the hardware protected mode (HPM). The write status register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. Read Status Register (RDSR) is the only instruction accepted while WRSR operation is in progress; all other instructions are ignored. Figure 10. Write status register (WRSR) instruction sequence S 0 C Instruction Status register in 7 High Impedance DQ1 AI13735 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ0 6 5 4 3 2 1 0 MSB 29/56 Instructions Table 7. W 1 0 Numonyx® Omneo™ P5Q Datasheet Protection modes SRWD bit 0 0 Software protected (SPM) Mode Write protection of the status register Status register is writable (if the WREN instruction has set the WEL bit) The values in the SRWD, TB, BP3, BP2, BP1 and BP0 bits can be changed Status register is hardware write protected The values in the SRWD, TB, BP3, BP2, BP1 and BP0 bits cannot be changed Memory content Protected area(1) Unprotected area(1) 1 1 Protected against page program, sector erase, and bulk erase Ready to accept page program, and sector erase instructions 0 1 Hardware protected (HPM) Protected against page program, sector erase, and bulk erase Ready to accept page program, and sector erase instructions 1. As defined by the values in the block protect (BP3, BP2, BP1, BP0) bits of the status register, as shown in Table 1. The protection features of the device are summarized in Table 7. When the status register write disable (SRWD) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the status register write disable (SRWD) bit of the status register is set to ‘1’, two cases need to be considered, depending on the state of Write Protect (W): – If Write Protect (W) is driven High, it is possible to write to the status register provided that the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction. – If write protect (W) is driven Low, it is not possible to write to the status register even if the write enable latch (WEL) bit has previously been set by a write enable (WREN) instruction (attempts to write to the status register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the block protect (BP3, BP2, BP1, BP0) bits of the status register, are also hardware protected against data modification. Regardless of the order of the two events, the hardware protected mode (HPM) can be entered: – by setting the status register write disable (SRWD) bit after driving Write Protect (W) Low – or by driving Write Protect (W) Low after setting the status register write disable (SRWD) bit. The only way to exit the hardware protected mode (HPM) once entered is to pull Write Protect (W) High. 30/56 Numonyx® Omneo™ P5Q Datasheet Instructions If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can never be activated, and only the software protected mode (SPM), using the block protect (BP3, BP2, BP1, BP0) bits of the status register, can be used. 6.6 Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address A[23:0], each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on serial data output (DQ1), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read data bytes (READ) instruction, while an erase, program, write is in progress, is rejected without having any effects on the cycle that is in progress. Figure 11. S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Read data bytes (READ) instruction sequence and data-out sequence DQ0 High Impedance DQ1 23 22 21 MSB 3 2 1 0 Data out 1 7 6 5 4 3 2 1 0 Data out 2 7 MSB AI13736b 31/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.7 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on serial data output (DQ1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase, program, write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 10 28 29 30 31 DQ0 High Impedance DQ1 23 22 21 3 2 1 0 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 7 6 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI13737b DQ1 7 MSB 6 5 4 3 2 32/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.8 Dual output fast read (DOFR) The dual output fast read (DOFR) instruction is very similar to the read data bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the read data bytes at higher speed (FAST_READ) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the dual output fast read instruction is followed by a 3-byte address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole memory can, therefore, be read with a single dual output fast read (DOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 13. Dual output fast read instruction sequence S Mode 3 C Mode 2 Instruction DQ0 24-bit address (1) 23 22 21 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 DQ1 High Impedance S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DATA OUT 1 DATA OUT 2 DATA OUT 3 DQ1 7 MSB 5 3 1 7 MSB 5 3 1 7 MSB 5 3 1 DATA OUT n 7 MSB 5 3 1 MSB ai13574b 33/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.9 Quad output fast read (QOFR) The quad output fast read (QOFR) instruction is very similar to the read data bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on four pins (pins DQ0, DQ1, DQ2 and DQ3) instead of only one. Outputting the data on four pins instead of one quadruples the data transfer bandwidth compared to the read data bytes at higher speed (FAST_READ) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the quad output fast read instruction is followed by a 3-byte address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0, DQ1, DQ2 and DQ3 at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0, DQ1, DQ2 and DQ3. The whole memory can, therefore, be read with a single quad output fast read (QOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 14. Quad output fast read instruction sequence S C Instruction 6Bh DQ0 24 bit Address 8 dummy cycles DQ1 Don’t care Don’t care Don’t care DQ2 DQ3 ‘1’ 1. After 40 clock cycles (cycle labeled 39 in the figured), data inputs (DQi) must be released because they become outputs. 2. Once 6Bh command is recognized, W and HOLD functionality is automatically disabled. 34/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.10 Note: Page program (PP) This definition applies to all flavors of Page Program: Legacy Program, Bit-alterable Write and Program on all 1s. The page program (PP) instruction allows bytes to be programmed/written in the memory. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed/written correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed/written at the requested addresses without having any effects on the other bytes of the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the page program cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a Page Program operation is in progress; all other instructions are ignored. A page program (PP) instruction applied to a page which is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1 and Table 2) is not executed. 35/56 Instructions Numonyx® Omneo™ P5Q Datasheet Figure 15. Page program (PP) instruction sequence S 0 C Instruction 24-bit address (1) Data byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 DQ0 23 22 21 MSB 3 2 1 0 7 MSB 6 5 4 3 2 1 0 S 2072 2073 2074 2075 2076 2077 2 2078 1 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte 64 2079 0 AI13739b DQ0 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 36/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.11 Note: Dual input fast program (DIFP) This definition applies to all flavors of Dual input fast program: Legacy Program, Bitalterable Write and Program on all 1s. The dual input fast program (DIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the page program (PP) instruction. The dual input fast program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed/written correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed/written at the requested addresses without having any effects on the other bytes in the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the dual input fast program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (DIFP) sequences each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the dual input fast program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the dual input fast program (DIFP) cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a dual input fast program operation is in progress; all other instructions are ignored. A dual input fast program (DIFP) instruction applied to a page that is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1) is not executed. 37/56 Instructions Numonyx® Omneo™ P5Q Datasheet Figure 16. Dual input fast program (DIFP) instruction sequence S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 DQ0 23 22 21 3 2 1 0 DQ1 High Impedance S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C DQ0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DATA IN 1 DQ1 7 MSB 5 3 1 DATA IN 2 7 MSB 5 3 1 DATA IN 3 7 MSB 5 3 1 7 DATA IN 4 5 3 1 7 DATA IN 5 5 3 1 DATA IN 64 7 MSB AI14229 5 3 1 MSB MSB 38/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.12 Note: Quad input fast program (QIFP) The following description applies to all flavors of Quad input fast program: Legacy Program, Bit-alterable Write and Program on all 1s. The quad input fast program (QIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on four pins (pin DQ0, DQ1, DQ2 and DQ3) instead of only one. Inputting the data on four pins instead of one quadruples the data transfer bandwidth compared to the page program (PP) instruction. The quad input fast program (QIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the quad input fast program (QIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several quad input fast program (QIFP) sequences each containing only a few bytes (see Table 15: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the quad input fast program (QIFP) instruction is not executed As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the quad input fast program (DIFP) cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a quad input fast program operation is in progress; all other instructions are ignored. A quad input fast program (QIFP) instruction applied to a page that is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1) is not executed 39/56 Instructions Numonyx® Omneo™ P5Q Datasheet Figure 17. Quad input fast program (QIFP) instruction sequence S C DATA IN DATA IN 3 0 4 0 4 4 4 DATA IN 5 0 4 6 32h DQ0 4 1 0 4 2 DQ1 Don’t care 5 1 5 1 5 1 5 5 1 5 DQ2 Don’t care 2 6 2 2 6 2 2 6 2 DQ3 Don’t care ‘1’ 3 7 MSB 3 3 7 MSB 3 3 7 MSB 3 1. Once 32h is recognized, W and HOLD functionality is automatically disabled. 40/56 Numonyx® Omneo™ P5Q Datasheet Instructions 6.13 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on serial data input (DQ0). Any address inside the sector (see Table 2) is a valid address for the sector erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is initiated. While the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while device is busy with erase operation; all other instructions are ignored. A sector erase (SE) instruction applied to a page which is protected by the block protect (BP3, BP2, BP1, BP0) bits (see Table 1 and Table 2) is not executed. Figure 18. Sector erase (SE) instruction sequence S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 29 30 31 DQ1 23 22 MSB 2 1 0 AI13742b 41/56 Instructions Numonyx® Omneo™ P5Q Datasheet 6.14 Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on serial data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed bulk erase cycle (whose duration is tBE) is initiated. While the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while device is busy with erase operation; all other instructions are ignored. The bulk erase (BE) instruction is executed only if all block protect (BP3, BP2, BP1, BP0) bits are 0. The bulk erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 19. Bulk erase (BE) instruction sequence S 0 C Instruction DQ0 1 2 3 4 5 6 7 AI13743 42/56 Numonyx® Omneo™ P5Q Datasheet Power-up and power-down 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC until VCC reaches the correct value: – VCC(min) at power-up, and then for a further delay of tVSL – VSS at power-down. A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the power on reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all write enable (WREN), page program (PP), dual input fast program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No write status register, program, erase instructions should be sent until the later of: – tPUW after VCC has passed the VWI threshold – tVSL after VCC has passed the VCC(min) level. These values are specified in Table 8. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for read instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state: – The device is in the standby power mode – The write enable latch (WEL) bit is reset – The write in progress (WIP) bit is reset Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the power on reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if power-down occurs while a write, program or erase cycle is in progress, some data corruption may result). 43/56 Initial delivery state Figure 20. Power-up timing VCC VCC(max) Numonyx® Omneo™ P5Q Datasheet Program, erase and write commands are rejected by the device Chip selection not allowed VCC(min) Reset state of the device VWI tPUW tVSL Read access allowed Device fully accessible time AI04009C Table 8. Symbol tVSL(1) tPUW(1) VWI(1) Power-up timing and VWI threshold Parameter VCC(min) to S Low Time delay to write instruction Write inhibit voltage Min 100 1 1.5 10 2.5 Max Unit µs ms V 1. These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). The status register contains 00h (all status register bits are 0). 44/56 Numonyx® Omneo™ P5Q Datasheet Maximum ratings 9 Maximum ratings Stressing the device outside the ratings listed in Table 9: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE program and other relevant quality documents. Table 9. Symbol VIO VCC VESD Absolute maximum ratings Parameter Input and output voltage (with respect to ground) Supply voltage Electrostatic discharge voltage (human body model)(1) Min –0.6 –0.6 –2000 Max VCC + 0.6 4.0 2000 Unit V V V 1. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). 45/56 DC and AC parameters Numonyx® Omneo™ P5Q Datasheet 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10. Symbol VCC TA TA Supply voltage Ambient operating temperature (66MHz) Ambient operating temperature (33MHz) Operating conditions Parameter Min 2.7 0 -30 Typ Max 3.6 70 +85 Unit V °C °C Omneo™ P5Q PCM endurance is different than traditional non-volatile memory. For PCM a “write cycle” is defined as any time a bit changes within a 32-byte page. Table 11. Parameter Write Cycle Endurance Specification Condition Main Block (VPP = VPPH) Min 1,000,000 Units Cycles per 32-Byte Page Notes 1 Parameter Write Cycle Parameter Block (VPP = VPPH) 1,000,000 1. In typical operation VPP program voltage is VPPL. Table 12. Symbol CL AC measurement conditions Parameter Load capacitance Input rise and fall times Input pulse voltages Input timing reference voltages Output timing reference voltages Min 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max Unit pF ns V V V Figure 21. AC measurement I/O waveform Input levels 0.8VCC Input and output timing reference levels 0.7VCC 0.5VCC 0.3VCC AI07455 0.2VCC 46/56 Numonyx® Omneo™ P5Q Datasheet Table 13. Symbol CIN/OUT CIN DC and AC parameters Capacitance(1) Parameter Input/output capacitance (DQ0/DQ1) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min Max 8 6 Unit pF pF 1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz. 47/56 DC and AC parameters Table 14. Symbol ILI ILO ICC1 Numonyx® Omneo™ P5Q Datasheet DC characteristics Parameter Input leakage current Output leakage current Standby current S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9VCC at 66 MHz, DQ1 = open Operating current (READ) C = 0.1VCC / 0.9VCC at 33 MHz, DQ1 = open 7 20 mA mA Test condition (in addition to those in Table 10) Min Max ±2 ±2 200 16 Unit µA µA µA mA ICC3 Operating current (DOFR) C = 0.1VCC / 0.9VCC at 66 MHz, DQ0=DQ1 = open C = 0.1VCC / 0.9VCC at 50 MHz, DQ0=DQ1=DQ2=DQ3 = open S = VCC S = VCC S = VCC S = VCC S = VCC – 0.5 0.7VCC IOL = 1.6 mA IOH = –100 µA VCC–0.2 Operating current (QOFR) Operating current (PP) ICC4 Operating current (DIFP) Operating current (QIFP) ICC5 ICC6 VIL VIH VOL VOH Operating current (WRSR) Operating current (SE, BE) Input low voltage Input high voltage Output low voltage Output high voltage 24 50 50 50 50 50 0.3VCC VCC+0.4 0.4 mA mA mA mA mA mA V V V V 48/56 Numonyx® Omneo™ P5Q Datasheet Table 15. AC characteristics(1) Test conditions specified in Table 10 and Table 12 Symbol Alt. Parameter Clock frequency for the following instructions: DOFR, DIFP, FAST_READ, SE, BE, WREN, WRDI, RDID, RDSR, WRSR (0 to +70 oC) Clock frequency for the following instructions: QOFR, QIFP (0 to +70 oC) fR f C / fR Clock frequency for READ instructions (0 to +70 oC) Clock frequency for ALL instructions: QOFR, QIFR, DOFR, DIFP, FAST_READ, READ SE, BE, WREN, WRDI, RDID, RDSR, WRSR (-30 to +85 oC) tCLH Clock High time tCLL Clock Low time Clock rise time(5) (peak to peak) Min DC and AC parameters Typ(2) Max Unit fC fC D.C. 66 MHz D.C. D.C. D.C. 6.5 6.5 0.1 0.1 5 5 2 5 5 5 80 50 33 33 MHz MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns tCH(3) tCL(2) tCLCH(4) tCHCL(4) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(4) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(4) tHLQZ(4) tWHSL(6) tSHWL (6) Clock fall time(5) (peak to peak) tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU Data in setup time tDH Data in hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH S deselect time tDIS tV tHO Output disable time Clock Low to Output valid under 30 pF Clock Low to Output valid under 10 pF Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C) tLZ tHZ HOLD to Output Low-Z HOLD to Output High-Z Write protect setup time Write protect hold time S High to standby mode 8 9 8 0 5 5 5 5 10 10 20 100 30 ns ns ns ns ns ns ns ns ns ns ns ns µs tRDP(4) 49/56 DC and AC parameters Table 15. AC characteristics(1) (continued) Numonyx® Omneo™ P5Q Datasheet Test conditions specified in Table 10 and Table 12 Symbol tW Alt. Parameter Write status register cycle time Page program cycle time (64 bytes) (Legacy Program & Bit-alterable Write) Page program cycle time (64 bytes) (Program on all 1s) Sector erase cycle time Bulk erase cycle time Min Typ(2) 200 120 71 400 50 Max 350 360 µs 280 800 100 ms s Unit µs tPP(7) tSE tBE 1. Preliminary data. 2. Typical values given for TA = 25° C @ nominal VCC. 3. tCH + tCL must be greater than or equal to 1/ fC. 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 7. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 64). Figure 22. Serial input timing tSHSL S tCHSL C tDVCH tCHDX DQ0 MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH DQ1 High Impedance AI13728 50/56 Numonyx® Omneo™ P5Q Datasheet DC and AC parameters Figure 23. Write protect setup and hold timing during WRSR when SRWD=1 W/VPP tWHSL tSHWL S C DQ0 High Impedance DQ1 AI07439c Figure 24. Hold timing S tHLCH tCHHL C tCHHH tHLQZ DQ1 tHHQX tHHCH DQ0 HOLD AI13746 51/56 DC and AC parameters Figure 25. Output timing S Numonyx® Omneo™ P5Q Datasheet tCH C tCLQV tCLQX DQ1 tQLQH tQHQL ADDR. DQ0 LSB IN AI13729 tCLQV tCLQX tCL tSHQZ LSB OUT 52/56 Numonyx® Omneo™ P5Q Datasheet Package mechanical 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline 1. Drawing is not to scale. Table 16. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Millimeters Inches Max 2.65 0.30 0.51 0.32 10.50 7.60 – 10.65 0.75 1.27 8° 0.10 0.050 Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 – 0.394 0.010 0.016 0° Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 Symbol Typ A A1 B C D E e H h L θ ddd 1.27 Min 2.35 0.10 0.33 0.23 10.10 7.40 – 10.00 0.25 0.40 0° 53/56 Ordering information Numonyx® Omneo™ P5Q Datasheet 12 Ordering information This section defines all active line items that can be ordered. Table 17. Active Line Item Ordering Table Part Number NP5Q128A13ESFC0E NP5Q128AE3ESFC0E Description 3V, SOIC, PbFree,10.34x10.34x2.54, 16 lead (0 to +70 oC) 3V, SOIC, PbFree,10.34x10.34x2.54, 16 lead (-30 to +85 oC) Note: For SO8 packaging solutions please contact your local Numonyx representative for details. 54/56 Numonyx® Omneo™ P5Q Datasheet Revision history 13 Revision history Table 18. Date June 2009 Document revision history Revision 1 Initial release Removed Numonyx Confidential Added Figures 23&24 Revised Hold Condition Verbiage 4.9 Removed Streaming Mode from Datasheet Added P5Q Product Designator Added Numonyx® Omneo™ Branding Added endurance verbiage (table-11) Revised DC and AC Section: tVSL (min), tCLQV (max), tHLQZ (max), Page Program (typ/max), Sector Erase (typ/max), Bulk Erase (max) Revised cover page with -30 to +85C Revised read current at 33MHz (Table 14) Revised AC characteristics for -30 to +85C (Table 15) Revised Ordering information Changes August 2009 2 April 2010 3 July 2010 4 55/56 Numonyx® Omneo™ P5Q Datasheet Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, StrataFlash, Axcell, Forté, and Omneo are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2010, Numonyx, B.V., All Rights Reserved.. 56/56