NP8P128AE3BSM60E

Numonyx® Omneo™ P8P PCM 128-Mbit Parallel Phase Change Memory Datasheet Product Features High Performance Read/Write — 115 ns initial read access — 135 ns initial read access — 25 ns 8-word asynchronous-page read Architecture — Asymmetrically-blocked architecture — Four 32-KByte parameter blocks: top or bottom configuration — 128-KByte main blocks — Serial Peripheral Interface (SPI) to enable lower pin count on-board programming Phase Change Memory (PCM) — Chalcogenide phase change storage element — Bit alterable write operation Voltage and Power — VCC (core) voltage: 2.7 V – 3.6 V — VCCQ (I/O) voltage: 1.7 V – 3.6 V — Standby current: 80 µA (Typ) Quality and Reliability — More than 1,000,000 write cycles — 90 nm PCM technology Temperature — Operating temperature -30 °C to +85 °C (135ns initial read access) — Operating temperature 0 °C to +70 °C (115ns initial read access) Security — One-Time Programmable Registers: • 64 unique factory device identifier bits • 2112 user-programmable OTP bits — Selectable OTP Space in Main Array: • Four pre-defined 32-KByte blocks (top or bottom configuration) • Three adjacent Main Blocks available for boot code or other secure information — Absolute write protection: VPP = VSS — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down Simplified Software Management — No block erase or cleanup required — Bit “twiddle” in either direction (1:0, 0:1) — 35 µs (Typ) program suspend — 35 µs (Typ) erase suspend — Numonyx™ Flash Data Integrator optimized — Scalable Command Set and Extended Command Set compatible — Common Flash Interface capable Density and Packaging — 128 Mbit density — 56-Lead TSOP package — 64-Ball Numonyx Easy BGA package 316144-07 July 2010 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Legal Lines and Disclaimers Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the Numonyx webbiest at http://www.numonyx.com. Numonyx, the Numonyx logo, StrataFlash, Axcell, Forté, and Omneo are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2010, Numonyx, B.V., All Rights Reserved. Datasheet 2 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 1.0 Product Description ................................................................................................... 6 1.1 Introduction ....................................................................................................... 6 1.2 Product Overview ................................................................................................ 7 1.3 Memory Map....................................................................................................... 9 Package Information ............................................................................................... 11 2.1 56-Lead TSOP................................................................................................... 11 2.2 64-Ball Easy BGA Package .................................................................................. 12 Pinouts and Ballouts ................................................................................................ 14 Signals .................................................................................................................... 16 Bus Operations ........................................................................................................ 17 5.1 Reads .............................................................................................................. 17 5.2 Writes.............................................................................................................. 17 5.3 Output Disable .................................................................................................. 17 5.4 Standby ........................................................................................................... 17 5.5 Reset............................................................................................................... 18 Command Set .......................................................................................................... 19 6.1 Device Command Codes ..................................................................................... 19 6.2 Device Command Bus Cycles .............................................................................. 20 Read 7.1 7.2 7.3 7.4 7.5 Operation........................................................................................................ 22 Read Array Command ........................................................................................ 22 Read Identifier Command ................................................................................... 22 Read Query Command ....................................................................................... 23 Other ID Mode Data........................................................................................... 23 Query (CFI) Data .............................................................................................. 23 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Program Operations ................................................................................................ 24 8.1 Word Program .................................................................................................. 24 8.2 Bit Alterable Word Write Command ...................................................................... 25 8.3 Buffered Program Command ............................................................................... 25 8.4 Bit Alterable Buffer Write.................................................................................... 26 8.5 Bit Alterable Buffer Program ............................................................................... 26 8.6 Program Suspend .............................................................................................. 27 8.7 Program Resume............................................................................................... 27 8.8 Program Protection............................................................................................ 27 Erase ....................................................................................................................... 28 9.1 Block Erase ...................................................................................................... 28 9.2 Erase Suspend Command ................................................................................... 28 9.3 Erase Resume................................................................................................... 29 9.0 10.0 Security Mode .......................................................................................................... 30 10.1 Block Locking.................................................................................................... 30 10.2 Permanent One Time Programmable (OTP) Block Locking ....................................... 33 11.0 Registers ................................................................................................................. 36 11.1 Read Status Register ......................................................................................... 36 11.2 System Protection Registers ............................................................................... 37 12.0 Serial Peripheral Interface (SPI) ............................................................................. 40 12.1 SPI Overview .................................................................................................... 40 12.2 SPI Signal Names.............................................................................................. 40 12.3 SPI Memory Orginization .................................................................................... 41 July 2010 316144-07 Datasheet 3 Numonyx® Omneo™ P8P Datasheet 12.4 SPI Instruction ..................................................................................................43 13.0 Power and Reset Specification .................................................................................56 13.1 Power-Up and Power-Down .................................................................................56 13.2 Reset Specifications ...........................................................................................56 13.3 Power Supply Decoupling....................................................................................57 14.0 Max Ratings and Operating Conditions .....................................................................58 14.1 Absolute Maximum Ratings .................................................................................58 14.2 Operating Conditions..........................................................................................58 14.3 Endurance ........................................................................................................59 15.0 Electrical Specifications ...........................................................................................60 15.1 DC Current Characteristics ..................................................................................60 15.2 DC Voltage Characteristics ..................................................................................61 16.0 AC Characteristics ....................................................................................................62 16.1 AC Test Conditions.............................................................................................62 16.2 Capacitance ......................................................................................................62 16.3 AC Read Specifications .......................................................................................63 16.4 AC Write Specifications .......................................................................................65 16.5 SPI AC Specifications .........................................................................................68 17.0 Program and Erase Characteristics...........................................................................71 18.0 Ordering Information ...............................................................................................72 A Supplemental Reference Information .......................................................................73 A.1 Flow Charts.......................................................................................................73 A.2 Write State Machine ...........................................................................................80 A.3 Common Flash Interface .....................................................................................84 Datasheet 4 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Revision History Date December 14th, 2006 March, 2007 Revision 0 1 Description Initial Advance Information Datasheet Advance Information Datasheet Fixed the spelling error and deleted a repeated sentence on page 10 Added Section 2.3 “64-Ball EBGA Package” on page 12 Added Figure 1 “EBGA Mechanical Specifications” on page 12 Added Table 1 “EBGA Package Dimensions” on page 12 Added note 6 on page 67 Updated note 5 on page 68 Fixed an error on the A33 Device Code on page 93 “from 881E8 Hex, to 881E Hex” Applied Numonyx branding. Changed the Operating Temperature on the Title page as well as Table 19 Changed the Writing Endurance to 100,000 No Read while at Streaming Mode in Section 4.4 Changed the stand by current to 160usec in Section 7.2 Added note 5 in Table 19 footnotes Changed the read latency to 115nsec. Also, changed the values of R1 and R2 to 115nsec in Section 7.4 Removed Numonyx Confidential Removed Streaming Mode references Changed all A33 references to P8P Revised Easy BGA Package Dimensions (Table 4) Revised SPI Section (Ch-12) Changes Erase & Program Suspend Specification Changed P2 Specification Changed W250 non-streaming mode legacy programming Applied Numonyx DS formatting Added Numonyx® Omneo™ Branding Added Program on all 1’s command (D1h) to Table-20 Added Edurance table to operating conditions section Updated AC/DC Specifications: P3 (max), ICCS (typ), ICCS/ICCD/ICCES/ICCWS (typ), ICCR (typ/max), Capacitance (max), tCLQV (max), tHHQX (max), Buffer Program (typ/max), Block Erase (typ/max), Suspend Latency (max) Added -30 to +85C (Cover Page, Section 14) Added 32-Byte alignment Note to Program Operation (Section 8) Removed Storage Temp Range (Section 14) Revised AC Read Spec for -30 to +85C (Section 16.3) Revised SPI AC Spec for -30 to +85C (Section 16.5) Revised Ordering INformation (Section 18) July, 2007 2 April 2008 03 February 200906 04 July 2009 05 April 2010 06 July 2010 07 July 2010 316144-07 Datasheet 5 Numonyx® Omneo™ P8P Datasheet 1.0 1.1 Product Description Introduction Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the best attributes from other memory types in a new, highly scalable and flexible technology. Phase Change Memory (PCM) is a new type of nonvolatile semiconductor memory that stores information through a reversible structural phase change in a chalcogenide material. The material exhibits a change in material properties, both electrical and optical, when changed from the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the case of Phase Change Memory, information is stored via the change in resistance the chalcogenide material experiences upon undergoing a phase change. The material also changes optical properties after experiencing a phase change, a characteristic that has been successfully mastered for use in current rewritable optical storage devices such as rewritable CDs and DVDs. The PCM storage element consists of a thin film of chalcogenide contacted by a resistive heating element. In PCM, the phase change is induced in the memory cell by highly localized Joule heating caused by an induced current at the material junction. During a write operation, a small volume of the chalcogenide material is made to change phase. The phase change is a reversible process, and is modulated by the magnitude of injected current, the applied voltage, and the duration of the heating pulse. PCM combines the benefits of traditional floating gate flash, both NOR-type and NANDtype, with some of the key attributes of RAM and EEpROM. Like NOR flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM has the ability to write moderately fast. And like RAM and EEpROM, PCM supports bit alterable writes (overwrite). Unlike flash, no separate erase step is required to change information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile with data retention comparable NOR flash. However, at the current time, PCM technology appears to have a write cycling endurance better than that of NAND or NOR flash, but less than that of RAM. Unlike other proposed alternative memories, PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory storage element. Overall, the basic memory manufacturing process used to make PCM is less complex than that of NAND, NOR or DRAM. Historically, systems have adopted many different types of memory to meet different needs within a design. Some systems might include boot memory, configuration memory, data storage memory, high speed execution memory, and dynamic working memory. The demands of many of today’s designs require better performance from the memory subsystem and a reduction in the overall component count. PCM provides many of the attributes of different kinds of memory found in a typical design, enabling the opportunity to consolidate or eliminate of different types of memory. The combination of fast random access with high speed, bit alterable writes in a nonvolatile memory is a capability only offered in complex, low density technologies such as parallel EEpROM or battery-backed RAM. The PCM feature set is intended to facilitate easy evaluation and adoption in systems and to enable the consolidation of memory functions into a single device. In some cases, PCM may enable new usages or new solutions to existing problems, in a manner that is more efficient, higher performance and/or more cost effective. Datasheet 6 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 1.2 Product Overview The Numonyx® Omneo™ P8P PCM provides the convenience and ease of NOR flash emulation while providing a set of Super Set features that exploit the inherent capabilities of the PCM technology. The device emulates most of the features of the Numonyx™ Axcel™ Embedded Memory (P33). This is intended to ease the evaluation and design of Numonyx® Omneo™ P8P PCM into existing hardware and software development platforms. This basic features set is supplemented by the Super Set Features. The Super Set Features are intended to allow the designer to exploit the inherent capabilities of the phase change memory technology, and to enable the eventual simplification of hardware and software in the design. This section describes an overview of the features and capabilities of Numonyx® Omneo™ P8P PCM. • Density: Numonyx® Omneo™ P8P PCM product family begins with a 128-Mbit density. • Packages: Numonyx® Omneo™ P8P PCM devices are available in 64 Ball Easy BGA and 56 Lead TSOP packages. These are the same pinouts and packages as the existing P33 NOR flash devices. • Low Power: Designed for low voltage systems, Numonyx® Omneo™ P8P PCM supports read, write and erase operations at a core supply of 2.7V VCC. P8P offers additional power savings through standby mode. Standby mode is initiated when the system deselects the device by driving CE inactive, which significantly reduces power consumption. • NOR-Compatible Program and Emulated Erase Operation: Numonyx® Omneo™ P8P PCM provides a complete set of commands that are compatible with industry-standard command sequences used by NOR-type flash. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and write. Each emulated block erase operation results in the contents of the addressed block being written to all “1s” (ones). Data can be programmed in word or buffer increments. Erase-suspend allows system software to pause an erase command so it can read or program data in another block. Program suspend allows system software to pause programming so it can read from other locations within the device. The Status Register indicates when the WSM’s block erase, or program operation is finished. • Write Buffer: A 64 byte/32 word Write Buffer is also included to allow optimum write performance. By using the write buffer, data is overwritten or programmed in buffer increments. This feature improves system program performance more than 20 times over independent byte writes. • Command User Interface: As with floating gate flash, a Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. • Data Protection: Numonyx® Omneo™ P8P PCM block locking enables zerolatency block locking/unlocking and permanent locking. Permanent block locking provides enhanced security for boot code. The combination of these two locking features provides complete locking solution for code and data. • CFI Compliant: A flash-compatible Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows deviceindependent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. July 2010 316144-07 7 Numonyx® Omneo™ P8P Datasheet • Bit Alterability or Overwrite: PCM technology supports the ability to change each memory bit independently from 0 to 1 or 1 to 0 without an intervening block erase operation. Bit Alterability enables software to write to the non-volatile memory in a similar manner as writing to RAM or EEpROM without the overhead of erasing blocks prior to write. Bit Alterable writes use similar command sequences as word programming and Buffer Programming. • Serial Peripheral Interface (SPI): SPI allows for in-system programming through a minimal pin count interface. This interface is provided in addition to a traditional parallel system interface. This feature has been added to facilitate the on-board, in-system programming of code into the Numonyx® Omneo™ P8P PCM device, after it has been soldered to a circuit board. Pre-programming of code prior to high temperature board attach is not recommended with the P8P device. Although the device reliability across the operating temperature range is typically superior to that of floating gate flash, the P8P device may be subject to thermallyactivated disturbs at higher temperatures. However, no permanent device damage occurs during either leaded and lead-free board attach. Datasheet 8 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 1.3 Memory Map This section cover the memory map for the Top and Bottom boot devices Table 1: Top Parameter Memory Map Programming Region Number Size (KW) 16 16 16 7 16 64 … Blk 130 129 128 127 126 … 128-Mbit 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF … 700000-70FFFF 6F0000-6FFFFF … 600000-60FFFF 5F0000-5FFFFF … 500000-50FFFF 4F0000-4FFFFF … 400000-40FFFF 3F0000-3FFFFF … 300000-30FFFF 2F0000-2FFFFF … 200000-20FFFF 1F0000-1FFFFF … 100000-10FFFF 0F0000-0FFFFF … 000000-00FFFF 64 64 6 … 112 111 … 96 95 … 80 79 … 64 63 … 48 47 … 32 31 … 16 15 … 0 64 64 5 … 64 64 4 … 64 64 3 … 64 64 2 … 64 64 1 … 64 64 0 … 64 July 2010 316144-07 9 Numonyx® Omneo™ P8P Datasheet Table 2: Bottom Parameter Memory Map Programming Region Number Size (KW) 64 7 … Blk 130 … 128-Mbit 7F0000-7FFFFF … 700000-70FFFF 6F0000-6FFFFF … 600000-60FFFF 5F0000-5FFFFF … 500000-50FFFF 4F0000-4FFFFF … 400000-40FFFF 3F0000-3FFFFF … 300000-30FFFF 2F0000-2FFFFF … 200000-20FFFF 1F0000-1FFFFF … 100000-10FFFF 0F0000-0FFFFF … 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF 64 64 6 … 115 114 … 99 98 … 83 82 … 67 66 … 51 50 … 35 34 … 19 18 … 4 3 2 1 0 64 64 5 … 64 64 4 … 64 64 3 … 64 64 2 … 64 64 1 … 64 64 … 64 0 16 16 16 16 Datasheet 10 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 2.0 Package Information This section covers the mechanical specification for the available packages. 2.1 Figure 1: 56-Lead TSOP TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Note 2 A2 e E See Detail B Y D1 D A1 Seating Plane See Detail A A Detail A Detail B C 0 b L Table 3: TSOP Package Dimensions (Sheet 1 of 2) Millimeters Inches Notes Min Nom 0.995 0.150 0.150 18.400 14.000 Max 1.200 1.025 0.200 0.200 18.600 14.200 Min 0.002 0.038 0.004 0.004 0.717 0.543 Nom 0.039 0.006 0.006 0.724 0.551 Max 0.047 0.040 0.008 0.008 0.732 0.559 0.050 0.965 0.100 0.100 18.200 13.800 Symbol A A1 A2 b c D1 E Product Information Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width July 2010 316144-07 11 Numonyx® Omneo™ P8P Datasheet Table 3: TSOP Package Dimensions (Sheet 2 of 2) Millimeters Inches Notes Min Nom 0.500 20.00 0.600 56 3° 0.250 Max 20.200 0.700 5° 0.100 0.350 Min 0.780 0.020 0° 0.006 Nom 0.0197 0.787 0.024 56 3° 0.010 Max 0.795 0.028 5° 0.004 0.014 19.800 0.500 0° 0.150 Symbol e D L N θ Y Z Product Information Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset Notes: 1. 2. 3. 4. One dimple on package denotes Pin 1. If two dimples, then the larger dimple denotes Pin 1. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. Daisy Chain Evaluation Unit information is at Numonyx® Omneo™ P8P PCM Memory Packaging Technology 2.2 Figure 2: Ball A1 Corner 64-Ball Easy BGA Package Easy BGA Mechanical Specifications Ball A1 Corner S1 D 1 A B C D E E F G H 2 3 4 5 6 7 8 A B C D E F G 8 7 6 5 4 3 2 1 S2 b e H Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Plane Y Note: Drawing not to scale Datasheet 12 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Table 4: Easy BGA Package Dimensions Millimeters Symbol Min Nom 0.78 0.43 10.00 8.00 1.00 64 1.50 0.50 Max 1.20 0.53 10.10 8.10 0.10 1.60 0.51 A A1 A2 b D E e N Y S1 S2 0.25 0.33 9.90 7.90 1.40 0.49 Notes Product Information Package Height (128-Mbit) Ball Height Package Body Thickness (128-Mbit) Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Notes: 1. Daisy Chain Evaluation Unit information is at Numonyx® Omneo™ P8P PCM Memory Packaging Technology July 2010 316144-07 13 Numonyx® Omneo™ P8P Datasheet 3.0 Figure 3: Pinouts and Ballouts 56-Lead TSOP Pinout (128-Mbit) A16 A15 A14 A13 A12 A11 A10 A9 A23 A22 A21 VSS VCC WE# WP# A20 A19 A18 A8 A7 A6 A5 A4 A3 A2 NC SERIAL VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Lead TSOP Pinout 14 mm x 20 mm Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Q A17 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 D C RST# VPP DQ11 DQ3 DQ10 DQ2 VCCQ DQ9 DQ1 DQ8 DQ0 VCC OE#/HOLD# VSS CE#/S# A1 Notes: 1. A1 is the least significant address bit to be compatible with x8 addressing systems. Even though Numonyx® Omneo™ P8P PCM is a 16 bit data bus. 2. A23 is valid for 128-Mbit densities and above. Datasheet 14 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Figure 4: 64-Ball Easy BGA Ballout (128-Mbit) 1 A A1 B A2 C A3 D A4 E D8 F 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A6 A8 Vpp A13 Vcc A18 A22 A22 A18 Vcc A13 Vpp A8 A6 A1 B Vss A9 CE#/S# A14 RFU A19 RFU RFU A19 RFU A14 CE#/S# A9 Vss A2 C A7 A10 A12 A15 WP# A20 A21 A21 A20 WP# A15 A12 A10 A7 A3 D A5 A11 RST# Vccq Vccq A16 A17 A17 A16 Vccq Vccq RST# A11 A5 A4 E D1 D9 D3 D4 C D15 RFU OE#/ HOLD# RFU D15 OE#/ HOLD# C D4 D3 D9 D1 D8 F SERIAL D0 G A23 RFU H D10 D11 D12 D Q Q D D12 D11 D10 D0 SERIAL G D2 Vccq D5 D6 D14 WE# WE# D14 D6 D5 Vccq D2 RFU A23 H RFU Vssq Vcc Vss D13 Vssq D7 RFU RFU D7 Vssq D13 Vss Vcc Vssq RFU Easy BGA Top View- Ball side down Easy BGA Bottom View- Ball side up Notes: 1. A1 is the least significant address bit to be compatible with x8 addressing systems, even though Numonyx® Omneo™ P8P PCM is a 16 bit data bus. 2. A23 is valid for 128-Mbit densities July 2010 316144-07 15 Numonyx® Omneo™ P8P Datasheet 4.0 Table 5: Symbol A[MAX:1] Signals Ball/Pin Descriptions Type Input Input/ Output Input Name and Function ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1] Note: that the address bus for TSOP and Easy BGA starts at A1. Numonyx® Omneo™ P8P PCM uses x16 addressing. The package is x8 addressing to be compatible with J3 or P30 products. DATA INPUT/OUTPUTS: Inputs data and commands during writes (internally latched). Outputs data during read operations. Data signals float when CE# or OE# are VIH. or RST# is VIL. CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#high deselects the device, places it in standby state, and places data outputs at high-Z. SPI Select: S# low activates command writes to the SPI interface. Rising S# to VIH completes (or terminates) the SPI command cycle; it also sets Q to high-Z. OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle. With OE# at VIH, device data outputs are placed in high-Z state. SPI HOLD#: When asserted, suspends the current cycle and sets Q to high-Z until de-asserted. RESET CHIP: When low, RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. The device is in 8-Word page mode array read after reset exits. WRITE ENABLE: controls Command User Interface (CUI) and array writes. Its rising edge latches addresses and data. WRITE PROTECT: Disables/enables the lock-down function. When WP# is VIL, the lock-down mechanism is enabled and software cannot unlock blocks marked lock-down. When WP# is VIH, the lock-down mechanism is disabled and blocks previously locked-down are now locked; software can unlock and lock them. After WP# goes low, blocks previously marked lockdown revert to that state. SPI Clock: Synchronization clock for input and output data SPI Data Input: Serial data input for Op Codes, address and program data bytes. Input data is clocked in on the rising edge of C, starting with the MSB. SPI Data Output: Serial data output for read data. Output data is clocked out, triggered by the falling edge of C, starting with the MSB. SPI Enable: SERIAL is a port select switching between the normal parallel or serial interface. When Vss, the normal (non-SPI) Numonyx® Omneo™ P8P PCM interface is enabled; all other SPI inputs are Don't Care, and Q is at High-Z. When Vcc, SPI mode is enabled, all non-SPI inputs are Don't Care, and all outputs are at High-Z. This pin has an internal weak pull down resistor to select the normal parallel interface when users leave the pin floating. A CAM can be used to permanently disable this feature. ERASE AND WRITE POWER: A valid VPP voltage allows erase or programming. Memory contents can’t be altered when VPP ≤ VPPLK. Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, VPP’s VIH level can be as low as VPPLMIN. Program/erase voltage is normally 1.7 V–3.6 V. DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC voltages should not be attempted. OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to VCC if VCCQ is to function within the VCC range. GROUND: connects device circuitry to system ground. I/O GROUND: Tie to GND NO CONNECT: No internal connection; can be driven or floated. DON’T USE: Don’t connect to power supply or other signals. RESERVED FOR FUTURE USE: Don’t connect to other signals. DQ[15:0] CE# or S# SPI OE# or HOLD# Input SPI Input RST# WE# Input WP# Input C D Q SPI SPI SPI SERIAL SPI VPP Pwr VCC VCCQ VSS VSSQ NC DU RFU Pwr Pwr Pwr Pwr Datasheet 16 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 5.0 Bus Operations CE# at VIL and RST# at VIH enables device read operations. Addresses are always assumed to be valid. OE#-low activates the outputs and gates selected data onto the I/ O bus. WE#-low enables device write operations. When the VPP voltage ≤ VPPLK (lockout voltage), only read operations are enabled. Table 6: Bus Operations State RST# VIH VIH VIH VIH VIL VIH CE# VIL VIL VIL VIH X VIL OE# VIL VIL VIH X X VIH WE# VIH VIH VIH X X VIL DQ[15:0] DOUT DOUT High-Z High-Z High-Z DIN 2 2 1 Note Read (Main Array) Read (Status, Query, Identifier) Output Disable Standby Reset Write Notes: 1. See Table 8, “Command Sequences in x16 Bus Mode” on page 20 for valid DIN during a write operation. 2. X = Don’t care (L or H) 3. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#. 5.1 Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 7, “Command Codes and Descriptions” on page 19 shows the bus cycle sequence for each of the supported device commands, while Table 8, “Command Sequences in x16 Bus Mode” on page 20 describes each command. See Section 16.0, “AC Characteristics” on page 62 for signal-timing details. Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted. 5.3 Output Disable When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a highimpedance (High-Z) state, WAIT is also placed in High-Z. 5.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby, average current is measured over the same time interval 5 μs after CE# is deasserted. July 2010 316144-07 17 Numonyx® Omneo™ P8P Datasheet When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 5.5 Reset As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array mode, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 16.0, “AC Characteristics” on page 62 for details about signal-timing. Datasheet 18 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 6.0 6.1 Command Set Device Command Codes The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. Table 7: Mode Code FFh 70h 90h 98h Command Codes and Descriptions Device Mode Read Array Read Status Register Read ID Code Read Query Clear Status Register Description Places device in read array mode so that data signals output array data on DQ[15:0]. Places the device in Status Register read mode. Status data is output on DQ[7:0]. The device automatically enters this mode after a program or erase command is issued to it. Puts the device in read identifier mode. Device reads from the addresses output manufacturer/ device codes, block lock status, or protection register data on DQ[15:0]. Puts the device in read query mode. Device reads from the address given outputting the Common Flash Interface information on DQ[7:0] The WSM can set the Status Register’s block lock (SR.1), VPP (SR.3), program (SR.4), and erase (SR.5) status bits to “1” but cannot clear them. Device reset or the Clear Status Register command at any device address clears those bits to “0.” This preferred program command’s first cycle prepares the CUI for a program operation. The second cycle latches address and data and executes the WSM Program algorithm at this location. Status Register updates occur when CE# or OE# is toggled. A Read Array command is required to read array data after programming. Equivalent to a Program Set-Up command (40h). The command sequence is the same as Word Program (40h). The difference is the state of the PCM memory cell can change from a 0 to 1 or 1 to 0, unlike a flash memory cell, which can only change from 1 to 0 during programming. This command loads a variable number of bytes up to the buffer size 32 words onto the program buffer. This command sequence is the similar to Buffered Program, but the buffer write command is bit alterable or overwrite operation. The command sequence is the same as E8h. This command is the same as Buffered Program, but user indicates that the pagee is already set to all 1s. The command sequence is the same as E8h The confirm command is issued after the data streaming for writing into the buffer is done. This initiates the WSM to carry out the buffered programing algorithm. Prepares the CUI for Block Erase. The device emulates erasure of the block addressed by the Erase Confirm command by writing all ones. If the next command is not Erase Confirm, the CUI (a) sets Status Register bits SR.4 and SR.5 to “1,” (b) places the device in the read Status Register mode, and (c) waits for another command. If the first command was Erase Set-Up (20h), the CUI latches address and data then emulates erasure of the block indicated by the Erase confirm cycle address. This command issued at any device address initiates suspension of the currently executing program/erase operation. The Status Register, invoked by a Read Status Register command, indicates successful suspend operation by setting (1) status bits SR.2 (write suspend) or SR.6 (erase suspend) and SR.7. The WSM remains in the Suspend mode regardless of the control signal states, except RST# = VIL. This command issued at any device address resumes suspended program or erase operation. Read 50h 40h Program Set-Up Alt Set-up Bit Alterable Write Buffered Program Bit Alterable Buffered Write Buffer Program on all 1s Buffered Write Confirm 10h 42h Program E8h EAh DEh D0h Erase 20h Block Erase Set-Up D0h Erase Confirm Suspend B0h Write or Erase Suspend D0h Suspend Resume July 2010 316144-07 19 Numonyx® Omneo™ P8P Datasheet Table 7: Mode Code 60h Block Locking 01h D0h 2Fh Command Codes and Descriptions Device Mode Lock Set-Up Lock Block Unlock Block Lock-Down Protection Program Set-Up Description Prepares the CUI for lock configuration. If the next command is not Block-Lock, Unlock, or LockDown the CUI sets SR.4 and SR.5 to indicate command sequence error. If the previous command was Lock Set-Up (60h), the CUI locks the addressed block. After a Lock Set-Up (60h) command the CUI latches the address and unlocks the addressed block. After a Lock Set-Up (60h) command, the CUI latches the address and locks-down the addressed block. Prepares the CUI for a protection register program operation. The second cycle latches address, data, and starts the WSM’s protection register program or lock algorithm. Toggling CE# or OE# updates the PCM Status Register data. To read array data after programming issue a Read Array command. Protection Note: C0h Don’t use unassigned (reserved) commands 6.2 Device Command Bus Cycles Device operations are initiated by writing specific device commands to the Command User Interface (CUI). Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command Table 8: Mode Command Sequences in x16 Bus Mode Command Read Array/Reset Read Device Identifiers Bus Cycles 1 ≥2 ≥2 2 1 2 2 >2 >2 >2 2 1 1 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(1) DnA DnA DnA BA X WA WA WA WA WA BA X X Data(2) FFh 90h 98h 70h 50h 40h or 10h 42h E8h EAh DEh 20h B0h D0h Second Bus Cycle Oper Read Read Read Write Write Write Write Write Write Addr(1) DBA+IA DBA+QA BA WA PA WA WA WA BA Data(2) ID QD SRD WD PD N-1 N-1 N-1 D0h - Read Read Query Read Status Register Clear Status Register Program Bit Alterable Program Program Buffered Program (3) Bit Alterable Buffered Program(3) Buffered Program on all 1s Erase Suspend Block Erase Program/Erase Suspend Program/Erase Resume Datasheet 20 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Table 8: Mode Command Sequences in x16 Bus Mode Command Lock Block Bus Cycles 2 2 2 2 2 First Bus Cycle Oper Write Write Write Write Write Addr(1) BA BA BA PA LPA Data(2) 60h 60h 60h C0h C0h Second Bus Cycle Oper Write Write Write Write Write Addr(1) BA BA BA PA LPA Data(2) 01h D0h 2Fh PD FFFDh Block Lock Unlock Block Lock-down Block Protection Protection Program Lock Protection Program Notes: 1. First command cycle address should be the same as the operation’s target address. X = Any valid address within the device. IA = Identification code address. BA = Address within the block. LPA = Lock Protection Address (from the CFI). P8P LPA is at 0080h. PA = 4-word protection address in the user programmable area of device identification plane. DnA = Address within the device. DBA = Device Base Address. (A[MAX:1]=0h) PRA = Program Region QA = Query code address. WA = Word address of memory location to be written. 2. SRD = Data read from the status register. WD = Data to be written at location WA. ID = Identifier code data. PD =User programmable protection data. QD = Query code data on DQ[7:0]. N = Data count to be loaded into the device to indicate how many words would be written into the buffer. Because the internal registers count from 0, the user writes N-1 to load N words. 3. The second cycle of the Buffered Program command, which is the count being loaded into the buffer is followed by data streaming up to 32 words and then a confirm command is issued which triggers the programming operation. Refer to the Appendix B, “Buffered Program Flowchart”. July 2010 316144-07 21 Numonyx® Omneo™ P8P Datasheet 7.0 Read Operation Numonyx® Omneo™ P8P PCM has several read modes: read array, read device identifier codes, read query (CFI codes) and read Status Register. P8P read modes are: • Read array mode: read returns PCM array data from the addressed locations. • Read identifier mode: reads returns manufacturer device identifier data, block lock status, and protection register data. • Read query mode: read returns device CFI (or query) data. • Read Status Register mode: read returns the device Status Register data. A system processor can check the Status Register to determine the device’s state or monitor program or erase progress. 7.1 Read Array Command The Read Array command places (or resets) the device to read array mode. Upon initial device power-up or after reset (RST# transitions from VIL to VIH), the device defaults to read array mode. If an Erase- or Program-Suspend command suspends the WSM, a subsequent Read Array command will place the device in read array mode. The Read Array command functions independently of VPP voltage. 7.2 Read Identifier Command The read identifier mode is used to access the manufacturer/device identifier, block lock status, and protection register codes. The identifier space occupies the address range supplied by the Read Identifier command (90h) address. Table 9: Read Identifier Table Item Address(1,2) DBA + 000000h DBA + 000001h Data Manufacturer Code Device Code Block Lock Configuration • Block Is Unlocked • Block Is Locked • Block Is not Locked-Down • Block Is Locked-Down • Reserved for Future Use(3) 0089h ID (see Table 10) Lock DQ0 = 0 BBA + 000002h DQ0 = 1 DQ1 = 0 DQ1 = 1 DQ[7:2] DBA + 000080h DBA + 000081h–000084h DBA + 000085h–000088h DBA + 000089h DBA + 00008Ah–0000109h PR-LK0 Protection Register Data Protection Register Data Protection Register Data PR-LK1 Lock Protection Register 0 64-bit Factory-Programmable Protection Register 64-bit User-Programmable Protection Register Lock Protection Register 1 16x128 bit User-Programmable Protection Registers Notes: 1. DBA = Device Base Address. (A[MAX:18] = DBA). Numonyx reserves other configuration address locations. 2. BBA = Block Base Address. 3. DQ[7:2] are invalid and should be ignored. Datasheet 22 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Table 10: Device ID Table Device Code (Byte/Word) Device Hex High Byte 128 Mb 128 Mb 881E 8821 10001000 10001000 Low Byte 00011110 00100001 Top Boot Bottom Boot Binary Mode 7.3 Read Query Command The Query space comes to the foreground and occupies the device address range supplied by the Read Query command address. The mode outputs Common Flash Interface (CFI) data when the device addresses are read. Appendix A, “Common Flash Interface” on page 84 shows the query mode information and addresses. Write the Read Array command to return to read array mode. The read performance of this CFI data follows the same timings as the main array. 7.4 Other ID Mode Data Other ID mode data besides the Protection registers (such as block locking information and the device JEDEC ID) may be accessed as long as there are no ongoing write or erase operations. 7.5 Query (CFI) Data Query data is read by sending the Read Query command to the device. Reading the Query data is subject to the same restrictions as reading the Protection Registers. July 2010 316144-07 23 Numonyx® Omneo™ P8P Datasheet 8.0 Program Operations There are five kinds of write operations available in Numonyx® Omneo™ P8P PCM. • Word Program (40h, or 10h) • Bit Alterable Word Write (42h) • Buffered Program (E8h) • Bit Alterable Buffered Write (EAh) • Buffered Program on all 1’s (DEh) Writing a program command to the device initiates internally timed sequences that write the requested word. Note: All program operations must stay with in 32-byte page. Writing must be aligned to a 32-byte page boundry (ex: 0x0, 0x8, 0x10, 0x18, 0x20, etc.). All addresses must lie within the starting address plus the buffer size. All transmitted data that goes beyond the 32-byte page boundry are not guaranteed. The WSM executes a sequence of internally timed events to write desired bits at the addressed location and verify that the bits are sufficiently written. For Word Programming the memory changes specifically addressed bits to “0”. “1” bits do not change the memory cell contents. This allows individual data-bits to be programmed (“0”) while “1” bits serve as data masks. For Bit Alterable Word Write, the memory cell can change from “0” to “1” or “1” to a “0”. The Status Register can be examined for write progress and errors by reading any address within the device during a write operation. Issuing a Read Status Register command brings the Status Register to the foreground allowing write progress to be monitored or detected at other device addresses. Status Register bit SR.7 indicates device write status while the write sequence executes. CE# or OE# toggle (during polling) updates the Status Register. Valid commands that can be issued to the writing device during write are Read Status Register, Write Suspend, Read Identifier, Read Query, and Read Array. However Read Array will return unknown data while the device is busy. When writing completes, Status Register bit SR.4 indicates write success if zero (0) or failure if set (1). If SR.3 is set (1), the WSM couldn’t execute the write command because VPP was outside acceptable limits. If SR.1 is set (1), the write operation targeted a locked block and was aborted. Attempting to write in an erase suspended block will result in failure and SR.4 will be set (1). After examining the Status Register, it should be cleared by the Clear Status Register command before issuing a new command. The device remains in Status Register mode until another command is written to that device. Any command can follow once writing completes. 8.1 Word Program The system processor writes the Word Program Setup command (40h/10h) to the device followed by a second write that specifies the address and data to be programmed. The device accessed during both of the command cycles automatically outputs Status Register data when the device address is read. The device accessed during the second cycle (the data cycle) of the program command sequence will be where the data is programmed. See Section 32, “Buffer Program or Bit Alterable Buffer Write Flowchart” on page 75. Datasheet 24 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet When VPP is greater than VPPLK, program-and erase-currents are drawn through the VCC input. If VPP is driven by a logic signal, VPP must remain above VPPMIN to perform in-system PCM modifications. Figure 5, “Example VPP Power Supply Configuration” on page 27 shows PCM power supply usage in various configurations. 8.2 Bit Alterable Word Write Command The Bit Alterable Word Write Command executes just like Word Program Command (40h/10h), using a two-write command sequence. The Bit Alterable Write Setup command (42h) is written to the CUI followed by the specific address and data to be written. The WSM will start executing the programming algorithm, but the data written to CUI will be directly overwritten into the PCM memory unlike flash memory, which can only be written from 1 to 0 without a prior erase of the entire block. See Table 12, “Bit Alterability vs. Flash Bit-Masking” on page 26. This overwrite function eliminates Flash Bit Masking, which means software cannot use a “1” in a data mask to produce no change of the memory cell, as might occur with floating gate flash. 8.3 Buffered Program Command A Buffered Program command sequence initiates the loading of a variable number of words, up to the buffer size (32 words), into the program buffer and after that into the PCM device. First, the Buffered Program setup command is issued along with the Block Address (Section 32, “Buffer Program or Bit Alterable Buffer Write Flowchart” on page 75). When Status Register bit 7 is set to 1, the buffer is ready for loading. Now a word count is given to the part with the Block Address. On the next write, a device starting address is given along with the Program Buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the starting address plus the buffer size. Maximum programming performance and lower power are obtained by aligning the starting address at the beginning of a 32 word boundary. A misaligned starting address is not allowed and will result in invalid data. After the final buffer data is given, a Program Buffer Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the PCM array. If a command other than Buffered Program Confirm command (D0h) is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another Program Buffer Setup command and check SR.7. If an error occurs while writing, the device will stop writing, and Status Register bit SR.4 will be set to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. If a program error is detected, the Status Register should be cleared by the user before issuing the next program command. Additionally, if the user attempts to program past the block boundary with a Program Buffer command, the device will abort the Program Buffer operation. This will generate an “Invalid Command/Sequence” error and Status Register bits SR.5 and SR.4 will be set to a “1. All bus cycles in the buffered programming sequence should be addressed to the same block. If a buffered programming is attempted while the VPP ≤ VPPLK, Status Register bits SR.4 and SR.3 will be set to “1”. Buffered write attempts with invalid VCC and VPP voltages produce spurious results and should not be attempted. Buffered program operations with VIH < RST# < VHH may produce spurious results and should not be attempted. July 2010 316144-07 25 Numonyx® Omneo™ P8P Datasheet Successful programming requires that the addressed block’s locking status to be cleared. If the block is locked down, then the WP# pin must be raised high and then the block could be unlocked to execute a program operation. An attempt to program a locked block results in setting of SR.4 and SR.1 to a ‘1’ (i.e. “Error in Programming”). 8.4 Bit Alterable Buffer Write The Bit Alterable Buffer Write command sequence is the same as for Buffer Program. For command sequence see Section 8.3, “Buffered Program Command” on page 25. The primary difference between the two Buffer commands is when the Write State Machine starts executing, the data written to the buffer will be directly overwritten into the PCM memory, unlike Flash Memory, which can only go from “1” to “0” before an erase of the entire block. See Table 12, “Bit Alterability vs. Flash Bit-Masking” on page 26. This overwrite function eliminates Flash Bit Masking, which means software cannot use a “1” in a data mask for no change of the memory cell, as might occur with floating gate flash. The advantage of Bit Alterability is no block erase is needed prior to writing a block, which minimizes system overhead for software management of data, and ultimately improves latency, determinism, and reduces power consumption because of reduction of system overhead. Storing of counter variables can easily be handled by using PCM memory because a “0” can change to a “1” or a “1” can change to a “0”. Table 11: Buffered Programming and Bit Alterable Buffer Write Timing Requirements Alignment 32-word/64-byte Aligned Programming Time tPROG/PB Example Start Address = 1FFF10h; End Address = 1FFF2Fh Table 12: Bit Alterability vs. Flash Bit-Masking Programming Function Flash Bit-Masking Command Issued 40h or E8h 40h or E8h 40h or E8h 40h or E8h 42h or EAh 42h or EAh 42h or EAh 42h or EAh Memory Cell Current State 0 0 1 1 0 0 1 1 Data From User 0 1 0 1 0 1 0 1 Memory Cell After Programming 0 0 0 1 0 1 0 1 8.5 Bit Alterability Datasheet 26 Bit Alterable Buffer Program This mode is sometimes referred to as PreSET Buffered Program. ‘Program on all 1s’ is similar to program mode (“1”s treated as masks; “0”s written to cells) with the assumption that all the locations in the addressed page have previously been SET (“1”s). [Performance of Buffer Program on All 1s expected to be better than buffered program mode because the pre-read step before programming is eliminated.] The command sequence for Buffered Program on all 1s is the same as Buffered Program Command (E8h). July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 8.6 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device address. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation. When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The device continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. To read data from the device, the Read Array command must be issued. Read Array, Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid commands during a program suspend. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset. 8.7 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any address. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted. 8.8 Program Protection Holding the VPP input at VIL provides absolute hardware write protection for all PCMdevice blocks. If VPP is below VPPLK, write or erase operations halt and an error is posted in Status Register bit SR.3. The block lock registers are not affected by the VPP level; they may be modified and read even if VPP is below VPPLK. Figure 5: Example VPP Power Supply Configuration 1 System supply VPP ≤ 10K Ω 2 VCC VPP System supply Prot# (logic signal ) VCC VPP • VPP supply during factory programming • Complete Write/Erase protection with VPP ≤ VPPLK • Low-voltage programming • Absolute write protection via logic signal 3 System supply 4 VCC VPP System supply VCC VPP VPP • Low Voltage and VPP Factory Programming • Low-voltage programming VPPSUPPLY .EMF July 2010 316144-07 27 Numonyx® Omneo™ P8P Datasheet 9.0 Erase Unlike floating gate flash, PCM does not require a high voltage block erase operation to change all the bits in a block to “1.” As a bit alterable technology, each bit is capable of independently being changed from a “0” to a “1” and from a “1” to a “0”. With floating gate flash, a high voltage potential must be placed in parallel upon a group of bits called an erase block. Each bit within the block may be changed independently from “1” to a “0”, but only may be changed from a “1” to a “0” through a grouped erase operation. To maintain compatibility with legacy flash system software, Numonyx® Omneo™ P8P PCM mimics or emulates a flash erase by writing each bit within a block to “1”, thereby emulating flash-style erase. 9.1 Block Erase The system processor writes the Erase Setup command (20h) to the device followed by a second Confirm (D0h) command write that specifies the address of the block to be erased. The device during both of the command cycles automatically outputs Status Register data when the device address is read. See Section 33, “Block Erase Flowchart” on page 76. After writing the command, the device automatically enters read status mode. The device Status Register bit SR.7 will be set (“1”) when the erase completes. If the erase fails, Status Register bit SR.5 will be set (“1”). SR.3 = “1” indicates an invalid VPP voltage. SR.1 = “1” indicates an erase operation was attempted on a locked block. CE# or OE# toggle (during polling) updates the Status Register. If an error bit is set, the Status Register can be cleared by issuing the Clear Status Register command before attempting the next operation. The device will remain in Status Register mode until another command is written to the device. Any command can follow once erase completes. Only one block can be in erase mode at a time. 9.2 Erase Suspend Command The Write/Erase Suspend command halts an in-progress write or erase operation. The command can be issued at any device address. The Suspend command allows data to be accessed from memory locations other than the one block being written or the block being erased. A Write operation can be suspended to perform reads only at any location except the address being programmed. An Erase operation can be suspended to perform either a write or a read operation within any block except the block that is erase suspended. A Write command nested within a suspended Erase can subsequently be suspended to read yet another location. Once the write/erase process starts, the Suspend command requests that the WSM suspend the write/erase sequence at predetermined points in the algorithm. An operation is suspended when status bits SR.7 and SR.6 and/or SR.2 display “1.” tSUSP/P/tSUSP/E specifies suspend latency. To read data from other blocks within the device (other than an erase-suspended block), a Read Array command can be written. During Erase Suspend, a Write command can be issued to a block other than the erase-suspended block. Block erase cannot resume until write operations initiated during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read Query, and Write Resume are valid commands during Write or Erase Suspend. Additionally, Clear Status Register, Program, Write Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block are valid commands during Erase Suspend. Datasheet 28 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet During a suspend, CE# = VIH places the device in standby state, which reduces supply current. VPP must remain at its program level and WP# must remain unchanged while in suspend mode. The Resume (D0h) command instructs the WSM to continue writing/erasing and automatically clears Status Register bits SR.2 (or SR.6) and SR.7. If Status Register error bits are set, the Status Register can be cleared before issuing the next instruction. RST# must remain at VIH. See Section 31, “Write Suspend/Resume Flowchart” on page 74 and Section 34, “Erase Suspend/Resume Flowchart” on page 77. If software compatibility with the Numonyx™ P33 device is desired, a minimum tERS/SUSP time (See Section 17.0, “Program and Erase Characteristics” on page 71) should elapse between an Erase command and a subsequent Erase Suspend command to ensure that the device achieves sufficient cumulative erase time. Occasional Erase-to-Suspend interrupts do not cause problems, but out-of-spec Erase-to-Suspend commands issued too frequently to a P33 device may produce uncertain results. However, this specification is not required for this PCM device. 9.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any address. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 31, “Write Suspend/Resume Flowchart” on page 74). July 2010 316144-07 29 Numonyx® Omneo™ P8P Datasheet 10.0 Security Mode The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 10.1 Block Locking There are two types of block locking on Numonyx® Omneo™ P8P PCM: • Zero Latency Block Locking • Selectable One Time Programmable (OTP) Block Locking This type of locking allows for permanent locking of the parameter blocks and 3 main blocks. 10.1.1 Zero Latency Block Locking Individual instant block locking protects code and data. It allows software to control block locking or it can require hardware interaction before locking can be changed. Any block can be locked or unlocked with no latency. Locked blocks cannot be written or erased; they can only be read. Write or erase operations to a locked block returns a Status Register bit SR.1 error. The following sections discuss the locking operations. State [WP#, LAT1, LAT0] specifies lock states (WP# = WP# state, LAT1= internal Block Lock Down latch status, LAT0 = internal Block Lock latch status). Figure 6, “Block Locking State Diagram” on page 33 defines possible locking states. The following summarizes the locking functionality. • All blocks power-up in the locked state. Then Unlock and Lock commands can unlock or lock them • The Lock-Down command locks and prevents a block from being unlocked when WP# = VIL WP# = VIH overrides lock-down so commands can unlock/lock blocks If a previously locked-down block is given a Lock/Unlock/Lock-Down command and WP# returns to VIL then those blocks will return to lock-down Lock-Down is cleared only when the device is reset or powered-down. The block lock registers are not affected by the VPP level; they may be modified and read even if VPP is below VPPLK. The following sections describe how to lock, unlock, and lock-down a block. Table 14 on page 32 shows the state table for the locking functions. See also Section 35, “Locking Operations Flowchart” on page 78. 10.1.2 Lock Block All blocks default power-up or reset state is locked (states [001] or [101]) to fully protect it from alteration. Write or erase operations to a locked block return a Status Register bit SR.1 error. The Lock Block command sequence can lock an unlocked block. Table 13: Block Locking Truth Table VPP X ≤ VPPLK WP# X VIL RST# VIL VIH Block Write Protection All blocks write/erase protected All blocks write/erase protected Block Lock Bits Block lock bits may not be changed Lock-Down block states may not be changed Datasheet 30 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Table 13: Block Locking Truth Table VPP ≤ VPPLK > VPPLK > VPPLK WP# VIH VIL VIH RST# VIH VIH VIH Block Write Protection All blocks write/erase protected All Lock-Down and Locked blocks write/erase protected All Lock-Down and Locked blocks write/erase protected Block Lock Bits All Lock-Down block states may be changed Lock-Down block states may not be changed All Lock-Down block states may be changed 10.1.3 Unlock Block The Unlock Block command unlocks locked blocks (if block isn’t locked-down) so they can be programmed or erased. Unlocked blocks return to the locked state at device reset or power-down. 10.1.4 Lock-Down Block Locked-down blocks (state 3 or [011]) are protected from write and erase operations (just like locked blocks), but software commands alone cannot change their protection state. When WP# is VIH, the lock-down function is disabled (state 7 or [111]), and an Unlock command (60h/D0h) must be issued to unlocked locked-down block (state 6 or [110]), prior to modifying data in these blocks. To return an unlocked block to lockeddown state, a Lock command (60h/01h) must be issued prior to changing WP# to VIL (state 7 or [111] and then state 3 or [011]). A locked or unlocked block can be lockeddown by writing the Lock-Down Block command sequence. Locked-down blocks revert to the locked state at device reset or power-down. 10.1.5 WP# Lock-Down Control WP# = VIH overrides the block lock-down. See Table 13, “Block Locking Truth Table” on page 30. The WP# signal controls the lock-down function. WP# = 0 protects lock-down blocks [011] from write, erase, and lock status changes. When WP# = 1, the lockdown function is disabled [111] and a software command can individually unlock locked-down blocks [110] so they can be erased and written. When the lock-down function is disabled, locked-down blocks remain locked, and must first be unlocked by writing the Unlock command prior to modifying data in these blocks. These blocks can then be re-locked [111] and unlocked [110] while WP# remains high. When WP# goes low, blocks in re-locked state [111] returns to locked-down state [011]. However, WP# going low changes blocks at unlocked state [110] to [010] or “virtual lock-down” state. When the lock status of a “virtual lock-down” blocks is read, it appears to be a “locked-down” state to user when WP# is VIL. Blocks in “virtual lockdown” will be immediately unlocked when WP# is VIH. Therefore, to avoid “virtual lockdown”, a Lock command must be issued to an unlocked block prior to WP# going low. Device reset or power-down resets all blocks to the locked state[101] or [001], including locked-down blocks. 10.1.6 Block Lock Status Every block’s lock status can be read in the device’s read identifier mode. To enter this mode, write 90h to the device. Subsequent reads at Block base-address + 00002h output that block’s lock status. Data bits DQ0 and DQ1 represent the lock status. DQ0 indicates the block lock/unlock state as set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates lock-down state as set by the Lock-Down command. It cannot be cleared by software, only by device reset or power-down. See Table 14, “Block Locking State Transitions” on page 32. July 2010 316144-07 31 Numonyx® Omneo™ P8P Datasheet 10.1.7 Locking Operations During Erase Suspend Block lock configurations can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful when another block needs to be updated while an erase operation is suspended. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has suspended. Next write the desired lock command sequence to a block; the lock state will be changed. After completing lock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will change immediately. But, when resumed, the erase operation will complete. Locking operations cannot occur during write suspend. Appendix A, “Write State Machine” on page 80 shows valid commands during erase suspend. Nested lock or write commands during erase suspend can return ambiguous Status Register results. 60h followed by 01h commands lock a block. A Configuration Setup command (60h) followed by an invalid command produces a lock command Status Register error (SR.4 and SR.5 = 1). If this error occurs during erase suspend, SR.4 and SR.5 remain at 1 after the erase resumes. When erase completes, the previous locking command error hides the Status Register’s erase errors. A similar situation occurs if a write operation error is nested within an erase suspend. Table 14: Block Locking State Transitions Current State Erase/Write Allowed?(1) WP# 0 0 0 0 1 1 1 1 Notes: 1. 2. 3. 4. 5. LAT 1 0 0 1 1 0 0 1 1 LAT 0 0 1 0 1 0 1 0 1 Unlocked Locked (default) (1) Virtual lock-down (4) Locked-Down Unlocked Locked Lock-Down Disabled Lock-Down Disabled Name Yes No No No Yes No Yes No Lock Command Input Result (Next State) (5) LockDown 011 011 011 011 111 111 111 111 WP# Toggle Result (Next State) 100 101 110 111 000 001 010 011 Locking Status Readout D1 0 0 1 1 0 0 1 1 D0 0 1 1 1 0 1 0 1 UnLock 000 000 011 011 100 100 110 110 Lock 001 001 011 011 101 101 111 111 Additional illegal states are shown but are not recommended for normal, non-erroneous operational modes. “Erase/Write Allowed?” shows whether a block’s current locking state allows erase or write. At power-up or device reset, blocks default to locked state [001] if WP# = 0, the recommended default. Blocks in “virtual lock-down” appear to be in locked-down state when WP#=VIL. WP# = 1 changes [010] to unlocked state [110]. “This column shows results of writing the four locking commands or WP# toggle from the current locking state. Datasheet 32 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Figure 6: Block Locking State Diagram Power-Up/Reset Locked [x01] LockedDown 4, 5 [ 011] Hardware Locked 5 [011 ] WP# Hardware Control Unlocked [x00] Software Locked [ 111] Unlocked [ 110] S oftw are B loc k Loc k (0x 60/ 0x 01) or S oftw are B loc k Unloc k (0x60/ 0x D0) S oftw are B loc k Loc k -D ow n (0x 60/0x 2F) WP # hardware c ontrol Notes : 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care 2. DQ1 indicates Block Lock -Down status DQ1 = ‘0’, Lock-Down has not bee issued to this block . . DQ1 = ’1', Lock-Down has been issued to this block . 3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked . DQ0 = ‘1’, block is locked . 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked system software to determine difference between Hardware Locked and Locked -Down states . 10.2 Permanent One Time Programmable (OTP) Block Locking The parameter blocks and first 3 main blocks for a bottom parameter device (or if device configured as a top parameter device this would be the last 3 main blocks and the parameter blocks) can be made OTP, so further write and erase operations to these blocks are disallowed, effectively permanently programming the blocks. This is achieved by programming bits 2, 3, 4, and 5 in the PR-LOCK0 register at offset 0x80 in ID Space. The OTP locking bit mapping may be seen in Table 15, “Selectable OTP Block Locking Feature” on page 34 below. Bit 6 in the PR-LOCK0 register at offset 0x80 in ID space is defined as the Configuration Lock bit. When bit 6 is cleared (at zero), the device shall disable further programming of the OTP Lock bits, thereby effectively “freezing” their state. Putting bit 6 at zero shall not affect the ability to write any other bits in the non OTP regions or in the System Protection Registers. Reference Table 16, “Selectable OTP Block Locking Programming of PR-LOCK0” on page 34 for Configuration Lock bit (Bit 6 in PR-LOCK0) control of allowed states when other bits of the register are programmed. The read operations of these permanently locked blocks are always supported regardless of the state of their corresponding Permanent Lock bits. Zero Latency Block Locking must be used until the block is permanently locked with the OTP Block Locking. Program and erase operations for these blocks remain fully supported until that block’s Permanent Lock bit is cleared. Program or erase operations to a permanently locked block returns a Status Register bit SR.1 error. Programming of the Permanent OTP Block Locking bits is not allowed during Erase Suspend of a Permanent Lockable Block. July 2010 316144-07 33 Numonyx® Omneo™ P8P Datasheet Note: The Selectable Block Locking will not be indicated in the Zero Latency Block Lock Status. See Section 10.1.6, “Block Lock Status” on page 31 for more information. Read PR-LOCK0 register to determine Block Lock Status for these blocks. Table 15: Selectable OTP Block Locking Feature Bit Number @ Offset 0x80 in CFI Space 2 Function When Set (‘1b) Function When Cleared (‘0b) Write/erase disabled for all parameter blocks Bottom Boot - Blocks 0-3 Top Boot 128M - Blocks 127-130 Write/erase disabled for first Main Block Bottom Boot - Block 4 Top Boot 128M - Block 126 Write/erase disabled for second Main Block Bottom Boot - Block 5 Top Boot 128M - Block 125 Write/erase disabled for third Main Block Bottom Boot - Block 6 Top Boot 128M - Block 124 Program disabled for PR-LOCK0[5:2] Blocks not permanently locked 3 Block not permanently locked 4 Block not permanently locked 5 6 Block not permanently locked Able to change PR-LOCK0[5:2] Bits Table 16: Selectable OTP Block Locking Programming of PR-LOCK0 Bit 6 unlocked locked locked locked Program to [5:2] don’t care YES YES NO Program to [1:0] don’t care YES NO YES Status Register no fail bits set program fail/ lock fail program fail/ lock fail no fail bits set Abort Program NO YES YES NO Status of Data in 80H OTP Space Changed No Change No Change Changed Figure 7: Selectable OTP Locking Illustration (Bottom Parameter Device Example) Main Array Block 6 0x030000 (Main Array) Main Array Block 5 0x020000 (Main Array) Main Array Block 4 0x010000 (Main Array) Parameter Blocks - Block 0-3 0x000000 (Parameter Array) 0x80 (OTP Array) PR-LOCK0 65432 { BOOT_ROM.WMF Datasheet 34 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 10.2.1 WP# Lock-Down Control for Selectable OTP Lock Blocks Once the block has been permanently locked with OTP bit, WP# at VIH does not override the lock down of the blocks those bits control. 10.2.2 Selectable OTP Locking Implementation Details Clearing (write to “0”) any of the four Permanent Lock bits shall effectively cause the following commands to fail with a block locking error when issued to their corresponding blocks: Buffer Program command, Bit-Alterable Buffer Write command, Word Program command, Bit-Alterable Word Write command, and Erase command. No other commands shall be affected. Programming the Permanent Lock bits or the Configuration Lock bit shall be done using the Protection Register Programming command. As with all bits in the CFI/OTP space once the Permanent Lock or the Configuration bits are programmed, they may not be erased (set) again. July 2010 316144-07 35 Numonyx® Omneo™ P8P Datasheet 11.0 11.1 Registers Read Status Register The device’s Status Register displays program and erase operation status. A device’s status can be read after writing the Read Status Register command. The Status Register can also be read following a Program, Erase, or Lock Block command sequence. Subsequent single reads from the device outputs its status until another valid command is written. The last of OE# or CE# falling edge latches and updates the Status Register content. DQ[7:0] output is the Status Register bits; DQ[15:8] output 00h. See Table 17, “Status Register Definitions” on page 36. Issuing a Read Status, Block Lock, Program, or Erase command to the device places it in the Read Status mode. Status Register bit SR.7 (DWS — Device Write Status) provides program/erase status of the device. Status Register bits SR.1-SR.6 present information about the WSM’s program, erase, suspend, VPP, and block-lock status mode. Table 17: Status Register Definitions DRS SR.7 ESS SR.6 Status Register Bits SR.7 = Device Write/Erase Status (DRS) 0 = Device WSM is Busy 1 = Device WSM is Ready SR.6 = Erase Suspend Status (ESS) 0 = Erase in progress/ completed 1 = Erase suspended SR.5 = Erase Status (ES) 0 = Successful erase 1 = Erase error SR.4 = Write Status (PS) 0 = Successful write 1 = Write error SR.3 = VPP Status (VPPS) 0 = VPP OK 1 = VPP low detect, operation aborted SR.2 = Write Suspend Status (PSS) 0 = Write in progress/ completed 1 = Write suspended SR.1 = Device Protect Status (DPS) 0 = Unlocked 1 = Aborted erase/program attempt on locked block SR.0 Super Page Write Status (PWS) 0 = Reserved 1 = Reserved ES SR.5 PS SR.4 VPPS SR.3 PSS SR.2 Notes: SR.7 indicates erase or program completion in the device. SR.1–6 are invalid while SR.7 = “0.” DPS SR.1 PRW SR.0 After issuing an Erase Suspend command, the WSM halts and sets (1) SR.7 and SR.6. SR.6 remains set until the device receives an Erase Resume command. SR.5 is set (1) if an attempted erase failed. A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set. SR.4 is set (1) if the WSM failed to program. A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set. The WSM indicates the VPP level after program or erase starts. SR.3 does not provide continuous VPP feedback and isn’t guaranteed when VPP < VPPLK After receiving a Write Suspend command, the WSM halts execution and sets (1) SR.7 & SR.2, which remains set until a Resume command is received. If an erase or program operation is attempted to a locked block (if WP# = VIL), the WSM sets (1) SR.1 and aborts the operation. Reserved Datasheet 36 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 11.1.1 Clear Status Register Command The Clear Status Register command clears the Status Register. The command functions independently of the applied VPP voltage. The WSM can set (1) Status Register bits SR[7:0] and clear (0) bits 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate various error conditions, they can only be cleared by the Clear Status Register command. By allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) may be performed before reading the Status Register to determine error occurrence. The Status Register should be cleared before beginning another command or sequence. Device reset (RST# = VIL) also clears the Status Register. 11.2 System Protection Registers The device contains two 64-bit, and sixteen 128-bit individually lockable protection registers that can increase system security or hinder device substitution by containing values that mate the PCM component to the system’s CPU or ASIC. One 64-bit protection register is programmed at the Numonyx factory with an nonchangeable unique 64-bit number. The other 64-bit and sixteen 128-bit protection registers are blank so customers can program them as desired. Once programmed, each customer segment can be locked to prevent further reprogramming. 11.2.1 Read Protection Register The Read Identifier command allows Protection register data to be read 16 bits at a time from addresses shown in Table 9, “Read Identifier Table” on page 22. To read the Protection Register, first issue the Read Device Identifier command at Device Base Address to place the device in the Read Device Identifier mode. Next, perform a read operation at the device’s base address plus the address offset corresponding to the register to be read. Table 9, “Read Identifier Table” on page 22 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. Refer Appendix , “Protection Register Addressing” on page 39. 11.2.2 Program Protection Register The Protection Program command should be issued followed by the data to be programed at the specified location. It programs the 64 user protection register 16 bits at a time. Table 9, “Read Identifier Table” on page 22 and in Table 18 on page 39 show allowable addresses. See also Figure 36, “Protection Register Programming Flowchart” on page 79. Addresses A[MAX:11] are ignored when programming the OTP, and OTP program will succeed if A[10:1] are within the prescribed protection addressing range; otherwise an error is indicated by SR4 = 1. 11.2.3 Lock Protection Register Each of the protection registers are lockable by programming their respective lock bits in the PR-LOCK0 or PR-LOCK1 registers. Bit 0 of the Lock-Register -0 is programmed by Numonyx to lock-in the unique device number. The physical address of the PR-LOCK0 register is 80h as seen in Figure 8, “Protection Register Memory Map” on page 38. Bit 1 of the Lock-Register -0 can be programmed by the user to lock the upper 64-bit portion. (Refer Table 18, “Protection Register Addressing” on page 39.). The bits in both PR-LOCK registers are made of “PCM cells” that may only be programmed to ‘0’ and may not be altered. Note: Bit0 of the Lock-Register, PR-LOCK0, is a don’t care, so users must mask out this bit when reading PR-LOCK0 register. This number is guaranteed to persist through board attach. July 2010 316144-07 37 Numonyx® Omneo™ P8P Datasheet For the 2K OTP space, there exists an additional 16-bit lock register called PR_LOCK1. Each bit in the PR_LOCK1 register locks a 128-bit segment of the 2K-OTP space. Therefore, the 16 128-bit segments of the 2K OTP space can be locked individually. Hence, any 128-bit segment can be first programmed and then locked using the protection program command followed by protection register data. The PR-LOCK1 register is physically located at the address 89h as shown in the Figure 8, “Protection Register Memory Map” on page 38. After PR-LOCK register bits have been programmed, no further changes can be made to the protection registers' stored values. Protection Program commands written to a locked section result in a Status Register error (Program Error bit SR.4 and Lock Error bit SR.1 are set to 1). Once locked, Protection register states are not reversible. Figure 8: Protection Register Memory Map 109h 8 Words User Programmed 102h 91h 8 Words User Programmed 8Ah 89h Group 2 Group 17 Lock Register 1 88h 4 Words (64 bits) User Programmed 85h 84h 81h 80h Group 1 4 Words (64 bits) Intel Factory Programmed Group 0 Lock Register 0 Datasheet 38 … July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 11.2.3.1 OTP Protection Register Addressing details Table 18: Protection Register Addressing Word LOCK 0 1 2 3 4 5 6 7 Note: Use Both Numonyx Numonyx Numonyx Numonyx Customer Customer Customer Customer ID Offset DBA + 000080h DBA + 000081h DBA + 000082h DBA + 000083h DBA + 000084h DBA + 000085h DBA + 000086h DBA + 000087h DBA + 000088h A8 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 0 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0 Addresses A9-A23 should be set to zero. Table 19: 2K OTP Space Addressing Word Lock 0 : : 127 Note: Use Customer Customer : : Customer ID Offset DBA+000089h DBA+00008Ah : : DBA+000109h A13 0 0 : : 0 A12 0 0 : : 0 A11 0 0 : : 0 A10 0 0 : : 0 A9 0 0 : : 1 A8 1 1 : : 0 A7 0 0 : : 0 A6 0 0 : : 0 A5 0 0 : : 0 A4 1 1 : : 1 A3 0 0 : : 0 A2 0 1 : : 0 A1 1 0 : : 1 DBA - Device Base Address. Typically this would start from Address 0. July 2010 316144-07 39 Numonyx® Omneo™ P8P Datasheet 12.0 12.1 Serial Peripheral Interface (SPI) SPI Overview A Serial Peripheral Interface has been added as a secondary interface on Numonyx® Omneo™ P8P PCM to enable low cost, low pin count on-board programming. This interface gives access to the P8P memory by using only seven signals, instead of a conventional parallel interface that may take 45 signals or more. The seven signals consist of six SPI-only signals plus one signal that is shared with the conventional interface. When the SPI mode is enabled, all non-SPI P8P output signals are tri-stated, and all non-SPI P8P inputs signals are ignored (made “don't care”). When the conventional interface is enabled, the SPI-only output is tri-stated, and the SPI-only inputs are ignored (made “don't care”). Note: The SPI interface can only be enable upon power-up, and to enable this interface the SERIAL pin must be tied to Vcc for the interface to be factional. Once the SPI interface is enable it is the only interface that can be accessed until the part is powered down. The SPI mode may be disabled. Please contact Numonyx for more information. 12.2 SPI Signal Names For P8P, the six additional SPI-only signals are implemented in addition to the power pins. VCC, VCCQ, and VPP are valid power pins during Serial mode and must be connected during SPI mode operation. Four of the six additional SPI signals do not share functions with the regular interface. For pin and signal descriptions of all P8P pins see Table 5, “Ball/Pin Descriptions” on page 16. Two pins are shared between the interface modes: S# is the same pin as CE#, and HOLD# is the same pin as OE#. The signals that are unique to the SPI mode and require a separate connection are C, D, Q, and SERIAL. Datasheet 40 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.3 SPI Memory Organization The memory is organized as: • 16,772,216 bytes (8 bits each) • 128 sectors (128 Kbytes each) • 131,072 pages (64 bytes each) Each page can be individually programmed (bits are programmed from ‘1’ to ‘0’) or written (bit alterable: ‘1’ can be altered to ‘0’ and ‘0’ can be altered to ‘1’). The device is sector or bulk erasable (bits are erased from ‘0’ to ‘1’). Table 6. Memory organization Sector 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 77 Address range FE0000 FC0000 FA0000 F80000 F60000 F40000 F20000 F00000 EE0000 EC0000 EA0000 E80000 E60000 E40000 E20000 E00000 DE0000 DC0000 DA0000 D80000 D60000 D40000 D20000 D00000 CE0000 9A0000 FFFFFF FDFFFF FBFFFF F9FFFF F7FFFF F5FFFF F3FFFF F1FFFF EFFFFF EDFFFF EBFFFF E9FFFF E7FFFF E5FFFF E3FFFF E1FFFF DFFFFF DDFFFF DBFFFF D9FFFF D7FFFF D5FFFF D3FFFF D1FFFF CFFFFF 9BFFFF Sector 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 42 Address range CC0000 CA0000 C80000 C60000 C40000 C20000 C00000 BE0000 BC0000 BA0000 B80000 B60000 B40000 B20000 B00000 AE0000 AC0000 AA0000 A80000 A60000 A40000 A20000 A00000 9E0000 9C0000 540000 CDFFFF CBFFFF C9FFFF C7FFFF C5FFFF C3FFFF C1FFFF BFFFFF BDFFFF BBFFFF B9FFFF B7FFFF B5FFFF B3FFFF B1FFFF AFFFFF ADFFFF ABFFFF A9FFFF A7FFFF A5FFFF A3FFFF A1FFFF 9FFFFF 9DFFFF 55FFFF July 2010 316144-07 41 Numonyx® Omneo™ P8P Datasheet Table 6. Memory organization (Continued) Sector 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Address range 980000 960000 940000 920000 900000 8E0000 8C0000 8A0000 880000 860000 840000 820000 800000 7E0000 7C0000 7A0000 780000 760000 740000 720000 700000 6E0000 6C0000 6A0000 680000 660000 640000 620000 600000 5E0000 5C0000 5A0000 580000 99FFFF 97FFFF 95FFFF 93FFFF 91FFFF 8FFFFF 8DFFFF 8BFFFF 89FFFF 87FFFF 85FFFF 83FFFF 81FFFF 7FFFFF 7DFFFF 7BFFFF 79FFFF 77FFFF 75FFFF 73FFFF 71FFFF 6FFFFF 6DFFFF 6BFFFF 69FFFF 67FFFF 65FFFF 63FFFF 61FFFF 5FFFFF 5DFFFF 5BFFFF 59FFFF Sector 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Address range 520000 500000 4E0000 4C0000 4A0000 480000 460000 440000 420000 400000 3E0000 3C0000 3A0000 380000 360000 340000 320000 300000 2E0000 2C0000 2A0000 280000 260000 240000 220000 200000 1E0000 1C0000 1A0000 180000 160000 140000 120000 53FFFF 51FFFF 4FFFFF 4DFFFF 4BFFFF 49FFFF 47FFFF 45FFFF 43FFFF 41FFFF 3FFFFF 3DFFFF 3BFFFF 39FFFF 37FFFF 35FFFF 33FFFF 31FFFF 2FFFFF 2DFFFF 2BFFFF 29FFFF 27FFFF 25FFFF 23FFFF 21FFFF 1FFFFF 1DFFFF 1BFFFF 19FFFF 17FFFF 15FFFF 13FFFF Datasheet 42 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Table 6. Memory organization (Continued) Sector 43 7 6 5 4 Address range 560000 0E0000 0C0000 0A0000 080000 57FFFF 0FFFFF 0DFFFF 0BFFFF 09FFFF Sector 8 3 2 1 0 Address range 100000 060000 040000 020000 000000 11FFFF 07FFFF 05FFFF 03FFFF 01FFFF 12.4 SPI Instruction Serial data input D is sampled on the first rising edge of Serial Clock (C) after Chip Select (S#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input DQ0, each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 20 on page 44. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ), read status register (RDSR) or read identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a page program (PP), sector erase (SE), write status register (WRSR), write enable (WREN), or write disable (WRDI), Chip Select (S#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S#) must driven High when the number of clock pulses after Chip Select (S#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write status register cycle, program cycle erase cycle are ignored, and the internal write status register cycle, program cycle, erase cycle continues unaffected. Note: Output Hi-Z is defined as the point where data out is no longer driven July 2010 316144-07 43 Numonyx® Omneo™ P8P Datasheet Table 20: Instruction set Instruction WREN WRDI RDID RDSR WRSR READ FAST_READ Description Write enable Write disable Read identification Read status register Write status register Read data bytes Read data bytes at higher speed Page program (Legacy Program) PP Page program (Bit-alterable write) Page program (On all 1’s) SE Sector erase One-byte instruction code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 0010 0010 1101 0001 1101 1000 06h 04h 9Fh 05h 01h 03h 0Bh 02h 22h D1h D8h Address bytes 0 0 0 0 0 3 3 3 3 3 3 Dummy bytes 0 0 0 0 0 0 1 0 0 0 0 Data bytes 0 0 1 to 3 1 to ∞ 1 1 to ∞ 1 to ∞ 1 to 64 1 to 64 1 to 64 0 12.4.1 Write enable (WREN) The write enable (WREN) instruction sets the write enable latch (WEL) bit. The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase (SE), or write status register (WRSR) instruction. The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 9: Write enable (WREN) instruction sequence S 0 C Instruction DQ0 High Impedance DQ1 AI13731 1 2 3 4 5 6 7 Datasheet 44 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.4.2 Write disable (WRDI) The write disable (WRDI) instruction resets the write enable latch (WEL) bit. The write disable (WRDI) instruction is entered by driving Chip Select (S#) Low, sending the instruction code, and then driving Chip Select (S#) High. The write enable latch (WEL) bit is reset under the following conditions: • Power-up • Write disable (WRDI) instruction completion • Write status register (WRSR) instruction completion • Page program (PP) instruction completion • Sector erase (SE) instruction completion Figure 10: Write disable (WRDI) instruction sequence S 0 C Instruction DQ0 High Impedance DQ1 AI13732 1 2 3 4 5 6 7 July 2010 316144-07 45 Numonyx® Omneo™ P8P Datasheet 12.4.3 Read identification (RDID) The read identification (RDID) instruction allows to read the device identification data: • Manufacturer identification (1 byte) • Device identification (2 bytes) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. Any read identification (RDID) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S#) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification stored in the memory will be shifted out on serial data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). The read identification (RDID) instruction is terminated by driving Chip Select (S#) High at any time during data output. When Chip Select (S#) is driven High, the device is put in the standby power mode. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 11: Read identification (RDID) instruction sequence and data-out sequence S 0 C Instruction D Manufacturer identification High Impedance Q MSB 15 14 13 MSB AI06809c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 Device identification 3 2 1 0 Datasheet 46 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.4.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase, write status register is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the status register continuously, as shown in Figure 12 on page 49 RDSR is the only instruction accepted by the device while a program, erase, write status register operation is in progress. Table 21: Status register format b7 SRWD BP3 TB BP2 BP1 BP0 WEL b0 WIP Status register write protect RFU RFU Write enable latch bit Write in progress bit The status and control bits of the status register are as follows: 12.4.4.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program, erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is in progress. While WIP is ‘1’, RDSR is the only instruction the device will accept; all other instructions are ignored. 12.4.4.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is reset and no write status register, program, erase instruction is accepted. 12.4.4.3 BP3, BP2, BP1, BP0 bits The block protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against program (or write) and erase instructions. These bits are written with the write status register (WRSR) instruction. When one or more of the block protect (BP3, BP2, BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 1) becomes protected against page program (PP), dual input fast program (DIFP), quad input fast program (QIFP), and sector erase (SE) instructions. The block protect (BP3, BP2, BP1, BP0) bits can be written provided that the hardware protected mode has not been set.The bulk erase (BE) instruction is executed if, and only if, all block protect (BP3, BP2, BP1, BP0) bits are 0. July 2010 316144-07 47 Numonyx® Omneo™ P8P Datasheet b Table 7. Protected area sizes Memory content Protected area none Upper 128th (Sector 127) Upper 64th (Sectors 126 to 127) Upper 32nd (Sectors 124 to 127) Upper 16th (Sectors 120 to 127) Upper 8th (Sectors 112 to 127) Upper quarter (Sectors 96 to 127) Upper half (Sectors 64 to 127) All sectors (Sectors 0 to 127) none Lower 128th (Sector 0) Lower 64th (Sectors 0 to 1) Lower 32nd (Sectors 0 to 3) Lower 16th (Sectors 0 to 7) Lower 8th (Sectors 0 to15) Lower 4th (Sectors 0 to 31) Lower half (Sectors 0 to 63) All sectors (Sectors 0 to 127) Unprotected area All sectors1 (Sectors 0 to 127) Sectors 0 to 126 Sectors 0 to 125 Sectors 0 to 123 Sectors 0 to 119 Sectors 0 to 111 Sectors 0 to 95 Sectors 0 to 63 None All sectors(1) (Sectors 0 to 127) Sectors 1 to 127 Sectors 2 to 127 Sectors 4 to 127 Sectors 8 to 127 Sectors 16 to 127 Sectors 32 to 127 Sectors 64 to 127 None Status register contents TB bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 BP bit 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 BP bit 2 0 0 0 0 1 1 1 1 X (2) BP bit 1 0 0 1 1 0 0 1 1 X(2) 0 0 1 1 0 0 1 1 X(2) BP bit 0 0 1 0 1 0 1 0 1 X(2) 0 1 0 1 0 1 0 1 X(2) 0 0 0 0 1 1 1 1 X(2) 1. The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP3, BP2, BP1, BP0) are 0 2. X can be 0 or 1 1. 12.4.4.4 Top/bottom bit Reads as 0 12.4.4.5 SRWD bit The status register write disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The status register write disable (SRWD) bit and the write protect (W) signal allow the device to be put in the hardware protected mode (when the status register write disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the non-volatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only bits and the write status register (WRSR) instruction is no longer accepted for execution. Datasheet 48 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Figure 12: Read status register (RDSR) instruction sequence and data-out sequence S 0 C Instruction DQ0 Status register out High Impedance DQ1 7 MSB 6 5 4 3 2 1 0 7 MSB AI13734 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Status register out 6 5 4 3 2 1 0 7 July 2010 316144-07 49 Numonyx® Omneo™ P8P Datasheet 12.4.5 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL). The write status register (WRSR) instruction is entered by driving Chip Select (S#) Low, followed by the instruction code and the data byte on serial data input (DQ0). The write status register (WRSR) instruction has no effect on b1 and b0 of the status register. Chip Select (S#) must be driven High after the eighth bit of the data byte has been latched in. If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select (S#) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The write status register (WRSR) instruction allows the user to change the values of the block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only. The write status register (WRSR) instruction also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the hardware protected mode (HPM). The write status register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. Read Status Register (RDSR) is the only instruction accepted while WRSR operation is in progress; all other instructions are ignored. Figure 13: Write status register (WRSR) instruction sequence S 0 C Instruction Status register in 7 High Impedance DQ1 AI13735 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ0 6 5 4 3 2 1 0 MSB Datasheet 50 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.4.6 Read data bytes (READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address A[23:0], each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes (READ) instruction is terminated by driving Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data output. Any read data bytes (READ) instruction, while an erase, program, write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14: Read data bytes (READ) instruction sequence and data-out sequence S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 DQ0 High Impedance DQ1 23 22 21 MSB 3 2 1 0 Data out 1 7 6 5 4 3 2 1 0 Data out 2 7 MSB AI13736b July 2010 316144-07 51 Numonyx® Omneo™ P8P Datasheet 12.4.7 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S#) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on serial data output (Q) at a maximum frequency fC, during the falling edge of Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase, program, write, or cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 15: Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 10 28 29 30 31 DQ0 High Impedance DQ1 23 22 21 3 2 1 0 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 7 6 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI13737b DQ1 7 MSB 6 5 4 3 2 Datasheet 52 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.4.8 Note: Page program (PP) This definition applies to all flavors of Page Program: Legacy Program, Bit-alterable. The page program (PP) instruction allows bytes to be programmed/written in the memory. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page program (PP) instruction is entered by driving Chip Select (S#) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S#) must be driven Low for the entire duration of the sequence. If more than 64 bytes are sent to the device, previously latched data are discarded and the last 64 data bytes are guaranteed to be programmed/written correctly within the same page. If less than 64 data bytes are sent to device, they are correctly programmed/written at the requested addresses without having any effects on the other bytes of the same page. (With Program on all 1s, the entire page should already have been set to all 1s (FFh).) For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes. Chip Select (S#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page program (PP) instruction is not executed. As soon as Chip Select (S#) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the page program cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while a Page Program operation is in progress; all other instructions are ignored. July 2010 316144-07 53 Numonyx® Omneo™ P8P Datasheet Figure 16: Page program (PP) instruction sequence S 0 C Instruction 24-bit address (1) Data byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 DQ0 23 22 21 MSB 3 2 1 0 7 6 5 4 3 2 1 0 MSB S 2072 2073 2074 2075 2076 2077 2 2078 1 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte 256 2079 0 AI13739b DQ0 7 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 MSB MSB Datasheet 54 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet 12.4.9 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The sector erase (SE) instruction is entered by driving Chip Select (S#) Low, followed by the instruction code, and three address bytes on serial data input (DQ0). Any address inside the sector is a valid address for the sector erase (SE) instruction. Chip Select (S#) must be driven Low for the entire duration of the sequence. Chip Select (S#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip Select (S#) is driven High, the self-timed sector erase cycle (whose duration is tSE) is initiated. While the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted while device is busy with erase operation; all other instructions are ignored. A sector erase (SE) instruction applied to a page which is protected by the block protect (BP3, BP2, BP1, BP0) bits is not executed. Figure 17: Sector erase (SE) instruction sequence S 0 C Instruction 24-bit address (1) 1 2 3 4 5 6 7 8 9 29 30 31 DQ1 23 22 MSB 2 1 0 AI13742b July 2010 316144-07 55 Numonyx® Omneo™ P8P Datasheet 13.0 13.1 Power and Reset Specification Power-Up and Power-Down Upon power-up the flash memory interface is defined by the SERIAL pin being at Vss (parallel) or Vcc (serial). • During power-up if the SERIAL pin is at Vss the flash memory will be a x16 parallel interface. • During power-up if the SERIAL pin is at Vcc the flash memory will be a SPI interface. After the interface is defined it can not be changed until a full power-down is completed and a power-up sequence is reinitiated. Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise VCC and VCCQ should attain their minimum operating voltage before applying VPP. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions. 13.2 Reset Specifications Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. Table 22: Power and Reset Num P1 P2 P3 Notes: 1. 2. 3. 4. 5. 6. 7. Symbol tPLPH tPLRH tVCCPH Parameter(1) RST# pulse width low RST# low to device reset during erase RST# low to device reset during program VCC Power valid to RST# de-assertion (high) Min 100 100 Max 40 40 us Unit ns Notes 1,2,3,4 1,3,4,7 1,3,4,7 1,4,5,6 These specifications are valid for all device versions (packages and speeds). The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed. Not applicable if RST# is tied to Vcc. Sampled, but not 100% tested. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing. Datasheet 56 July 2010 316144-07 Numonyx® Omneo™ P8P Datasheet Figure 18: Reset Operation Waveforms P1 R5 (A) Reset during read mode RST# [P] VIH VIL P2 (B) Reset during program or block erase P1 ≤ P2 Abort Complete R5 RST# [P] VIH VIL P2 (C) Reset during program or block erase P1 ≥ P2 Abort Complete R5 RST# [P] VIH VIL P3 (D) VCC Power-up to RST# high VCC VCC 0V 13.3 Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are 1) standby current levels, 2) active current levels, and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. Highfrequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance. July 2010 316144-07 57 Numonyx® Omneo™ P8P Datasheet 14.0 14.1 Warning: Max Ratings and Operating Conditions Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 23: Absolute Maximum Ratings Parameter Voltage on any signal (except VCC, Vccq, VPP)(1) VPP voltage (2,4) Maximum Rating –2.0 V to +5.6v,