PC48F4400PJQB0

Numonyx™ Wireless Flash Memory (W18) Datasheet Product Features High Performance Read-While-Write/Erase — Burst frequency at 66 MHz (zero wait states) — 60 ns Initial access read speed — 11 ns Burst mode read speed — 20 ns Page mode read speed — 4-, 8-, 16-, and Continuous-Word Burst mode reads — Burst and Page mode reads in all Blocks, across all partition boundaries — Burst Suspend feature — Enhanced Factory Programming at 3.1 µs/ word Security — 128-Bit OTP Protection Register: 64 unique pre-programmed bits + 64 user-programmable bits — Absolute Write Protection with VPP at ground — Individual and Instantaneous Block Locking/ Unlocking with Lock-Down Capability Quality and Reliability — Temperature Range: –40 °C to +85 °C — 100K Erase Cycles per Block — 90 nm ETOX™ IX Process — 130 nm ETOX™ VIII Process Architecture — Multiple 4-Mbit partitions — Dual Operation: RWW or RWE — Parameter block size = 4-Kword — Main block size = 32-Kword — Top or bottom parameter devices — 16-bit wide data bus Software — 5 µs (typ.) Program and Erase Suspend latency time — Flash Data Integrator (FDI) and Common Flash Interface (CFI) Compatible — Programmable WAIT signal polarity Packaging and Power — 90 nm: 32- and 64-Mbit in VF BGA — 130 nm: 32-, 64-, and 128-Mbit in VF BGA — 130 nm: 128-Mbit in QUAD+ package — 56 Active Ball Matrix, 0.75 mm Ball-Pitch — VCC = 1.70 V to 1.95 V — VCCQ (90 nm) = 1.7 V to 1.95 V — VCCQ (130 nm) = 1.7 V to 2.24 V or 1.35 V to 1.80 V — VCCQ (130 nm) = 1.35 V to 2.24 V — Standby current (130 nm): 8 µA (typ.) — Read current: 8 mA (4-word burst, typ.) Order Number: 290701-18 November 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Legal L ines and D isc laim er s Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx B.V., All Rights Reserved. Datasheet 2 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Contents 1.0 Introduction .............................................................................................................. 7 1.1 Nomenclature ..................................................................................................... 7 1.2 Conventions ....................................................................................................... 8 Functional Overview .................................................................................................. 9 2.1 Memory Map and Partitioning .............................................................................. 10 Package Information ............................................................................................... 13 3.1 W18 — 90 nm Lithography ................................................................................. 13 3.2 W18 — 130 nm ................................................................................................. 14 Ballout and Signal Descriptions ............................................................................... 16 4.1 Signal Ballout ................................................................................................... 16 4.2 Signal Descriptions ............................................................................................ 18 Maximum Ratings and Operating Conditions ............................................................ 21 5.1 Absolute Maximum Ratings................................................................................. 21 5.2 Operating Conditions ......................................................................................... 21 Electrical Specifications ........................................................................................... 23 6.1 DC Current Characteristics.................................................................................. 23 6.2 DC Voltage Characteristics.................................................................................. 24 AC Characteristics ................................................................................................... 26 7.1 AC Write Characteristics ..................................................................................... 36 7.2 Erase and Program Times................................................................................... 42 7.3 Reset Specifications........................................................................................... 43 7.4 AC I/O Test Conditions....................................................................................... 44 7.5 Device Capacitance ........................................................................................... 45 Power and Reset Specifications ............................................................................... 46 8.1 Active Power..................................................................................................... 46 8.2 Automatic Power Savings (APS) .......................................................................... 46 8.3 Standby Power.................................................................................................. 46 8.4 Power-Up/Down Characteristics........................................................................... 46 8.4.1 System Reset and RST#.......................................................................... 46 8.4.2 VCC, VPP, and RST# Transitions............................................................... 47 8.5 Power Supply Decoupling ................................................................................... 47 Bus Operations Overview ........................................................................................ 48 9.1 Bus Operations ................................................................................................. 48 9.1.1 Reads ................................................................................................... 48 9.1.2 Writes................................................................................................... 49 9.1.3 Output Disable ....................................................................................... 49 9.1.4 Burst Suspend ....................................................................................... 49 9.1.5 Standby ................................................................................................ 50 9.1.6 Reset.................................................................................................... 50 9.2 Device Commands............................................................................................. 50 9.3 Command Sequencing ....................................................................................... 53 Operations ...................................................................................................... 55 Asynchronous Page Read Mode ........................................................................... 55 Synchronous Burst Read Mode ............................................................................ 55 Read Array ....................................................................................................... 56 Read Identifier.................................................................................................. 56 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Read 10.1 10.2 10.3 10.4 November 2007 Order Number: 290701-18 Datasheet 3 Numonyx™ Wireless Flash Memory (W18) 10.5 10.6 10.7 CFI Query .........................................................................................................57 Read Status Register..........................................................................................57 Clear Status Register .........................................................................................58 11.0 Program Operations .................................................................................................59 11.1 Word Program ...................................................................................................59 11.2 Factory Programming .........................................................................................60 11.3 Enhanced Factory Program (EFP) .........................................................................61 11.3.1 EFP Requirements and Considerations .......................................................61 11.3.2 Setup....................................................................................................62 11.3.3 Program ................................................................................................62 11.3.4 Verify....................................................................................................62 11.3.5 Exit.......................................................................................................63 12.0 Program and Erase Operations .................................................................................65 12.1 Program/Erase Suspend and Resume ...................................................................65 12.2 Block Erase .......................................................................................................67 12.3 Read-While-Write and Read-While-Erase ...............................................................69 13.0 Security Modes ........................................................................................................71 13.1 Block Lock Operations ........................................................................................71 13.1.1 Lock......................................................................................................72 13.1.2 Unlock...................................................................................................72 13.1.3 Lock-Down ............................................................................................72 13.1.4 Block Lock Status ...................................................................................73 13.1.5 Lock During Erase Suspend ......................................................................73 13.1.6 Status Register Error Checking .................................................................73 13.1.7 WP# Lock-Down Control ..........................................................................74 13.2 Protection Register.............................................................................................74 13.2.1 Reading the Protection Register ................................................................75 13.2.2 Programing the Protection Register ...........................................................75 13.2.3 Locking the Protection Register.................................................................75 13.3 VPP Protection...................................................................................................77 14.0 Set Read Configuration Register ..............................................................................78 14.1 Read Mode (RCR[15]) ........................................................................................79 14.2 First Access Latency Count (RCR[13:11]) ..............................................................79 14.2.1 Latency Count Settings............................................................................80 14.3 WAIT Signal Polarity (RCR[10]) ...........................................................................81 14.4 WAIT Signal Function .........................................................................................81 14.5 Data Hold (RCR[9])............................................................................................82 14.6 WAIT Delay (RCR[8]) .........................................................................................83 14.7 Burst Sequence (RCR[7])....................................................................................83 14.8 Clock Edge (RCR[6]) ..........................................................................................84 14.9 Burst Wrap (RCR[3]) ..........................................................................................84 14.10 Burst Length (RCR[2:0]).....................................................................................85 A B C Write State Machine States ......................................................................................86 Common Flash Interface (CFI) .................................................................................89 Ordering Information ...............................................................................................99 Datasheet 4 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Revision History Date 09/13/00 Revision -001 Initial Release Description 01/29/01 -002 Deleted 16-Mbit density Revised ADV#, Section 2.2 Revised Protection Registers, Section 4.16 Revised Program Protection Register, Section 4.18 Revised Example in First Access Latency Count, Section 5.0.2 Revised Figure 5, Data Output with LC Setting at Code 3 Added WAIT Signal Function, Section 5.0.3 Revised WAIT Signal Polarity, Section 5.0.4 Revised Data Output Configuration, Section 5.0.5 Added Figure 7, Data Output Configuration with WAIT Signal Delay Revised WAIT Delay Configuration, Section 5.0.6 Changed VCCQ Spec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2, Extended Temperature Operation Changed ICCS Spec from 15 µA to 18 µA in Section 8.4, DC Characteristics Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13 mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in Section 8.4, DC Characteristics Changed ICCWS Spec from 15 µA to 18 µA in Section 8.4, DC Characteristics Changed ICCES Spec from 15 µA to 18 µA in Section 8.4, DC Characteristics Changed tCHQX Spec from 5 ns to 3 ns in Section 8.6, AC Read Characteristics Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation Waveform Added Figure 26, WAIT Signal in Asynchronous Page Mode Read Operation Waveform Added Figure 27, WAIT Signal in Asynchronous Single Word Read Operation Waveform Revised Appendix E, Ordering Information Revised entire Section 4.10, Enhanced Factory Program Command (EFP) and Figure 6, Enhanced Factory Program Flowchart Revised Section 4.13, Protection Register Revised Section 4.15, Program Protection Register Revised Section 7.3, Capacitance, to include 128-Mbit specs Revised Section 7.4, DC Characteristics, to include 128-Mbit specs Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device specifications Added tVHGL Spec in Section 7.6, AC Read Characteristics Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device specifications Minor text edits New Sections Organization Added 16-Word Burst Feature Added Burst Suspend Section Revised Block Locking State Diagram Revised Active Power Section, Automatic Power Savings (APS) Section and Power-Up/Down Operation Section Revised Extended Temperature Operation Added 128 Mb DC Characteristics Table and AC Read Characteristics Table Revised Table 17. Test Configuration Component Values for Worst Case Speed Conditions Added 0.13 µm Product DC and AC Read Characteristics Revised AC Write Characteristics Added Read to Write and Write to Read Transition Waveforms Revised Reset Specifications Various text edits 06/12/01 -003 04/05/02 -004 November 2007 Order Number: 290701-18 Datasheet 5 Numonyx™ Wireless Flash Memory (W18) Date Revision Description Various text edits Updated Latency Count Section, including adding Latency Count Tables Added section 8.4 WAIT Function and WAIT Summary Table Updated Package Drawing and Dimensions Various text clarifications Removed Numonyx Burst Order Revised Table 10 “DC Current Characteristics” Various text edits Revised Table 22, Read Operations, tAPA Added note to table 15, Configuration Register Descriptions Added note to section 3.1.1, Read Updated Block-Lock Operations (Section 7.1 and Figure 11) Updated Table 21 (128 Mb ICCR) Updated Table 4 (WAIT behavior) Added QUAD+ ballout, package mechanicals, and order information Various text edits including latest product-naming convention Added 90 nm product line; Removed µBGA* package Added Page- and Burst-Mode descriptions; Minor text edits Fixed omitted text for Table 21, note 1 regarding max DC voltage on I/O pins Removed Extended I/O Supply Voltage for 90 nm products Minor text edits Updated the title and layout of the datasheet VCCQ Max. changed for 90 nm products Updated “Absolute Maximum Ratings” table Typical ICCS updated as 35 μ A Updated subtitle Typical ICCS updated as 22 Minor text edits 10/10/02 -005 11/12/02 01/14/03 -006 -007 03/21/03 -008 12/17/03 -009 02/12/04 -010 05/06/04 06/03/04 -011 -012 06/29/04 -013 01/21/05 -014 μA 07-Dec-2005 -015 Typical 90nm APS updated to 22 µA in Table 11, “DC Current Characteristics” on page 23. Updated 90nm VLKO to 0.7 V in Table 12, “DC Voltage Characteristics” on page 24. Product ordering information updated. Added line item RD48F1000W0YTQ0 and RD48F1000W0YBQ0, in QUAD+ ballout, 10x8x1.2 package. Removed extended range voltage specifications that are no longer supported. Removed tAVQV/tCHQV 80ns/14ns; Applied new template/format. Updated ordering information Applied Numonyx branding. December 2006 016 August 2007 November 2007 017 18 Datasheet 6 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 1.0 Introduction This datasheet contains information about the Numonyx™ Wireless Flash Memory (W18) device family. This section describes nomenclature used in the datasheet. Section 2.0 provides an overview of the W18 flash memory device. Section 6.0, Section 7.0, and Section 8.0 describe the electrical specifications for extended temperature product offerings. Ordering information can be found in Section C. The Numonyx™ Wireless Flash Memory (W18) device with flexible multi-partition dualoperation architecture, provides high-performance Asynchronous and Synchronous Burst reads. It is an ideal memory for low-voltage burst CPUs. Combining high read performance with flash memory intrinsic non-volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing redundant code memory from slow nonvolatile storage to faster execution memory. It reduces total memory requirement that increases reliability and reduces overall system power consumption and cost. The W18 device’s flexible multi-partition architecture allows program or erase to occur in one partition while reading from another partition. This allows for higher data write throughput compared to single-partition architectures and designers can choose code and data partition sizes. The dual-operation architecture allows two processors to interleave code operations while program and erase operations take place in the background. 1.1 Table 1: APS BBA CFI CUI DU EFP FDI NC OTP PBA RCR RWE RWW SCSP SRD VF BGA WSM Nomenclature Acronyms Automatic Power Savings Block Base Address Common Flash Interface Command User Interface Don’t Use Enhanced Factory Programming Flash Data Integrator No Connect One-Time Programmable Partition Base Address Read Configuration Register Read-While-Erase Read-While-Write Stacked Chip Scale Package Status Register Data Very-thin, Fine-pitch, Ball Grid Array Write State Machine November 2007 Order Number: 290701-18 Datasheet 7 Numonyx™ Numonyx™ Wireless Flash Memory (W18) 1.2 Table 2: “1.8 V” Set Pin and signal Word Signal Voltage Conventions Conventions Refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted) and “VPP = 12 V” refers to 12 V ±5%. Refers to registers means the bit is a logical 1 and cleared means the bit is a logical 0. Often used interchangeably to refer to the external signal connections on the package (ball is the term used for VF BGA). 2 bytes or 16 bits. Names are in all CAPS (see Section 4.2, “Signal Descriptions” on page 18.) Applied to the signal is subscripted for example VPP. Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these references, the following conventions have been adopted: Block Main block Parameter block Block Base Address (BBA) Partition Partition Base Address (PBA) Top partition Bottom partition Main partition Parameter partition Top parameter device Bottom parameter device (BPD) A group of bits (or words) that erase simultaneously with one block erase instruction. Contains 32-Kwords. Contains 4-Kwords. The first address of a block. A group of blocks that share erase and program circuitry and a common Status Register. The first address of a partition. For example, on a 32-Mbit top-parameter device partition number 5 has a PBA of 0x140000. Located at the highest physical device address. This partition may be a main partition or a parameter partition. Located at the lowest physical device address. This partition may be a main partition or a parameter partition. Contains only main blocks. Contains a mixture of main blocks and parameter blocks. Has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. This was formerly referred to as a Top-Boot device. Has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of that partition. This was formerly referred to as a Bottom-Boot Block flash device. Datasheet 8 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 2.0 Functional Overview This section provides an overview of the W18 device features and architecture. The W18 device provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability with high-performance synchronous and asynchronous reads on packagecompatible densities with a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks. The memory architecture for the W18 device consists of multiple 4-Mbit partitions, the exact number depending on device density. By dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. Burst reads can traverse partition boundaries, but user application code is responsible for ensuring that they don’t extend into a partition that is actively programming or erasing. Although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. A program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. After device power-up or reset, the W18 device defaults to asynchronous page-mode read configuration. Writing to the device’s Read Configuration Register (RCR) enables synchronous burst-mode read operation. In synchronous mode, the CLK input increments an internal burst address generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when data from the flash memory device is ready. In addition to its improved architecture and interface, the W18 device incorporates Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power designs. The EFP feature provides the fastest currently-available program performance, which can increase a factory’s manufacturing throughput. The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V. With the 1.8 V option, VCC and VPP can be tied together for a simple, ultralow-power design. In addition to voltage flexibility, the dedicated VPP input provides complete data protection when VPP ≤ VPPLK. This device (130 nm) allows I/O operation at voltages lower than the minimum VCCQ of 1.7 V. This Extended VCCQ range, 1.35 V – 1.8 V, permits even greater system design flexibility. A 128-bit protection register enhances the user’s ability to implement new security techniques and data protection schemes. Unique flash device identification and fraud-, cloning-, or content- protection schemes are possible through a combination of factoryprogrammed and user-OTP data cells. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. An additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status. The Command User Interface (CUI) is the system processor’s link to internal flash memory operation. A valid command sequence written to the CUI initiates device Write State Machine (WSM) operation that automatically executes the algorithms, timings, November 2007 Order Number: 290701-18 Datasheet 9 Numonyx™ Numonyx™ Wireless Flash Memory (W18) and verifications necessary to manage flash memory program and erase. An internal Status Register provides ready/busy indication results of the operation (success, fail, and so on). Three power-saving features– Automatic Power Savings (APS), standby, and RST# – can significantly reduce power consumption. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also resets the part to read-array mode (important for system-level reset), clears internal Status Registers, and provides an additional level of flash write protection. 2.1 Memory Map and Partitioning The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The device’s memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. Each block can be erased independently in block erase mode. Simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. See Table 3, “Bottom Parameter Memory Map” on page 11 and Table 4, “Top Parameter Memory Map” on page 12. The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit device has 32 partitions. Each device density contains one parameter partition and several main partitions. The 4-Mbit parameter partition contains eight 4Kword parameter blocks and seven 32-Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each. The bulk of the array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. . Datasheet 10 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Table 3: Bottom Parameter Memory Map Size (KW) Blk # 32-Mbit Blk # 64-Mbit Blk # 262 .. . 128-Mbit 7F8000-7FFFFF .. . 400000-407FFF 3F8000-3FFFFF .. . 200000-207FFF 1F8000-1FFFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 0C0000-0C7FFF 0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF Datasheet 11 Sixteen Partitions 32 .. . 32 135 Eight Partitions 32 .. . 134 .. . 3F8000-3FFFFF .. . 134 .. . 71 70 .. . 39 38 .. . 31 30 .. . 23 22 .. . 15 14 .. . 8 7 .. . 0 32 71 200000-207FFF Four Partitions 32 .. . 70 .. . 1F8000-1FFFFF .. . 70 .. . 1F8000-1FFFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 0C0000-0C7FFF 0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF Main Partitions 32 39 100000-107FFF 39 One Partition 32 .. . 38 .. . 0F8000-0FFFFF .. . 38 .. . 31 30 .. . 23 22 .. . 15 14 .. . 8 7 .. . 0 32 31 0C0000-0C7FFF One Partition 32 .. . 30 .. . 0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF 32 23 One Partition 32 .. . 22 .. . 15 14 .. . 8 7 .. . 0 32 32 Parameter One Partition 128 Mbit is not available at 90 nm. November 2007 Order Number: 290701-18 .. . 4 .. . 32 4 Numonyx™ Numonyx™ Wireless Flash Memory (W18) Table 4: Top Parameter Memory Map Size (KW) 4 .. . Blk # 70 .. . 32-Mbit 1FF000-1FFFFF .. . Blk # 134 .. . 64-Mbit 3FF000-3FFFFF .. . Blk # 262 .. . 128-Mbit 7FF000-7FFFFF .. . 7F8000-7F8FFF 7F0000-7F7FFF .. . 7C0000-7C7FFF 7B8000-7BFFFF .. . 780000-787FFF 778000-77FFFF .. . 740000-747FFF 738000-73FFFF .. . 700000-707FFF 6F8000-6FFFFF .. . 600000-607FFF 5F8000-5FFFFF .. . 400000-407FFF 3F8000-3FFFFF .. . 000000-007FFF Parameter Partition One Partition 4 32 .. . 63 62 .. . 1F8000-1F8FFF 1F0000-1F7FFF .. . 127 126 .. . 3F8000-3F8FFF 3F0000-3F7FFF .. . 255 254 .. . 248 247 .. . 240 239 .. . 232 231 .. . 224 223 .. . 192 191 .. . 128 127 .. . 0 32 56 1C0000-1C7FFF 120 3C0000-3C7FFF One Partition 32 .. . 55 .. . 1B8000-1BFFFF .. . 119 .. . 3B8000-3BFFFF .. . 380000-387FFF 378000-37FFFF .. . 340000-347FFF 338000-33FFFF .. . 300000-307FFF 2F8000-2FFFFF .. . 200000-207FFF 1F8000-1FFFFF .. . 000000-007FFF 32 48 18000-187FFF 112 One Partition 32 .. . 47 .. . 178000-17FFFF .. . 111 .. . 104 103 .. . 96 95 .. . 64 63 .. . 0 32 40 140000-147FFF One Partition 32 .. . 39 .. . 138000-13FFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 000000-007FFF Main Partitions 32 32 Four Partitions 32 .. . 31 .. . 0 32 Eight Partitions 32 .. . 32 32 .. . 32 128 Mbit is not available at 90 nm. Datasheet 12 Sixteen Partitions November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 3.0 3.1 Figure 1: Ball A1 Corner Package Information W18 — 90 nm Lithography 32- and 64-Mbit VF BGA Package Drawing Ball A1 Corner D S1 1 A B C E D E F G 2 3 4 5 6 7 8 A B C D E F G 8 7 6 5 4 3 2 1 S2 e b Top View - Bump Side Down A1 A2 A Bottom View - Ball Side U p Seating Plane Y Table 5: 32- and 64-Mbit VF BGA Package Dimensions Millimeters Dimension Symbol Min Nom 0.665 0.375 7.700 9.000 0.750 56 1.225 2.250 Max 1.000 0.425 7.800 9.100 0.100 1.325 2.350 Min 0.0059 0.0128 0.2992 0.3504 0.0443 0.0846 Nom 0.0262 0.0148 0.3031 0.3543 0.0295 56 0.0482 0.0886 Max 0.0394 0.0167 0.3071 0.3583 0.0039 0.0522 0.0925 A A1 A2 b D E [e] N Y S1 S2 0.150 0.325 7.600 8.900 1.125 2.150 Inches Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E November 2007 Order Number: 290701-18 Datasheet 13 Numonyx™ Numonyx™ Wireless Flash Memory (W18) 3.2 Figure 2: Ball A1 Corner W18 — 130 nm 32-, 64-, and 128-Mbit VF BGA Package Drawing Ball A1 Corn r e D S1 1 A B C E D E F G 2 3 4 5 6 7 8 A B C D E F G 8 7 6 5 4 3 2 1 S 2 e b Top View - Bump Side Down A1 A2 A Bottom View - Ball Side U p Seating Plane Y Table 6: 32-, 64-, and 128-Mbit VF BGA Package Dimensions Millimeters Dimension Symbol Min Nom 0.665 0.375 7.700 11.000 9.000 0.750 56 1.225 2.2875 2.250 Max 1.000 0.425 7.800 11.100 9.100 0.100 1.325 2.975 2.350 Min 0.0059 0.0128 0.2992 0.4291 0.3504 0.0443 0.1093 0.0846 Nom 0.0262 0.0148 0.3031 0.4331 0.3543 0.0295 56 0.0482 0.1132 0.0886 Max 0.0394 0.0167 0.3071 0.4370 0.3583 0.0039 0.0522 0.1171 0.0925 A A1 A2 b D D E [e] N Y S1 S1 S2 0.150 0.325 7.600 10.900 8.900 1.125 2.775 2.150 Inches Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32/64-Mbit) Package Body Width (128-Mbit) Package Body Length (32/64/128-Mbit) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64-Mbit) Corner to Ball A1 Distance Along D (128-Mbit) Corner to Ball A1 Distance Along E (32/64/128-Mbit) Datasheet 14 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Figure 3: 128-Mbit QUAD+ Package Drawing A1 Index Mark 1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E e 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M S1 Top View - Ball Down A2 A1 Bottom View - Ball Up A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 9.900 7.900 Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600 Notes Min 0.0079 Inches Nom Max 0.0472 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 1.100 0.500 0.100 1.300 0.700 0.0433 0.0197 0.0039 0.0512 0.0276 November 2007 Order Number: 290701-18 Datasheet 15 Numonyx™ Numonyx™ Wireless Flash Memory (W18) 4.0 4.1 Ballout and Signal Descriptions Signal Ballout The W18 device is available in a 56-ball VF BGA and µBGA Chip Scale Package with 0.75 mm ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. Figure 4 shows the device ballout for the VF BGA package. Figure 5 shows the device ballout for the QUAD+ package. Figure 4: 1 56-Ball VF BGA Ballout 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A11 B A12 C A13 D A15 E VCCQ F VSS G DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7 DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE# OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0 A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ A14 WAIT A16 DQ12 WP# A22 A1 A1 A22 WP# DQ12 A16 WAIT A14 A15 A10 A21 ADV# WE# A19 A7 A2 A2 A7 A19 WE# ADV# A21 A10 A13 A9 A20 CLK RST# A17 A5 A3 A3 A5 A17 RST# CLK A20 A9 A12 A8 VSS VCC VPP A18 A6 A4 A4 A6 A18 VPP VCC VSS A8 A11 A B C D E F G Top View - Ball Side Down Complete Ink Mark Not Shown Bottom View - Ball Side Up Notes: 1. On lower density devices, upper address balls can be treated as NC.; for example, 32-Mbit density, A21 and A22 are NC). 2. See Section 3.0, “Package Information” on page 13 for mechanical specifications for the package. Datasheet 16 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Figure 5: 88-Ball (80 Active Balls) QUAD+ Ballout 1 2 3 4 5 6 7 8 A B DU DU DU DU A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 D A3 A17 A24 F-VPP, F-VPEN R-WE# P1-CS# A9 A13 E A2 A7 A25 F-WP# ADV# A20 A10 A15 F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 G A0 D8 D2 D10 D5 D13 WAIT F2-CE# H R-OE# D0 D1 D3 D12 D14 D7 F2-OE# J S-CS1# F1-OE# D9 D11 D4 D6 D15 VCCQ K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE L VSS VSS DU VCCQ F1-VCC VSS VSS VSS DU VSS DU M DU Top View - Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific Notes: 1. Unused upper address balls can be treated as NC; for example, 128-Mbit device, A[25:23] are not used. 2. See Section 3.0, “Package Information” on page 13 f or the mechanical specifications for the package. November 2007 Order Number: 290701-18 Datasheet 17 Numonyx™ Numonyx™ Wireless Flash Memory (W18) 4.2 Signal Descriptions Table 7 describes the signals used on the VF BGA package. Table 8 describes the signals used on the QUAD+ package. Table 7: Symbol A[22:0] D[15:0] Signal Descriptions - VF BGA Package Type Input Input/ Output Name and Function ADDRESS INPUTS: For memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, protection register, and configuration code reads. Data pins float when the chip or outputs are deselected. Data is internally latched during writes. ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous read operations, all addresses are latched on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first. CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps. De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z. CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and increments an internal address generator. During synchronous read operations, addresses are latched on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first. OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle. When OE# is deasserted, data outputs are placed in a high-impedance state. RESET: When low, RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. de-asserting RST# enables normal operation and places the device in asynchronous read-array mode. WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-stated if CE# is deasserted. WAIT is not gated by OE#. WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the rising edge of WE#. WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See Section 13.1, “Block Lock Operations” on page 71 for details on block locking. ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP ≤ VPPLK . Block erase and program at invalid VPP voltages should not be attempted. Set VPP = VCC f or in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1 min to perform in-system flash modification. VPP may be 0 V during read operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 12 V may reduce block cycling capability. DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC voltages should not be attempted. OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to VCC. GROUND: Pins for all internal device circuitry must be connected to system ground. OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied directly to VSS. DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or other pins and must be floated. NO CONNECT: No internal connection; can be driven or floated. ADV# Input CE# Input CLK Input OE# Input RST# Input WAIT Output WE# Input WP# Input VPP Power VCC VCCQ VSS VSSQ DU NC Power Power Power Power — — Datasheet 18 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Table 8: Symbol Signal Descriptions - QUAD+ Package (Sheet 1 of 2) Type Description ADDRESS INPUTS: Inputs for all die addresses during read and write operations. —256-Mbit Die : AMAX= A23 —128-Mbit Die : AMAX = A22 —64-Mbit Die : AMAX = A21 —32-Mbit Die : AMAX = A20 —8-Mbit Die : AMAX = A18 A0 is the lowest-order 16-bit wide address. A[25:24] denote high-order addresses reserved for future device densities. DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes on the flash device. FLASH CHIP ENABLE: Low-true input. F[3:1]-CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. F1-CE# selects or deselects flash die #1; F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two flash dies. SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively). When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked combinations without SRAM die. PSRAM CHIP SELECT: Low-true input. When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This ball is an RFU on stacked combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM dies. This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM. FLASH OUTPUT ENABLE: L ow-true input. Fx-OE# low enables the selected flash’s output buffers. F[2:1]-OE# high disables the selected flash’s output buffers, placing them in High-Z. F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked combinations with two or three flash die and is RFU on stacked combinations with only one flash die. RAM OUTPUT ENABLE: Low-true input. R-OE# low enables the selected RAM’s output buffers. R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z. R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only stacked combinations. FLASH WRITE ENABLE: L ow-true input. F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of FWE#. RAM WRITE ENABLE: L ow-true input. R-WE# controls writes to the selected RAM die. R-WE# is available on stacked combinations with PSRAM or SRAM die and is an RFU on flash-only stacked combinations. CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and increments the internal address generator. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, addresses are latched on the rising edge ADV#, or are continuously flowthrough when ADV# is kept asserted. A[MAX:MIN] Input D[15:0] Input/ Output F[3:1]-CE# Input S-CS1# S-CS2 Input P[2:1]-CS# Input F[2:1]-OE# Input R-OE# Input F-WE# Input R-WE# Input CLK Input November 2007 Order Number: 290701-18 Datasheet 19 Numonyx™ Numonyx™ Wireless Flash Memory (W18) Table 8: Signal Descriptions - QUAD+ Package (Sheet 2 of 2) WAIT: Output signal. Indicates invalid data during synchronous array or non-array flash reads. Read Configuration Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is deasserted; WAIT is not gated by F-OE#. • In synchronous array or non-array flash read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous flash page read, and all flash write modes, WAIT is asserted. FLASH WRITE PROTECT: Low-true input. F-WP# enables/disables the lock-down protection mechanism of the selected flash die. • F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. • F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. ADDRESS VALID: Low-true input. During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are continuously flow-through when ADV# is kept asserted. RAM UPPER / LOWER BYTE ENABLES: Low-true input. During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and RLB# low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on flash-only stacked combinations. FLASH RESET: L ow-true input. F-RST# low initializes flash internal circuitry and disables flash operations. F-RST# high enables flash operation. Exit from reset places the flash in asynchronous read array mode. P-Mode (PSRAM Mode): Low-true input. P-Mode is used to program the Configuration Register, and enter/exit Low Power Mode of PSRAM die. P-Mode is available on stacked combinations with asynchronous-only PSRAM die. P-CRE (PSRAM Configuration Register Enable): High-true input. P-CRE is high, write operations load the refresh control register or bus control register. P-CRE is applicable only on combinations with synchronous PSRAM die. P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die. FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Erase / program operations at invalid F-VPP (F-VPEN) voltages should not be attempted. Refer to flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products. FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-VCC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked combinations with only one flash die. SRAM POWER SUPPLY: Supplies power for SRAM operations. S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations without SRAM die. PSRAM POWER SUPPLY: Supplies power for PSRAM operations. P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations without PSRAM die. DEVICE I/O POWER: Supply power for the device input and output buffers. DEVICE GROUND: Connect to system ground. Do not float any VSS connection. RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact Numonyx regarding the use of balls designated RFU. DO NOT USE: Do not connect to any other signal, or power supply; must be left floating. WAIT Output F-WP# Input ADV# Input R-UB# R-LB# Input F-RST# Input P-Mode, P-CRE Input F-VPP, F-VPEN Power F[2:1]-VCC Power S-VCC Power P-VCC VCCQ VSS RFU DU Power Power Power — — Datasheet 20 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 5.0 5.1 Warning: Maximum Ratings and Operating Conditions Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Notice: This datasheet contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Table 9: Absolute Maximum Ratings Parameter Temperature under Bias Storage Temperature Voltage on Any Pin (except VCC , VCCQ, VPP) VPP Voltage VCC and VCCQ Voltage Output Short Circuit Current Notes: 1. Specified voltages are with respect to VSS. 2. During transitions, this level may: Maximum Rating –40 °C to +85 °C –65 °C to +125 °C Notes –0.5 V to +2.45 V –0.2 V to +13.1 V –0.2 V to +2.45 V 100 mA 1,2 1,3,4 1,2 5 3. 4. 5. Maximum DC voltage on VPP may overshoot to +14.6 V for periods < 20 ns. VPP program voltage is normally VPP1. VPP can be 12 V ± 0.6 V for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. Output shorted for no more than one second. No more than one output shorted at a time. (130 nm) Undershoot –2.0 V for periods < 20 ns and overshoot to VCCQ +2.0 V for periods < 20 ns (90 nm) Undershoot –1.0 V for periods < 20 ns and overshoot to VCCQ +1.0 V for periods < 20 ns. 5.2 Warning: Operating Conditions Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions”may affect device reliability. Table 10: Extended Temperature Operation (Sheet 1 of 2) Symbol TA VCC Parameter 1 Operating Temperature VCC Supply Voltage I/O Supply Voltage (90 nm) VCCQ VPP1 VPP2 tPPH I/O Supply Voltage (130 nm) VPP Voltage Supply (Logic Level) FactoryProgramming VPP Maximum VPP Hours VPP = 12 V Min –40 1.7 1.7 1.7 0.90 11.4 Nom 25 1.8 1.8 1.8 1.80 12.0 Max 85 1.95 1.95 2.24 1.95 12.6 80 Hours Unit °C V 2 2 2 1 1 1 Note November 2007 Order Number: 290701-18 Datasheet 21 Numonyx™ Numonyx™ Wireless Flash Memory (W18) Table 10: Extended Temperature Operation (Sheet 2 of 2) Symbol Block Erase Cycles Parameter1 Main and Parameter Blocks Main Blocks Parameter Blocks VPP ≤ VCC VPP = 12 V VPP = 12 V Min 100,000 Nom Max 1000 2500 Cycles Unit Note 1 1 1 Notes: 1. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks at extended temperatures and 2500 cycles on parameter blocks at extended temperatures. 2. Contact your Numonyx field representative for VCC/VCCQ operations down to 1.65 V. Datasheet 22 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 6.0 6.1 Note: Electrical Specifications DC Current Characteristics Specifications are for 130 nm and 90 nm devices unless otherwise stated; the 128 Mbit density is supported ONLY on 90 nm. Table 11: DC Current Characteristics (Sheet 1 of 2) VCCQ = 1.8 V Symbol Parameter (1) 32/64-Mbit Typ Max ±1 128-Mbit Typ — Max ±1 Unit Test Condition Note ILI Input Load — µA VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQ Max CE# = VCC RST# =VCCQ VCC = VCCMax VCCQ = VCCQ Max CE# = VSSQ RST# =VCCQ All other inputs =VCCQ or VSSQ 4 Word Read Burst length = 4 Burst length = 8 Burst length =16 Burst length = Continuous Burst length = 4 Burst length = 8 Burst length = 16 Burst length = Continuous Burst length = 4 Burst length = 8 Burst length = 16 Burst length = Continuous 8 ILO 130 nm ICCS 90 nm ICCS 130 nm ICCAPS 90 nm ICCAPS Output Leakage D[15:0] — ±1 — ±1 µA 8 VCC Standby 22 8 APS 22 Asynchronous Page Mode f=13 MHz 50 50 50 50 8 — 8 — 70 µA — 70 µA — 9 10 3 6 6 13 14 18 20 16 18 22 25 17 20 25 30 40 15 40 4 6 8 11 11 7 10 12 13 — — — — 18 8 18 7 13 14 19 20 16 18 22 25 — — — — 40 15 40 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 3 ICCR Average VCC Read Synchronous CLK = 40 MHz 8 10 11 7 3 Synchronous CLK = 54 MHz 10 12 13 8 3 ICCR Average VCC Read Synchronous CLK = 66 MHz 11 14 16 3, 4 ICCW VCC Program 18 8 18 VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP = VPP1, Block Erase in Progress VPP = VPP2, Block Erase in Progress 4,5,6 ICCE VCC Block Erase 8 15 8 15 mA 4,5,6 November 2007 Order Number: 290701-18 Datasheet 23 Numonyx™ Numonyx™ Wireless Flash Memory (W18) Table 11: DC Current Characteristics (Sheet 2 of 2) VCCQ = 1.8 V Symbol Parameter (1) 32/64-Mbit Typ Max 50 50 50 50 128-Mbit Typ 5 — 5 — Max 25 — 25 — Unit Test Condition Note 130nm ICCWS 90nm ICCWS 130nm ICCES 90nm ICCWS IPPS (IPPWS, IPPES) IPPR IPPW 8 VCC Program Suspend 22 8 VCC Erase Suspend 22 VPP Standby VPP Program Suspend VPP Erase Suspend VPP Read VPP Program µA µA µA µA CE# = VCC, Program Suspended 7 CE# = VCC, Erase Suspended 7 0.2 2 0.05 8 0.05 8 5 15 0.10 22 0.10 22 0.2 2 0.05 16 0.05 8 5 15 0.10 37 0.10 22 µA µA mA VPP VCC the input load current increases to 10 µA max. 9. ICCS is the average current measured over any 5 ms time interval 5 μs after a CE# de-assertion. 10. Refer to section Section 8.2, “Automatic Power Savings (APS)” on page 46 for ICCAPS measurement details. 6.2 Note: DC Voltage Characteristics Specifications are for 130 nm and 90 nm devices unless otherwise stated; the 128 Mbit density is supported ONLY on 90 nm. Table 12: DC Voltage Characteristics (Sheet 1 of 2) VCCQ= 1.8 V Symbol Parameter 32/64-Mbit Min VIL VIH VOL Input Low Input High Output Low 0 VCCQ – 0.4 Max 0.4 VCCQ 0.1 128-Mbit Min 0 VCCQ – 0.4 Max 0.4 VCCQ 0.1 V V V VCC = VCCMin VCCQ = VCCQ Min IOL = 100 µA 2 2 Unit Test Condition Notes Datasheet 24 November 2007 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) Table 12: DC Voltage Characteristics (Sheet 2 of 2) V CCQ= 1.8 V Symbol Parameter 32/64-Mbit Min VOH VPPLK VLKO VILKOQ Output High VPP Lock-Out VCC Lock (130nm) VCC Lock (90nm) VCCQ L ock VCCQ – 0.1 1.0 0.7 0.9 Max 0.4 128-Mbit Min VCCQ – 0.1 1.0 0.9 Max 0.4 V V V V V VCC = VCC Min VCCQ = VCCQMin IOH = –100 µA 3 4 Unit Test Condition Notes Notes: 1. VCCQ = 1.35 V - 1.8V is available on 130 nm devices only. 2. VIL can undershoot to –1.0 V for durations of 2 ns or less and VIH can overshoot to VCCQ+1.0 V for durations of 2 ns or less. 3. VPP