Numonyx™ StrataFlash® Cellular Memory (M18)
Datasheet
Product Features
High-Performance Read, Program and Erase — 96 ns initial read access — 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output — 133 MHz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output — 8-, 16-, and continuous-word synchronous-burst Reads — Programmable WAIT configuration — Customer-configurable output driver impedance — Buffered Programming: 2.0 µs/Word (typ), 512-Mbit 65 nm; Block Erase: 0.9 s per block (typ) — 20 µs (typ) program/erase suspend Architecture — 16-bit wide data bus — Multi-Level Cell Technology — Symmetrically-Blocked Array Architecture — 256-Kbyte Erase Blocks — 1-Gbit device: Eight 128-Mbit partitions — 512-Mbit device: Eight 64-Mbit partitions — 256-Mbit device: Eight 32-Mbit partitions. — 128-Mbit device: Eight 16-Mbit partitions. — Read-While-Program and Read-While-Erase — Status Register for partition/device status — Blank Check feature Quality and Reliability — Expanded temperature: –30 °C to +85 °C — Minimum 100,000 erase cycles per block — ETOX™ X Process Technology (65 nm) — ETOX™ IX Process Technology (90 nm) Power — Core voltage: 1.7 V - 2.0 V — I/O voltage: 1.7 V - 2.0 V — Standby current: 60 µA (typ) for 512-Mbit, 65 nm — Deep Power-Down mode: 2 µA (typ) — Automatic Power Savings mode — 16-word synchronous-burst read current: 23 mA (typ) @ 108 MHz; 24 mA (typ) @ 133 MHz Software — Numonyx™ Flash Data Integrator (Numonyx™ FDI) optimized — Basic Command Set and Extended Command Set compatible — Common Flash Interface Security — OTP Registers: 64 unique pre-programmed bits 2112 user-programmable bits — Absolute write protection with VPP = GND — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down Density and Packaging — Density: 128-, 256-, and 512-Mbit, and 1Gbit — Address-data multiplexed and nonmultiplexed interfaces — x16D (105-ball) Flash SCSP — x16C (107-ball) Flash SCSP — 0.8 mm pitch lead-free solder-ball
Order Number: 309823-11 April 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal L ines and D isc laim er s
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the Numonyx website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet 2
April 2008 Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
Contents
1.0 Introduction .............................................................................................................. 8 1.1 Document Purpose .............................................................................................. 8 1.2 Nomenclature ..................................................................................................... 8 1.3 Acronyms........................................................................................................... 8 1.4 Conventions ....................................................................................................... 9 Functional Description ............................................................................................. 10 2.1 Product Overview .............................................................................................. 10 2.2 Configuration and Memory Map ........................................................................... 11 2.3 Device ID ......................................................................................................... 12 Package Information ............................................................................................... 13 Ballouts and Signal Descriptions .............................................................................. 23 4.1 Ballouts, x16D .................................................................................................. 23 4.1.1 x16D (105-Ball) Ballout, Non-Mux ............................................................ 23 4.1.2 x16D (105-Ball) Ballout, AD-Mux.............................................................. 24 4.1.3 x16D Mux (105-Ball) Ballout, AA/D Mux .................................................... 25 4.2 Signal Descriptions, x16D................................................................................... 26 4.3 Ballouts, x16C .................................................................................................. 29 4.3.1 x16C (107-Ball) Ballout, Non-Mux ............................................................ 29 4.3.2 x16C (107-Ball) Ballout, AD-Mux .............................................................. 31 4.3.3 x16C (107-Ball) Ballout, AA/D-Mux ........................................................... 32 4.4 Signal Descriptions x16C .................................................................................... 33 4.5 Ballouts, x16 Split Bus ....................................................................................... 37 4.5.1 x16 Split Bus (165-Ball) Ballout, Non-Mux ................................................. 37 4.6 Signal Descriptions, x16 Split Bus........................................................................ 38 Maximum Ratings and Operating Conditions ............................................................ 42 5.1 Absolute Maximum Ratings................................................................................. 42 5.2 Operating Conditions ......................................................................................... 42 Electrical Characteristics ......................................................................................... 43 6.1 Initialization ..................................................................................................... 43 6.1.1 Power-Up/Down Characteristics................................................................ 43 6.1.2 Reset Characteristics .............................................................................. 43 6.1.3 Power Supply Decoupling ........................................................................ 43 6.2 DC Current Specifications ................................................................................... 44 6.3 DC Voltage Specifications ................................................................................... 46 6.4 Capacitance...................................................................................................... 47 NOR Flash AC Characteristics................................................................................... 48 7.1 AC Test Conditions ............................................................................................ 48 7.2 Read Specifications............................................................................................ 49 7.2.1 Read Timing Waveforms.......................................................................... 52 7.2.2 Timings: Non-Mux Device, Async Read ...................................................... 53 7.2.3 Timings: Non-Mux Device, Sync Read ....................................................... 54 7.2.4 Timings: AD-Mux Device, Async Read ....................................................... 57 7.2.5 Timings: AD-Mux Device, Sync Read ......................................................... 58 7.3 Write Specifications ........................................................................................... 60 7.3.1 Write Timing Waveforms ......................................................................... 61 7.3.2 Timings: Non Mux Device ........................................................................ 62 7.3.3 Timings: AD-Mux Device ......................................................................... 65 7.4 Program and Erase Characteristics....................................................................... 68
2.0
3.0 4.0
5.0
6.0
7.0
April 2008 Order Number: 309823-11
Datasheet 3
Numonyx™ StrataFlash® Cellular Memory (M18)
7.5 7.6 8.0
Reset Specifications ...........................................................................................69 Deep Power Down Specifications..........................................................................69
NOR Flash Bus Interface ..........................................................................................71 8.1 Bus Reads ........................................................................................................71 8.1.1 Asynchronous single-word reads ...............................................................72 8.1.2 Asynchronous Page Mode (Non-multiplexed devices only) ............................72 8.1.3 Synchronous Burst Mode .........................................................................72 8.2 Bus Writes ........................................................................................................73 8.3 Reset ...............................................................................................................73 8.4 Deep Power-Down .............................................................................................73 8.5 Standby ...........................................................................................................74 8.6 Output Disable ..................................................................................................74 8.7 Bus Cycle Interleaving ........................................................................................74 8.7.1 Read Operation During Program Buffer fill ..................................................75 8.8 Read-to-Write and Write-to-Read Bus Transitions...................................................75 8.8.1 Write to Asynchronous read transition .......................................................75 8.8.2 Write to synchronous read transition .........................................................75 8.8.3 Asynchronous/Synchronous read to write transition.....................................75 8.8.4 Bus write with active clock .......................................................................75 NOR Flash Operations ..............................................................................................76 9.1 Status Register..................................................................................................76 9.1.1 Clearing the Status Register .....................................................................77 9.2 Read Configuration Register ................................................................................77 9.2.1 Latency Count ........................................................................................78 9.3 Enhanced Configuration Register..........................................................................79 9.3.1 Output Driver Control ..............................................................................80 9.3.2 Programming the ECR .............................................................................80 9.4 Read Operations ................................................................................................81 9.4.1 Read Array ............................................................................................81 9.4.2 Read Status Register...............................................................................82 9.4.3 Read Device Information .........................................................................82 9.4.4 CFI Query ..............................................................................................83 9.5 Programming Modes ..........................................................................................83 9.5.1 Control Mode .........................................................................................84 9.5.2 Object Mode ..........................................................................................85 9.6 Programming Operations ....................................................................................88 9.6.1 Single-Word Programming .......................................................................88 9.6.2 Buffered Programming ............................................................................89 9.6.3 Buffered Enhanced Factory Programming (BEFP).........................................90 9.7 Block Erase Operations .......................................................................................92 9.8 Blank Check Operation .......................................................................................93 9.9 Suspend and Resume .........................................................................................93 9.10 Simultaneous Operations ....................................................................................95 9.11 Security ...........................................................................................................95 9.11.1 Block Locking .........................................................................................95 9.11.2 One-Time Programmable (OTP) Registers ..................................................97 9.11.3 Global Main-Array Protection ....................................................................99
9.0
10.0 Device Command Codes ......................................................................................... 100 11.0 Flow Charts ............................................................................................................ 101 12.0 Common Flash Interface ........................................................................................ 110 12.1 Query Structure Output .................................................................................... 110 12.2 Block Status Register ....................................................................................... 111
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April 2008 Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
12.3 12.4 12.5 A B C
CFI Query Identification String .......................................................................... 111 Device Geometry Definition .............................................................................. 113 Numonyx-Specific Extended Query Table ............................................................ 114
13.0 Next State ............................................................................................................. 120 AADM Mode ........................................................................................................... 128 Additional Information .......................................................................................... 136 Ordering Information ............................................................................................ 136
April 2008 Order Number: 309823-11
Datasheet 5
Numonyx™ StrataFlash® Cellular Memory (M18)
Revision History
Date 14-April-06 28-April-06
Revision 001 002
Description Initial Release Updated the template (naming and branding). On the cover page, changed BEFP from 1.6 µs/byte (typ) to 3.2 µs/Word (typ). Correced the BEFP on the cover page to read 3.2 µs/Word and synchronized the BEFP on the cover with that in S ection 7.4, “Program and Erase Characteristics” on page 68. Added Figure 1, “Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)” on page 14 and Figure 5, “Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2 mm)” on page 18. Added the following line item part numbers: —PF48F6000M0Y0BE —PF38F6070M0Y0BE —PF38F6070M0Y0VE —PF48F6000M0Y1BE Removed information on the 90 nm Extended Flash Array (EFA) feature that is no longer supported. Revised to include 65 nm, 1-Gbit device information. Moved sections for Device ID, Additional Information, and Order Information to Functional Description chapter. Created a separate M18 Developer’s Manual to include the following information: —Bus Interface —Flash Operations —Device Command Codes —Flow Charts —Common Flash Interface —Next State Table Removed line item PF5566MMY0C0 (512+512 M18 + 128 + 128 PSRAM) and its accompanying package (8x11x1.4, x16C 107 ball). Added the following line items: —PF48F6000M0Y0BE, 65 nm —PF38F6070M0Y0BE, 65 nm —PF38F4060M0Y0B0 —PF58F0031M0Y1BE, 65 nm —PF38F6070M0Y0C0, 65 nm —PF38F4060M0Y0C0 —PF38F4060M0Y1C0 —PF38F6070M0Y0VE, 65 nm Added the following packages to support new line items: —8x10x1.0, x16D 105 ball —11x15x1.2, x16D 105 ball —11x11x1.2, x16C 107 ball —8x10x1.2, x16C 107 ball —10x11x1.2, x16SB 165 ball Updated line item information. Added the following line items and package as applicable: PF48F4000M0Y0CE, 8x10x1.0 x16C Merged the Developer Manual and Datasheet content into a single document. Updated the Performance specifications for 133MHz Capulet 1G improvements. Updated timing diagrams in AC Characteristics section.
20-June-06
003
October 2006
004
November 2006
005
November 2006 February 2007 June 2007 March 2008 March 2007
006 007 008 009 008
Datasheet 6
April 2008 Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
Date
Revision
Description Added note stating the value of RCR8 in timing diagrams inSection 7.2.1, “Read Timing Waveforms” on page 52. Resized several timing diagrams in AC Characteristics section. Updated timing diagrams Figure 31, “Async Read to Write (Non-Mux)” on page 62, Figure 36, “Async Read to Write (AD-Mux)” on page 66 and Figure 37, “Write to Async Read (AD-Mux)” on page 66 Updated Program performance specs with Capulet improved performance values. Applied Numonyx branding.
July 2007
009
March 2008 April 2008
010 11
April 2008 Order Number: 309823-11
Datasheet 7
Numonyx™ StrataFlash® Cellular Memory (M18)
1.0
Introduction
Numonyx™ StrataFlash® Cellular Memory is the sixth generation Numonyx™ StrataFlash® memory with multi-level cell (MLC) technology. It provides highperformance, low-power synchronous-burst read mode and asynchronous read mode at 1.8 V. It features flexible, multi-partition read-while-program and read-while-erase capability, enabling background programming or erasing in one partition simultaneously with code execution or data reads in another partition. The eight partitions allow flexibility for system designers to choose the size of the code and data segments. The Numonyx™ StrataFlash® Cellular Memory is manufactured using Intel* 65 nm ETOX* X and 90 nm ETOX* IX process technology and is available in industrystandard chip-scale packaging.
1.1
Document Purpose
This document describes the specifications of the Numonyx™ StrataFlash® Cellular Memory device.
1.2
Table 1:
Nomenclature
Definition of Terms
Term Definition Refers to VCC and VCCQ voltage range of 1.7 V to 2.0 V A group of bits that erase with one erase command A group of 256-KB blocks used for storing code or data A group of blocks that share common program and erase circuitry and command status register An aligned 1-KB section within the main array A 32-byte section within the programming region 8 bits 2 bytes = 16 bits 1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes
1.8 V Block Main Array Partition Programming Region Segment Byte Word Kb KB KW Mb MB
1.3
Table 2:
Acronyms
List of Acronyms
Meaning Automatic Power Savings Common Flash Interface Don’t Use Enhanced Configuration Register (Flash)
Acronym APS CFI DU ECR
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April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 2:
List of Acronyms
Meaning EPROM Tunnel Oxide Numonyx™ Flash Data Integrator Read Configuration Register (Flash) Reserved for Future Use Stacked Chip Scale Package
Acronym ETOX FDI RCR RFU SCSP
1.4
Table 3:
Conventions
Datasheet Conventions
Meaning Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1]. When referring to a signal or package-connection name, the notation used is VCC. When referring to a voltage level, the notation used is subscripted such as VCC . This term is used interchangeably throughout this document to denote either a particular die, or all die in the package. This is the method used to refer to more than one chip-enable or output enable. When each is referred to individually, the reference is F1-CE# and F1-OE# (for die #1), and F2-CE# and F2OE# (for die #2). When referencing flash memory signals, the notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with “P-” (for example, PVCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with “S-” (for example, SVCC or S-VCC). P-VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM. Used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between two or more RAM die. R-OE#, R-LB#, R-UB# and R-WE# are RFU for stacked combinations that do not include PSRAM or SRAM. Denotes 16-bit hexadecimal numbers Denotes 32-bit hexadecimal numbers
Convention Group Membership Brackets VCC vs. VCC Device F[3:1]-CE#, F[2:1]-OE#
F-VCC P-VCC, S-VCC
R-OE#, R-LB#, R-UB#, R-WE# 00FFh 00FF 00FFh
April 2008 309823-10
Datasheet 9
Numonyx™ StrataFlash® Cellular Memory (M18)
2.0
2.1
Functional Description
Product Overview
The Numonyx™ StrataFlash® Cellular Memory (M18) device provides high read and write performance at low voltage on a 16-bit data bus. The flash memory device has a multi-partition architecture with read-while-program and read-while-erase capability. The device supports synchronous burst reads up to 108 MHz using ADV# and CLK address-latching on some litho/density combinations and up to 133 MHz using CLK address-latching only on some litho/density combinations. It is listed below in the following table.
Table 4:
M18 Product Litho/Density/Frequency Combinations
Density (Mbit) 256 512 128 256 Supports frequency up to (MHz) 133 108 133 133 133 108 133 Sync read address-latching CLK-latching ADV#- and CLK-latching CLK-latching CLK-latching CLK-latching ADV#- and CLK-latching CLK-latching
Litho (nm) 90
65
512 1024 1024
In continuous-burst mode, a data Read can traverse partition boundaries. Upon initial power-up or return from reset, the device defaults to asynchronous arrayread mode. Synchronous burst-mode reads are enabled by programming the Read Configuration Register. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. Designed for low-voltage applications, the device supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. VCC and VPP can be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Status Register provides status and error conditions of erase and program operations. One-Time-Programmable (OTP) registers allow unique flash device identification that can be used to increase flash content security. Also, the individual block-lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array. The flash memory device offers three power savings features: • Automatic Power Savings (APS) mode: The device automatically enters APS following a read-cycle completion. • Standby mode: Standby is initiated when the system deselects the device by deasserting CE#.
Datasheet 10
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
• Deep Power-Down (DPD) mode: DPD provides the lowest power consumption and is enabled by programming in the Enhanced Configuration Register. DPD is initiatied by asserting the DPD pin.
2.2
Configuration and Memory Map
The Numonyx™ StrataFlash® Cellular Memory device features a symmetrical block architecture. The flash device main array is divided as follows: • The main array of the 128-Mbit device is divided into eight 16-Mbit partitions. Each parition is divided into eight 256-KByte blocks: 8 x 8 = 64 blocks in the main array of a 128-Mbit device. • The main array of the 256-Mbit device is divided into eight 32-Mbit partitions. Each parition is divided into sixteen 256-KByte blocks: 8 x 16 = 128 blocks in the main array of a 256-Mbit device. • The main array of the 512-Mbit device is divided into eight 64-Mbit partitions. Each parition is divided into thirty-two 256-KByte blocks: 8 x 32 = 256 blocks in the main array of a 256-Mbit device. • The main array of the 1-Gbit device is divided into eight 128-Mbit partitions. Each parition is divided into sixty-four 256-KByte blocks: 8 x 64 = 512 blocks in the main array of a 1-Gbit device. Each block is divided into as many as two-hundred-fifty-six 1-KByte programming regions. Each region is divided into as many as thirty-two 32-Byte segments.
Table 5:
Partition
Main Array Memory Map (Sheet 1 of 2)
128-Mbit Device Mbit Blk # 63 ... Address Range 07E000007FFFFF ... 32 Mbit 256-Mbit Device Blk # 127 ... Address Range 0FE00000FFFFFF ... 64 Mbit 512-Mbit Device Blk # 255 ... Address Range 1FE00001FFFFFF ... 128 Mbit 1-Gbit Device Blk # 511 ... Address Range 3FE00003FFFFFF ... 3800000381FFFF 37E000037FFFFF ... 3000000301FFFF 2FE00002FFFFFF ... 2800000281FFFF 27E000027FFFFF ... 2000000201FFFF Datasheet 11
7
16
56 55 ... 6 16
0700000071FFFF 06E000006FFFFF ... 32
112 111 ...
0E000000E1FFFF 0DE00000DFFFFF ... 64
224 223 ...
1C000001C1FFFF 1BE00001BFFFFF ... 128
448 447 ... 384 383 ... 320 319 ... 256 128 128
48 47 ... 5 16
0600000061FFFF 05E000005FFFFF ... 32
96 95 ...
0C000000C1FFFF 0BE00000BFFFFF ... 64
192 191 ...
1800000181FFFF 17E000017FFFFF ... 1400000141FFFF 13E000013FFFFF ... 1000000101FFFF
40 39 ... 4 16
0500000051FFFF 04E000004FFFFF ... 32
80 79 ...
0A000000A1FFFF 09E000009FFFFF ... 64
160 159 ... 128
32
0400000041FFFF
64
0800000081FFFF
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 5:
Partition
Main Array Memory Map (Sheet 2 of 2)
128-Mbit Device Mbit Blk # 31 ... Address Range 03E000003FFFFF ... 32 Mbit 256-Mbit Device Blk # 63 ... Address Range 07E000007FFFFF ... 64 Mbit 512-Mbit Device Blk # 127 ... Address Range 0FE00000FFFFFF ... 128 Mbit 1-Gbit Device Blk # 255 ... Address Range 1FE00001FFFFFF ... 1800000181FFFF 17E000017FFFFF ... 1000000101FFFF 0FE00000FFFFFF ... 0800000081FFFF 07E000007FFFFF ... 0000000001FFFF April 2008 309823-10
3
16
24 23 ... 2 16
0300000031FFFF 02E000002FFFFF ... 32
48 47 ...
0600000061FFFF 05E000005FFFFF ... 64
96 95 ...
0C000000C1FFFF 0BE00000BFFFFF ... 128
192 191 ... 128 127 ... 64 63 ... 0 8900 8903 8901 8904 887E 8881 88B0 88B1 128 128
16 15 ... 1 16
0200000021FFFF 01E000001FFFFF ... 32
32 31 ...
0400000041FFFF 03E000003FFFFF ... 64
64 63 ...
0800000081FFFF 07E000007FFFFF ... 0400000041FFFF 03E000003FFFFF ... 0000000001FFFF
8 7 ... 0 16
0100000011FFFF 00E000000FFFFF ... 32
16 15 ...
0200000021FFFF 01E000001FFFFF ... 64
32 31 ... 0
0
0000000001FFFF
0
0000000001FFFF
2.3
Table 6:
Device ID
Device ID codes
Density Litho (nm) Non-Mux AD-Mux Non-Mux AD-Mux Non-Mux AD-Mux Non-Mux AD-Mux Product Device Identifier Code (Hex)
128 Mbit
65
256 Mbit
65, 90
512 Mbit
65, 90
1024 Mbit Note:
65
To order parts listed above and to obtain a datasheet for the M18 SCSP parts, please contact your local Numonyx sales office.
Datasheet 12
Numonyx™ StrataFlash® Cellular Memory (M18)
3.0
Package Information
The following figures show the ballout package information for the device: • Figure 1, “Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)” • Figure 2, “Mechanical Specifications: x16D (105-ball) package (8x10x1.4 mm)” on page 15 • Figure 3, “Mechanical Specifications: x16D (105-ball) package (9x11x1.2 mm)” • Figure 4, “Mechanical Specifications: x16D (105 balls) Package (11x15x1.2 mm)” on page 17 • Figure 5, “Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2 mm)” • Figure 6, “Mechanical Specifications: x16C (107-ball) package (8x10x1.0 mm)” on page 19 • Figure 7, “Mechanical Specifications: x16C (107-ball) package (8x10x1.2 mm)” on page 20 • Figure 8, “Mechanical Specifications: x16C (107-ball) package (8x11x1.2 mm)” on page 21 • Figure 9, “Mechanical Specifications: x16C (107-ball) package (11x11x1.2 mm)” on page 22
April 2008 309823-10
Datasheet 13
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 1:
Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)
Pin 1 Corner 1 2 3 4 5 6 7 8 9
S1
S2
A B
C
D
E
D
F
G
H
J
K
L
e b
M
E
SCS Top View PBall Si de Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.90 7.90
Nom
Max 1.0
Notes
Min 0.0079
Nom
Max 0.0394
0.660 0.375 10.00 8.00 0.800 105 0.800 0.600
0.425 10.10 8.10
0.0128 0.3898 0.3110
0.0260 0.0148 0.3937 0.3150 0.0315 105 0.0315 0.0236
0.0167 0.3976 0.3189
0.700 0.500
0.100 0.900 0.700
0.0276 0.0197
0.0039 0.0354 0.0276
Datasheet 14
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 2:
Mechanical Specifications: x16D (105-ball) package (8x10x1.4 mm)
Pi n 1 Corner 1 2 3 4 5 6 7 8 9
S1
S2
A B
C
D
E
D
F
G
H
J
K
L
e b
M
E
SCS Top View P Ball Si de Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.90 7.90
Nom
Max 1.4
Notes
Min 0.0079
Nom
Max 0.0551
1.070 0.375 10.00 8.00 0.800 105 0.800 0.600
0.425 10.10 8.10
0.0128 0.3898 0.3110
0.0421 0.0148 0.3937 0.3150 0.0315 105 0.0315 0.0236
0.0167 0.3976 0.3189
0.700 0.500
0.100 0.900 0.700
0.0276 0.0197
0.0039 0.0354 0.0276
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Datasheet 15
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 3:
Mechanical Specifications: x16D (105-ball) package (9x11x1.2 mm)
S1
Pin 1 Corner
A B 1 2 3 4 5 6 7 8 9
S2
C
D
E
D
F
G
H
J
K
L
e b
M
E
Top View - Ball Side Down
A2 A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 10.90 8.90
Nom
Max 1.2
Notes
Min 0.0079
Nom
Max 0.0472
0.860 0.375 11.00 9.00 0.800 105 1.300 1.100
0.425 11.10 9.10
0.0128 0.4291 0.3504
0.0339 0.0148 0.4331 0.3543 0.0315 105 0.0512 0.0433
0.0167 0.4370 0.3583
1.200 1.000
0.100 1.400 1.200
0.0472 0.0394
0.0039 0.0551 0.0472
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 4:
Mechanical Specifications: x16D (105 balls) Package (11x15x1.2 mm)
April 2008 309823-10
Datasheet 17
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 5:
Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2 mm)
Ball one Corner
1 2 3 4 5 6 7 8 9 10 11 12
S1 S2
A B
C
D
E
F
G
D
H
J
K
L
M
N
e b
P
R
E
Top View - Ball Side Down
A2 A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Millimeters Min Nom 0.200 0.325 10.90 9.90 0.860 0.375 11.00 10.00 0.650 165 1.425 1.600
Max 1.2
Notes
Inches Min 0.0079
Nom
Max 0.0472
0.425 11.10 10.10
0.0128 0.4291 0.3898
0.0339 0.0148 0.4331 0.3937 0.0256 165 0.0561 0.0630
0.0167 0.4370 0.3976
1.325 1.500
0.100 1.525 1.700
0.0522 0.0591
0.0039 0.0600 0.0669
Datasheet 18
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 6:
Mechanical Specifications: x16C (107-ball) package (8x10x1.0 mm)
S1
1 2 3 4 5 6 7 8 9 10
Pin 1 Corner
S2
A B
C
D
E
D
F
G
H
J
K
L
e b
M
E
SCS Top View PBall Side Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.90 7.90
Nom
Max 1.0
Notes
Min 0.0079
Nom
Max 0.0394
0.660 0.375 10.00 8.00 0.800 107 0.800 0.600
0.425 10.10 8.10
0.0128 0.3898 0.3110
0.0260 0.0148 0.3937 0.3150 0.0315 107 0.0315 0.0236
0.0167 0.3976 0.3189
0.700 0.500
0.100 0.900 0.700
0.0276 0.0197
0.0039 0.0354 0.0276
April 2008 309823-10
Datasheet 19
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 7:
Mechanical Specifications: x16C (107-ball) package (8x10x1.2 mm)
Pi n 1 Corner 1 2 3 4 5 6 7 8 9 10
S1
S2
A B
C
D
E
D
F
G
H
J
K
L
e b
M
E
SCS Top View PBall Si de Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.90 7.90
Nom
Max 1.2
Notes
Min 0.0079
Nom
Max 0.0472
0.860 0.375 10.00 8.00 0.800 107 0.800 0.600
0.425 10.10 8.10
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 107 0.0315 0.0236
0.0167 0.3976 0.3189
0.700 0.500
0.100 0.900 0.700
0.0276 0.0197
0.0039 0.0354 0.0276
Datasheet 20
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 8:
Mechanical Specifications: x16C (107-ball) package (8x11x1.2 mm)
Pin 1 Corner
1 A B C D E 2 3 4 5 6 7 8 9
S1
S2
D
F G H J K L M
e b
E
Top View - Ball Side Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Millimeters Min Nom 0.200 0.325 10.90 7.90 0.860 0.375 11.00 8.00 0.800 107 0.800 1.100
Max 1.2
Notes
Inches Min 0.0079
Nom
Max 0.0472
0.425 11.10 8.10
0.0128 0.4291 0.3110
0.0339 0.0148 0.4331 0.3150 0.0315 107 0.0315 0.0433
0.0167 0.4370 0.3189
0.700 1.000
0.100 0.900 1.200
0.0276 0.0394
0.0039 0.0354 0.0472
April 2008 309823-10
Datasheet 21
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 9:
Mechanical Specifications: x16C (107-ball) package (11x11x1.2 mm)
Datasheet 22
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.0
Ballouts and Signal Descriptions
This section provides ballout and signal description information for x16D (105-ball), x16C (107-ball), and x16 Split Bus (165-ball) packages, Non-Mux, AD-Mux, AA/D Mux interfaces.
4.1
4.1.1
Ballouts, x16D
x16D (105-Ball) Ballout, Non-Mux
Figure 10: x16D (105-Ball) Electrical Ballout, Non-Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
A4
A6
A7
A19
A23
A24
A25
DU
A
B
A2
A3
A5
A17
A18
F-DPD
A22
A26
A16
B
C
A1
VSS
VSS
VSS
D-VCC
VSS
VSS
VSS
A15
C
D
A0
S-VCC
D-VCC
F1-VCC
ADV#
F2-VCC
D-VCC
N-ALE
A14
D
E
F-WP1#
WE#
D2-CS#
Depop (Index)
N-CLE
F4-CE# / A27 N-RE# / S-CS1#
A21
A10
A13
E
F
F-WP2#
D1-CS#
D-CAS#
D-RAS#
Depop (RFUs) Depop (RFUs)
A20
A9
A12
F
G
RFU
F2-CE#
F1-CE#
D-BA0
D-CKE
F-RST#
A8
A11
G
H
N-RY/BY#
N-WE# / S-CS2
F3-CE#
D-BA1
D-CLK#
D-WE#
OE#
D-DM1 / S-UB#
D-DM0 / S-LB#
H
J
F-VPP
VCCQ
VCCQ
F1-VCC
D-CLK
F2-VCC
VCCQ
VCCQ
F-WAIT
J
K
DQ2
VSS
VSS
VSS
F-CLK
VSS
VSS
VSS
DQ13
K
L
DQ1
DQ3
DQ5
DQ6
DQ7
DQ9
DQ11
DQ12
DQ14
L
M
DU
DQ0
D-LDQS
DQ4
DQ8
DQ10
D-UDQS
DQ15
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Legend: Active Balls De-Populated Balls Reserved for Future Use Do Not Use
April 2008 309823-10
Datasheet 23
Numonyx™ StrataFlash® Cellular Memory (M18)
4.1.2
x16D (105-Ball) Ballout, AD-Mux
Figure 11: x16D (105-Ball) Electrical Ballout, AD-Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
A4
A6
A7
A19
A23
A24
A25
DU
A
B
A2
A3
A5
A17
A18
F-DPD
A22
A26
A16
B
C
A1
VSS
VSS
VSS
D-VCC
VSS
VSS
VSS
A15
C
D
A0
S-VCC
D-VCC
F1-VCC
ADV#
F2-VCC
D-VCC
N-ALE
A14
D
E
F-WP1#
WE#
D2-CS#
Depop (Index)
N-CLE
F4-CE# / A27 N-RE# / S-CS1#
A21
A10
A13
E
F
F-WP2#
D1-CS#
D-CAS#
D-RAS#
Depop (RFUs) Depop (RFUs)
A20
A9
A12
F
G
RFU
F2-CE#
F1-CE#
D-BA0
D-CKE
F-RST#
A8
A11
G
H
N-RY/BY#
N-WE# / S-CS2
F3-CE#
D-BA1
D-CLK#
D-WE#
OE#
D-DM1 / R-UB#
D-DM0 / R-LB#
H
J
F-VPP
VCCQ
VCCQ
F1-VCC
D-CLK
F2-VCC
VCCQ
VCCQ
F-WAIT
J
K
AD2
VSS
VSS
VSS
F-CLK
VSS
VSS
VSS
AD13
K
L
AD1
AD3
AD5
AD6
AD7
AD9
AD11
AD12
AD14
L
M
DU
AD0
D-LDQS
AD4
AD8
AD10
D-UDQS
AD15
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Legend: Active Balls De-Populated Balls Reserved for Future Use Do Not Use
Datasheet 24
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.1.3
x16D Mux (105-Ball) Ballout, AA/D Mux
Figure 12: x16D (105-Ball) Electrical Ballout, AA/D Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
A4
A6
A7
RFU
RFU
RFU
RFU
DU
A
B
A2
A3
A5
RFU
RFU
F-DPD
RFU
F-ADV2#
RFU
B
C
A1
VSS
VSS
VSS
D-VCC
VSS
VSS
VSS
A15
C
D
A0
S-VCC
D-VCC
F-VCC
F-ADV#
F-VCC
D-VCC
N-ALE
A14
D
E
F-WP1#
WE#
D2-CS#
Depop (Index)
N-CLE
F4-CE#
RFU
A10
A13
E
F
F-WP2#
D1-CS#
D-CAS#
D-RAS#
Depop (RFU) Depop (RFU)
S-CS1 / N-RE#
RFU
A9
A12
F
G
RFU
F2-CE#
F1-CE#
D-BA0
D-CKE
F-RST#
A8
A11
G
H
N-RY/BY#
S-CS2 / N-WE#
F3-CE#
D-BA1
D-CLK#
D-WE#
OE#
D-DM1 / S-UB#
D-DM0 / S-LB#
H
J
F-VPP
VCCQ
VCCQ
F-VCC
D-CLK
F-VCC
VCCQ
VCCQ
F-WAIT
J
K
AD2
VSS
VSS
VSS
F-CLK
VSS
VSS
VSS
AD13
K
L
AD1
AD3
AD5
AD6
AD7
AD9
AD11
AD12
AD14
L
M
DU
AD0
D-LDQS
AD4
AD8
AD10
D-UDQS
AD15
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Legend: Active Balls De-Populated Balls Reserved for Future Use Do Not Use
April 2008 309823-10
Datasheet 25
Numonyx™ StrataFlash® Cellular Memory (M18)
4.2
Table 7:
Symbol
Signal Descriptions, x16D
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 1 of 4)
Type Signal Descriptions Notes
Address and Data Signals, Non-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 4-Gbit: AMAX = A27 • 2-Gbit: AMAX = A26 • 1-Gbit: AMAX = A25 • 512-Mbit: AMAX = A24 • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 • A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM. • A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM. • A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM. Unused address inputs should be treated as RFU. DATA INPUT/OUTPUTS: Global device signals. DQ[15:0] are used to input commands and write-data during Write cycles, and to output readdata during Read cycles. During NAND accesses, DQ[7:0] are used to input commands, addressdata, and write-data, and to output read-data. Data signals are High-Z when the device is deselected or its output is disabled. FLASH ADDRESS VALID: Flash-specific signal; low-true input. During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to 133 MHz. In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV# or continuously flows through while F-ADV# is low.
A[MAX: 0]
Input
1
DQ[15:0]
Input/ Output
F-ADV#
Input
Address and Data Signals, AD-Mux ADDRESS: Global device signals. Shared address inputs for all Flash and SRAM memory die during Read and Write operations. • 4-Gbit: AMAX = A27 • 2-Gbit: AMAX = A26 • 1-Gbit: AMAX = A25 • 512-Mbit: AMAX = A24 • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash and SRAM lower address and data signals; LPSDRAM data signals. During AD-Mux flash and SRAM Write cycles, AD[15:0] are used to input the lower address followed by commands or write-data. During AD-Mux flash Read cycles, AD[15:0] are used to input the lower address followed by read-data output. During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write cycles or to output read-data during Read cycles. During NAND accesses, AD[7:0] are used to input commands, address, or write-data, and to output read-data. AD[15:0] are High-Z when the flash or SRAM is deselected or its output is disabled. RFU, except for DRAM.
A[MAX:16]
Input
1
AD[15:0]
Input / Output
A[15:0]
Input
Datasheet 26
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Symbol
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 2 of 4)
Type Signal Descriptions FLASH ADDRESS VALID: Flash-specific signal; low-true input. During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to 133 MHz. In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#. ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 4-Gbit: AMAX = A27 • 2-Gbit: AMAX = A26 • 1-Gbit: AMAX = A25 • 512-Mbit: AMAX = A24 • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 • A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM. • A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM. • A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM. Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AAD-Mux flash address and data; LPSDRAM data. During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower address, and commands or write-data. During AAD-Mux flash Read cycles, AD[15:0] are used to input the upper address and lower address, and output read-data. During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write cycles or to output read-data during Read cycles. During NAND accesses, AD[7:0] are used to input commands, address-data, or write-data, and to output read-data. AD[15:0] are High-Z when the device is deselected or its output is disabled. FLASH ADDRESS VALID: Flash-specific signal; low-true input. During a synchronous flash Read operation, the address is latched on the F-ADV# rising edge or the first F-CLK edge after F-ADV# low in devices that support up to 104 MHz, and on the last rising F-CLK edge after F-ADV# low in devices that support upto 133 MHz. During a synchronous flash Read operation, the address is latched on the rising edge of F-ADV# or the first active F-CLK edge whichever occurs first. In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#. During AAD-Mux flash accesses, the upper address is latched on the valid edge of F-CLK while F-ADV2# is low; the lower address is latched on the valid edge of F-CLK while F-ADV# is low. The upper address is always latched first, followed by the lower address. Notes
F-ADV#
Input
A[MAX: 0]
Input
1
AD[15:0]
Input / Output
F-ADV# F-ADV2#
Input
Control Signals FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. • F1-CE# is dedicated to flash die #1. • F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. • For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2 while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3CE# selects NAND die #3 if present. FLASH CLOCK: Flash-specific signal; rising active-edge input. F-CLK synchronizes the flash with the system clock during synchronous operations. LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input. D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock. DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input. D-CLK# synchronizes the DDR LPSDRAM with the system clock. 2 2
F[4:1]CE#
Input
1
F-CLK D-CLK D-CLK#
Input Input Input
April 2008 309823-10
Datasheet 27
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Symbol
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 3 of 4)
Type Signal Descriptions OUTPUT ENABLE: Flash- and SRAM-specific signal; low-true input. When low, OE# enables the output drivers of the selected flash or SRAM die. When high, OE# disables the output drivers of the selected flash or SRAM die and places the output drivers in High-Z. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation. FLASH WAIT: Flash -specific signal; configurable-true output. When asserted, F-WAIT indicates invalid output data. F-WAIT is driven whenever F-CE# and OE# are low. F-WAIT is High-Z whenever F-CE# or OE# is high. WRITE ENABLE: Flash- and SRAM-specific signal; low-true input. When low, WE# enables Write operations for the enabled flash or SRAM die. LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input. D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define the LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. • F-WP1# is dedicated to flash die #1. • F-WP2# is common to all other flash dies, if present. Otherwise it is RFU. • For NOR/NAND stacked device, F-WP1# selects all NOR dies; F-WP2# selects all NAND dies. FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input. When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode. NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input. When high, N-CLE enables commands to be latched on the rising edge of N-WE#. NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input. When high, N-ALE enables addresses to be latched on the rising edge of N-WE#. NAND READ ENABLE: NAND-specific signal; low-true input. When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE# disables the output drivers of the selected NAND die and places the output drivers in High-Z. NAND READY/BUSY: NAND-specific signal; low-true output. When low, N-RY/BY# indicates the NAND is busy performing a read, program, or erase operation. When high, N-RY/BY# indicates the NAND device is ready. NAND WRITE ENABLE: NAND-specific signal; low-true input. When low, N-WE# enables Write operations for the enabled NAND die. LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input. When high, D-CKE indicates that the next D-CLK edge is valid. When low, D-CKE indicates that the next D-CLK edge is invalid and the selected LPSDRAM die is suspended. LPSDRAM BANK SELECT: L PSDRAM-specific input signals. D-BA[1:0] selects one of four banks in the LPSDRAM die. LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input. D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define the LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK. LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input. D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define the LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK. LPSDRAM CHIP SELECT: LPSDRAM-specific signal; low-true input. When low, D-CS# selects the associated LPSDRAM memory die and starts the command input cycle. When D-CS# is high, commands are ignored but operations continue. • D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#, define the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-CLK. • D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present. Otherwise, any unused LPSDRAM chip selects should be treated as RFU. 2 2 2 Notes
OE#
Input
F-RST#
Input
F-WAIT
Output
WE#
Input
D-WE#
Input
FWP[2:1]#
Input
F-DPD N-CLE N-ALE
Input Input Input
N-RE#
Input
2, 4
N-RY/BY#
Output
2
N-WE#
Input
2, 5
D-CKE
Input
2
D-BA[1:0]
Input
2
D-RAS#
Input
2
D-CAS#
Input
2
D[2:1]CS#
Input
2
Datasheet 28
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Symbol
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 4 of 4)
Type Signal Descriptions LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input. When high, D-DM[1:0] controls masking of input data during writes and output data during reads. • D-DM1 corresponds to the data on DQ[15:8]. • D-DM0 corresponds to the data on DQ[7:0]. LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals. D-UDQS and D-LDQS provide as output the read-data strobes, and as input the write-data strobes. • D-UDQS corresponds to the data on DQ[15:8]. • D-LDQS corresponds to the data on DQ[7:0]. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both are asserted, S-CS1# and S-CS2 select the SRAM die. When either is deasserted, the SRAM die is deselected and its power is reduced to standby levels. SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs. When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM Read and Write cycles. When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0]. Notes
D-DM[1:0]
Input
2, 3
D-UDQS D-LDQS
Input / Output
2
S-CS1# S-CS2 S-UB# S-LB#
Input
2, 4, 5
Input
2, 3
Power Signals F-VPP F1-VCC Power Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. F1-VCC supplies the core power to the NOR flash die. FLASH CORE POWER SUPPLY: Flash specific. F2-VCC supplies the core power to either 1) the NOR flash die in stack packages with multiple NOR flash dies, or 2) NAND flash die in stack packages with NOR-NAND flash dies. I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. LPSDRAM CORE POWER SUPPLY: LPSDRAM specific. D-VCC supplies the core power to the LPSDRAM die. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: Ball should not be connected to any power supplies, signals, or other balls. Ball can be left floating. RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality/enhancement. Ball must be left floating. 2 2 6
F2-VCC
Power
VCCQ D-VCC S-VCC VSS
Power Power Power Groun d —
DU
RFU
—
Notes: 1. F4-CE# and A27 share the same package ball at location E6. Only one signal function is available, depending on the stacked device combination. 2. Only available on stacked device combinations with NAND, SRAM, and/or LPSDRAM die; otherwise, treated as RFU. 3. D-DM[1:0] and S-UB#/S-LB# share the same package balls at locations H8 and H9, respectively. Only one signal function for each ball location is available, depending on the stacked device combination. 4. S-CS1# and N-RE# share the same package ball at location F6. Only one signal function is available, depending on the stacked device combination. 5. S-CS2 and N-WE# share the same package ball at location H2. Only one signal function is available, depending on the stacked device combination. 6. In stack packages with only one NOR flash die, this signal can be left floating.
4.3
4.3.1
Ballouts, x16C
x16C (107-Ball) Ballout, Non-Mux
April 2008 309823-10
Datasheet 29
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 13: x16C (107-Ball) Electrical Ballout, Non-Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
N-CLE
A27
A26
P-VCC
F-DPD
VSS
DU
A
B
DU
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
N-ALE
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
VSS
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
VSS
A2
A7
A25
F-WP1#
ADV#
A20
A10
A15
E
F
F-WP2#
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
VCCQ
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
VSS
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE# / N-RE#
H
J
RFU
S-CS1# / N-WE#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F4-CE#
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
RFU
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
N-RY/BY#
RFU
RFU
RFU
RFU
RFU
RFU
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Legend: Active Balls Reserved for Future Use Do Not Use
Datasheet 30
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.3.2
x16C (107-Ball) Ballout, AD-Mux
Figure 14: x16C (107-Ball) Electrical Ballout, AD-Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
N-CLE
A27
A26
P-VCC
F-DPD
VSS
DU
A
B
DU
RFU
A18
A19
VSS
F1-VCC
F2-VCC
A21
RFU
B
C
N-ALE
RFU
R-LB#
A23
VSS
S-CS2
CLK
A22
RFU
C
D
VSS
RFU
A17
A24
F-VPP
R-WE#
P1-CS#
RFU
RFU
D
E
VSS
RFU
RFU
A25
F-WP1#
ADV#
A20
RFU
RFU
E
F
F-WP2#
RFU
RFU
R-UB#
F-RST#
F-WE#
RFU
RFU
A16
F
G
VCCQ
RFU
AD8
AD2
AD10
AD5
AD13
WAIT
F2-CE#
G
H
VSS
R-OE#
AD0
AD1
AD3
AD12
AD14
AD7
F2-OE# / N-RE#
H
J
RFU
S-CS1# / N-WE#
F1-OE#
AD9
AD11
AD4
AD6
AD15
VCCQ
J
K
F4-CE#
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
RFU
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
N-RY/BY#
RFU
RFU
RFU
RFU
RFU
RFU
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Active Balls Reserved for Future Use Do Not Use
Legend:
April 2008 309823-10
Datasheet 31
Numonyx™ StrataFlash® Cellular Memory (M18)
4.3.3
x16C (107-Ball) Ballout, AA/D-Mux
Figure 15: x16C (107-Ball) Electrical Ballout, AA/D-Mux
Pin 1
1 2 3 4 5 6 7 8 9
A
DU
N-CLE
RFU
RFU
P-VCC
F-DPD
VSS
DU
A
B
DU
RFU
RFU
RFU
VSS
F1-VCC
F2-VCC
RFU
RFU
B
C
N-ALE
RFU
R-LB#
RFU
VSS
S-CS2
CLK
RFU
RFU
C
D
VSS
RFU
RFU
RFU
F-VPP
R-WE#
P1-CS#
RFU
RFU
D
E
VSS
RFU
RFU
RFU
F-WP1#
ADV#
RFU
RFU
RFU
E
F
F-WP2#
RFU
RFU
R-UB#
F-RST#
F-WE#
RFU
RFU
RFU
F
G
VCCQ
RFU
AD8
AD2
AD10
AD5
AD13
WAIT
F2-CE#
G
H
VSS
R-OE#
AD0
AD1
AD3
AD12
AD14
AD7
F2-OE# / N-RE#
H
J
RFU
S-CS1# / N-WE#
F1-OE#
AD9
AD11
AD4
AD6
AD15
VCCQ
J
K
F4-CE#
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
RFU
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
N-RY/BY#
RFU
RFU
RFU
F-ADV2#
RFU
RFU
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Active Balls Reserved for Future Use Do Not Use
Legend:
Datasheet 32
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.4
Table 8:
Symbol
Signal Descriptions x16C
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 1 of 3)
Type Signal Descriptions Notes
Address and Data Signals, Non-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22 • 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21 • 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20 • 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19 • 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18 Unused address inputs should be treated as RFU. DATA INPUT/OUTPUTS: Global device signals. Inputs data and commands during Write cycles, outputs data during Read cycles. Data signals are High-Z when the device is deselected or its output is disabled. ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to 133 MHz. In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or continuously flows through while ADV# is low.
A[MAX:0]
Input
DQ[15:0]
Input / Output
ADV#
Input
Address and Data Signals, AD-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22 • 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21 • 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20 • 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19 • 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18 Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals. During AD-Mux Write cycles, AD[15:0] are used to input the lower address followed by commands or data. During AD-Mux Read cycles, AD[15:0] are used to input the lower address followed by read-data output. During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and output read-data. AD[15:0] are High-Z when the device is deselected or its output is disabled. ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to 133 MHz. In an asynchronous flash Read operation, the address is latched on the rising edge of ADV#.
A[MAX:16]
Input
AD[15:0]
Input / Output
ADV#
Input
Address and Data Signals, AAD-Mux ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals. During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower address, and commands or data. During AAD-Mux flash Read cycles, AD[15:0] are used to input the upper address and lower address, and output read-data. During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and output read-data. AD[15:0] are High-Z when the device is deselected or its output is disabled.
AD[15:0]
Input / Output
April 2008 309823-10
Datasheet 33
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 8:
Symbol F-ADV2# ADV#
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 2 of 3)
Type Signal Descriptions FLASH ADDRESS VALID: Flash-specific signal; low-true input. During AAD-Mux flash accesses, the upper address is latched on the valid edge of CLK while F-ADV2# is low; the lower address is latched on the valid edge of CLK while ADV# is low. The upper address is always latched first, followed by the lower address. Notes
Input
Control Signals FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. • F1-CE# is dedicated to flash die #1. • F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. • For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2 while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3CE# selects NAND die #3 if present. CLOCK: Flash- and Synchronous PSRAM-specific input signal. CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous operations. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. • For NOR only stacked device, F[2:1]-OE# are common to all NOR dies in the device. • For NOR/NAND stacked device, F1-OE# enables all NOR dies, F2-OE# selects all NAND dies if present. RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# disables the output drivers of the selected memory die and places the output drivers in High-Z. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation. WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. • WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable is low. • WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable is high. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-WE# enables Write operations for the selected memory die. Data is latched on the rising edge of R-WE#. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. • F-WP1# is dedicated to flash die #1. • F-WP2# is common to all other flash dies, if present. Otherwise it is RFU. • For NOR/NAND stacked device, F-WP1# selects all NOR dies, while F-WP2# selects all NAND dies. FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input. When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode. NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input. When high, N-CLE enables commands to be latched on the rising edge of N-WE#. 1 1
F[4:1]-CE#
Input
CLK
Input
F[2:1]-OE#
Input
2
R-OE#
Input
1
F-RST#
Input
WAIT
Output
F-WE#
Input
R-WE#
Input
F-WP[2:1]#
Input
F-DPD N-CLE
Input Input
Datasheet 34
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 8:
Symbol N-ALE
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 3 of 3)
Type Input Signal Descriptions NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input. When high, N-ALE enables addresses to be latched on the rising edge of N-WE#. NAND READ ENABLE: NAND-specific signal; low-true input. When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE# disables the output drivers of the selected NAND die and places the output drivers in High-Z. NAND READY/BUSY: NAND-specific signal; low-true output. When low, N-RY/BY# indicates the NAND is busy performing a Read, Program, or Erase operation. When high, N-RY/BY# indicates the NAND device is ready. NAND WRITE ENABLE: NAND-specific signal; low-true input. When low, N-WE# enables Write operations for the enabled NAND die. PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input. When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control Register (P-BCR). When low, P-CRE enables normal Read or Write operations. PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input. When low, P-MODE# enables access to the configuration register, and to enter or exit LowPower mode. When high, P-MODE# enables normal Read or Write operations. PSRAM CHIP SELECT: PSRAM-specific signal; low-true input. When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT outputs are placed in a High-Z state. • P1-CS# is dedicated to PSRAM die #1. • P2-CS# IS dedicated to PSRAM die #2. Otherwise, any unused PSRAM chip select should be treated as RFU. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or S-CS2 is deasserted, the SRAM die is deselected. RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs. When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. Notes 1
N-RE#
Input
1, 2
N-RY/BY#
Output
1
N-WE#
Input
1, 4
P-CRE
Input
1, 3
P-MODE#
Input
1, 3
P[2:1]-CS#
Input
1
S-CS1# S-CS2 R-UB# R-LB#
Input
1, 4
Input
1
Power Signals F-VPP Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. F[2:1]-VCC supplies the core power to the flash die. For NOR/NAND stacked device, F1-VCC is dedicated for all NOR dies, F2-VCC is dedicated for all NAND dies. I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC supplies the core power to the PSRAM die. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: Ball should not be connected to any power supplies, signals, or other balls. Ball can be left floating. RESERVED for FUTURE USE: Reserved by Numonyx for future device functionality and enhancement. Ball must be left floating. 1 1
F[2:1]-VCC
Power
5
VCCQ P-VCC S-VCC VSS
Power Power Power Groun d —
DU
RFU
—
April 2008 309823-10
Datasheet 35
Numonyx™ StrataFlash® Cellular Memory (M18)
Notes: 1. Only available on stacked device combinations with NAND, SRAM, and/or LPSDRAM die. Otherwise treated as RFU. 2. F2-OE# and N-RE# share the same package ball at location H9. Only one signal function is available, depending on the stacked device combination. 3. P-CRE and P-MODE# share the same package ball at location K9. Only one signal function is available, depending on the stacked device combination. 4. S-CS1# and N-WE# share the same package ball at location J2. Only one signal function is available, depending on the stacked device combination. 5. The F2-VCC signal applies to a NAND flash die if one exists; if not, the F2-VCC signal applies to the NOR flash die.
Datasheet 36
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.5
4.5.1
Ballouts, x16 Split Bus
x16 Split Bus (165-Ball) Ballout, Non-Mux
Figure 16: x16 Split Bus (165 Active Ball) Electrical Ballout, Non-Mux
Pin 1 1 2 3 4 5 B: D-BA0 6 B: D-A11 7 8 9 10 B: D-A4 11 12
A
DU
B: D-A2
B: D-A0
B: D-A12
B: D-A8
B: D-A6
DU
A
B
DU
A: F-A15
B: D-A3
B: D-A1
B: D-BA1 B: D-WE# B: D-A13 A: F3CE# / N2-CE# A: F4CE# / N1-CE# B: D1CE#
B: D-A9
B: D-A7
B: D-A5
RFU
DU
B
C
A: F-A13
A: F-A14
A: F-A16
A: VSS
B: D-CKE B: D-A14
A: VSS
RFU
A: F-D7 / A: F-D14 / N-ADQ7 N-ADQ14 A: F-D15 / A: F-D6 / N-ADQ15 N-ADQ6
C
D
A: F-A12
A: F-A22 A: F2-CE# B: D-A10 B: D-VCC
B: D2CE#
B: DCLK#
B: D-CLK
A: VSS
D
E
A: F-A11
A: F-A21
A: N-R/B# A: F-DPD
RFU
B: DRAS#
B: DCAS#
RFU
A: FWAIT
A: VCCQ
RFU
A: F-D13 / N-ADQ13
E
F
A: F-A10
A: F-A20
A: F-WE#
A: VSS A: FWP2# / N-WP#
Depop (Index)
Depop (RFU)
Depop (RFU)
A: F2VCC / N-VCC B: D-VCC
A: VSS
A: VCCQ
A: VSS
A: F-D5 / N-ADQ5
F
G
A: F-A9
A: F-A26 A: F-WP1#
RFU
Depop (RFU)
Depop (RFU)
RFU
A: FADV#
A: F-D12 / A: F-D4 / N-ADQ12 N-ADQ4
G
H
A: F-A8
A: F-A24
A: F-A25
A: VSS
A: F1-CE#
Depop (RFU)
Depop (RFU)
A: F1VCC
A: VSS
RFU
RFU
A: F-CLK
H
J
A: F-A18
A: F-A19
A: F-A23 A: N-CLE
A: F2VCC / N-VCC
Depop (RFU)
Depop (RFU)
RFU
RFU
A: F-OE# A: F-D10 / A: F-D11 / N-ADQ10 N-ADQ11
J
K
A: F-A7
A: F-A17
RFU
A: VSS
B: D-VCC
Depop (RFU)
Depop (RFU)
RFU
A: VSS
A: VCCQ
A: VSS
A: F-D3 / N-ADQ3
K
L
A: F-A5
A: F-A6
A: N-ALE A: N-WE# A: F1-VCC A: N-RE#
RFU
A: F-VPP
A: FRST# B: DVDDQ
A: VCCQ
RFU
A: F-D2 / N-ADQ2
L
M
A: F-A3
A: F-A4
RFU
B: DVDDQ
B: D-DM0
B: DVDDQ
B: DVDDQ
B: DDM1
A: VSS
A: F-D1 / N-ADQ1
A: F-D9 / N-ADQ9
M
N
A: F-A1
A: F-A2
B: D-VSS
B: DDQS0
B: D-VSS
A: VSS
B: D-VSS
B: DDQS1
B: D-VSS
RFU
A: F-D8 / N-ADQ8
A: F-D0 / N-ADQ0
N
P
DU
A: F-A0
B: D-D1
B: D-D3
B: D-D5
B: D-D7
B: D-D8
B: D-D10 B: D-D12
B: D-D14
RFU
DU
P
R
DU
B: D-D0
B: D-D2
B: D-D4
B: D-D6
B: D-D9
B: D-D11 B: D-D13
B: D-D15
DU
R
1
2
3
4
5
6
7
8
9
10
11
12
Top View - Ball Side Down
B5173 -01
April 2008 309823-10
Datasheet 37
Numonyx™ StrataFlash® Cellular Memory (M18)
4.6
Table 9:
Symbol
Signal Descriptions, x16 Split Bus
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 1 of 4)
Type Signal Descriptions Notes
Address and Data Signals, Non-Mux FLASH ADDRESS: Flash device signals. Dedicated address inputs for Flash memory die during read and write operations. • 2-Gbit: AMAX = A26 • 1-Gbit: AMAX = A25 • 512-Mbit: AMAX = A24 • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 Unused address inputs are RFU. LPSDRAM ADDRESS: LSPDRAM device signals. Dedicated address inputs for LPSDRAM memory die during read and write operations. • A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM. • A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM. • A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM. Unused address inputs are RFU. FLASH DATA INPUT/OUTPUTS: Flash device signals. • Inputs Flash data and commands during write cycles. • Outputs data during read cycles. • Data signals are High-Z when the device is deselected or its output is disabled. LPSDRAM DATA INPUT/OUTPUTS: LPSDRAM device signals. • Inputs LPSDRAM data and commands during write cycles. • Outputs data during read cycles. • Data signals are High-Z when the device is deselected or its output is disabled.
F-A[MAX:0]
Input
D-A[MAX:0]
Input
F-DQ[15:0]
Input/ Output
D-DQ[15:0]
Input/ Output
Address and Data Signals, A/D Mux ADDRESS: Flash device signals. Shared address inputs for all Flash memory die during Read and Write operations. • 2-Gbit: AMAX = A26 • 1-Gbit: AMAX = A25 • 512-Mbit: AMAX = A24 • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash lower address and data signals; LPSDRAM data signals. During AD-Mux flash Write cycles, ADQ[15:0] are used to input the lower address followed by commands or write-data. During AD-Mux flash Read cycles, ADQ[15:0] are used to input the lower address followed by read-data output. During LPSDRAM accesses, ADQ[15:0] are used to input commands and write-data during Write cycles or to output read-data during Read cycles. During NAND accesses, ADQ[7:0] are used to input commands, address, or write-data, and to output read-data. ADQ[15:0] are High-Z when the flash is deselected or its output is disabled.
F-A[MAX:16]
Input
F-ADQ[15:0]
Input / Output
Control Signals
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Table 9:
Symbol
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 2 of 4)
Type Signal Descriptions FLASH ADDRESS VALID: Flash-specific signal; low-true input. During synchronous flash Read operations, the address is latched on the rising edge of FADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to 133 MHz. In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#. FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. • F1-CE# is dedicated to flash die #1. • F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise, treat any unused flash chip enable as RFU. • When NAND is used, F4-CE# is dedicated for NAND die 1 and NAND die 2. Otherwise, this is RFU. FLASH CLOCK: Flash-specific signal; configurable active-edge input. F-CLK synchronizes the flash memory with the system clock during synchronous operations. LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input. D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock. DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input. D-CLK# synchronizes the DDR LPSDRAM with the system clock. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. • When low, OE# enables the output drivers of the selected flash die. • When high, OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. FLASH RESET: Flash-specific signal; low-true input. • When low, F-RST# resets internal operations and inhibits writes. • When high, F-RST# enables normal operation. FLASH WAIT: Flash-specific signal; configurable-true output. When asserted, F-WAIT indicates invalid output data. • F-WAIT is driven whenever F-CE# and OE# is low. • F-WAIT is High-Z whenever F-CE# or OE# is high. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, WE# enables write operations for the selected flash die. NAND WRITE ENABLE: NAND-specific signal; low-true input. When low, WE# enables write operations for the selected NAND die. LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input. D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define the LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-Down function, enabling locked-down blocks to be unlocked with the Unlock command. • F-WP1# is dedicated to flash die #1. • F-WP2# is used for NAND die when available. Otherwise, this signal is for all other NOR die. FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input. When enabled in the ECR, F-DPD is used to enter or exit Deep Power-Down mode. NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input. When high, N-CLE enables commands to be latched on the rising edge of WE#. NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input. When high, N-ALE enables addresses to be latched on the rising edge of WE#. 1 1 1 1 1 Notes
F-ADV#
Input
F[4:1]-CE#
Input
F-CLK D-CLK D-CLK#
Input Input Input
F-OE#
Input
F-RST#
Input
F-WAIT
Output
F-WE# N-WE#
Input Input
D-WE#
Input
1
F-WP[2:1]#
Input
F-DPD N-CLE N-ALE
Input Input Input
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 9:
Symbol
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 3 of 4)
Type Signal Descriptions NAND READY/BUSY: NAND-specific signal; low-true output. • When low, N-RY/BY# indicates the NAND device is busy performing a read, program, or erase operations. • When high, N-RY/BY# indicates the NAND device is ready. NAND READ ENABLE: NAND-specific signal; drives the data onto the flash bus after the falling edge of N-RE#. This signal increments the internal column address and reads out each data. LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input. • When high, D-CKE indicates that the next D-CLK edge is valid. • When low, D-CKE indicates that the next D-CLK edge is invalid and the selected LPSDRAM die is suspended. LPSDRAM BANK SELECT: LPSDRAM-specific input signals. D-BA[1:0] selects one of four banks in the LPSDRAM die. LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input. D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define the LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK. LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input. D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define the LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK. LPSDRAM CHIP ENABLE: LPSDRAM-specific signal; low-true input. When low, D-CS# selects the associated LPSDRAM memory die and starts the command input cycle. When D-CS# is high, commands are ignored but operations continue. • D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#, define the LPSDRAM command or operation. D-CS# is sampled on the rising edge of DCLK. • D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present. Otherwise, treat any unused LPSDRAM chip selects as RFU. LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input. When high, D-DM[1:0] controls masking of input data during writes and output data during reads. • D-DM1 corresponds to the data on DQ[15:8]. • D-DM0 corresponds to the data on DQ[7:0]. LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals. D-DQS1 and D-DQS0 provide as output the read data strobes, and as input the write data strobes. • D-DQS1 corresponds to the data on DQ[15:8]. • D-DQS0 corresponds to the data on DQ[7:0]. SRAM CHIP SELECTS: SRAM-specific signals. • S-CS1# low-true input. • S-CS2# high-true input. • When both are asserted, S-CS1# and S-CS2 select the SRAM die. • When either is deasserted, the SRAM die is deselected and its power is reduced to standby levels. SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs. • When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM read and write cycles. • When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0]. Notes
N-R/B#
Output
1
N-RE#
Output
1
D-CKE
Input
1
D-BA[1:0]
Input
1
D-RAS#
Input
1
D-CAS#
Input
1
D[2:1]-CE#
Input
1
D-DM[1:0]
Input
1
D-DQS1 D-DQS0
Input / Output
1
S-CS1# S-CS2#
Input
3
S-UB# S-LB# Power Signals F-VPP
Input
2,3
Power
FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die.
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Table 9:
Symbol
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 4 of 4)
Type Signal Descriptions FLASH CORE POWER SUPPLY: Flash specific. F-VCC supplies the core power to the flash die. • F1-VCC is dedicated for NOR die. • F2-VCC is used for NAND die when available. Otherwise, this signal is for NOR die. (When NAND is available, the F2-VCC signal is named N-VCC.) LPSDRAM CORE POWER SUPPLY: LPSDRAM specific. D-VCC supplies the core power to the LPSDRAM die. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. FLASH I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage to the flash die. LPSDRAM I/O POWER SUPPLY: Global device I/O power. VDDQ supplies the device input/output driver voltage to the LPSDRAM die. FLASH DEVICE GROUND: Global ground reference for all flash signals and power supplies. Connect all A: VSS balls to system ground. Do not float any VSS connections. LPSDRAM DEVICE GROUND: Global ground reference for all LPSDRAM signals and power supplies. Connect all B: D-VSS balls to system ground. Do not float any VSS connections. DO NOT USE: Do not connect this ball to any power supplies, signals, or other balls. This ball can be left floating. RESERVED for FUTURE USE: Reserved by Numonyx for future device functionality and enhancement. This ball must be left floating. 1 1 1 Notes
F[2:1]-VCC
Power
D-VCC S-VCC VCCQ D-VDDQ VSS
Power Power Power Power Ground
D-VSS
Ground
DU
—
RFU
—
Notes: 6. Available only on stacked device combinations with NAND, and/or LPSDRAM die. Otherwise, treat the signal as RFU.
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Numonyx™ StrataFlash® Cellular Memory (M18)
5.0
5.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.
Table 10: Absolute Maximum Ratings
Parameter Temperature under Bias Expanded Storage Temperature F-VCC Voltage VCCQ and P-VCC Voltage Voltage on any input/output signal (except VCC, VCCQ,and VPP) F-VPP Voltage ISH Output Short Circuit Current VPPH Time Block Program/Erase Cycles: Main Blocks Min –30 –65 –2.0 –2.0 –2.0 –2.0 — — 100,000 Max +85 +125 VCCQ + 2.0 VCCQ + 2.0 VCCQ + 2.0 +11.5 100 80 — Unit °C °C V V V V mA Hours Cycles F-VPP = VCC or F-VPP = VPPH Conditions — — — — — — — Notes 1 1 2,3 2,4 2,4 2,3 5 6 6
Notes: 1. Temperature is Ambient, not Case. 2. Voltage is referenced to VSS. 3. During signal transitions, minimum DC voltage may undershoot to –2.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCC (max) + 2.0 V for periods < 20 ns. 4. During signal transitions, minimum DC voltage may undershoot to –1.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCCQ (max) + 1.0 V for periods < 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. 6. Operation beyond this limit may degrade performance.
5.2
Warning:
Operating Conditions
Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
Table 11: Operating Conditions
Symbol TC VCC VCCQ VPPL VPPH Description Operating Temperature (Case Temperature) VCC Supply Voltage I/O Supply Voltage Programming Voltage (Logic Level) Factory Programming Voltage (High Level) Min –30 +1.7 +1.7 +0.9 +8.5 Max +85 +2.0 +2.0 +2.0 +9.5 Unit °C V V V V Conditions — — — — —
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6.0
6.1
Electrical Characteristics
Initialization
Proper device initialization and operation is dependent on the power-up/down sequence, reset procedure, and adequate power-supply decoupling. The following sections describe each of these areas.
6.1.1
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the power-up/power-down sequence shown in Table 12 is recommended. Note that each power supply must reach its minimum voltage range before applying/removing the next supply voltage.
Table 12: Power-Up/Down Sequence
Power Supply Voltage VCC(min) VCCQ(min) VPP(min) 1st 2nd 3rd Power-Up Sequence 1st 2nd* 3rd Sequencing not required* 2nd 1st Power-Down Sequence 2nd 1st*
1st* 2nd
2nd* 1st
Sequencing not required*
* Power supplies connected or sequenced together. Device inputs must not be driven until all supply voltages reach their minimum range. RST# should be low during power transitions. Note: If VCCQ is below VLKOQ, the device is reset.
6.1.2
Reset Characteristics
During power-up and power-down, RST#should be asserted to prevent spurious program or erase operations. While RST#is low, device operations are disabled; all inputs such as address and control are ignored; and all outputs such as data and WAIT are placed in High-Z. Invalid bus conditions are effectively masked out. Upon power-up, RST#can be deasserted after tVCCPH, allowing the device to exit from reset. Upon exiting from reset, the device defaults to asynchronous Read Array mode, and the Status Register defaults to 0080h. Array data is available after tPHQV, or a buswrite cycle can begin after tPHWL. If RST#is asserted during a program or erase operation, the operation will abort and array contents at that location will be invalid. For proper system initialization, connect RST#to the low-true reset signal that asserts whenever the processor is reset. This will ensure the flash device is in the expected read mode (i.e., Read Array) upon startup.
6.1.3
Power Supply Decoupling
High-speed flash memories require adequate power-supply decoupling to prevent external transient noise from affecting device operations, and to prevent internallygenerated transient noise from affecting other devices in the system.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Ceramic chip capacitors of 0.01 to 0.1 µF capacitors should be used between all VCC, VCCQ, VPPsupply connections and system ground. These high-frequency, inherently low-inductance capacitors should be placed as close as possible to the device package, or on the opposite side of the printed circuit board close to the center of the devicepackage footprint. Larger (4.7 µF to 33.0 µF) electrolytic or tantulum bulk capacitors should also be distributed as needed throughout the system to compensate for voltage sags caused by circuit trace inductance. Transient current magnitudes depend on the capacitive and inductive loading on the device’s outputs. For best signal integrity and device performance, high-speed design rules should be used when designing the printed-circuit board. Circuit-trace impedances should match output-driver impedance with adequate ground-return paths. This will help minimize signal reflections (overshoot/undershoot) and noise caused by high-speed signal edge rates.
6.2
DC Current Specifications
The M18 device includes specifications for different lithographies, densities, and frequencies. For additional information on combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description.
Table 13: DC Current Specifications (Sheet 1 of 3)
Sym Parameter Litho (nm) Density (Mbit) 1.7 V – 2.0 V Unit Typ — Max ±1 µA VCC = VCC Max VCCQ = VCCQ Max VIN = VCCQ or VSS VCC = VCC Max VCCQ = VCCQ Max VIN = VCCQ or VSS Test Conditions Notes
ILI
Input Load Current
1
ILO
Output Leakage Current 256 90 512 128
— 35 50 45 50 60 70 35 50 45 50 60 70
±1 95 120 115 130 160 185 95 120 115 130 160 185
µA
ICCS
VCC Standby 65
256 512 1,024 256 90 512 128
µA
VCC = VCCMax VCCQ = VCCQMax CE# = VCCQ RST# = VCCQ or GND (for ICCS) WP# = VIH
1,2
ICCAPS
APS 65
256 512 1,024
µA
VCC = VCC Max VCCQ = VCCQ Max CE# = VSSQ RST# = VCCQ All inputs are at rail to rail (VCCQ or VSSQ).
—
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Table 13: DC Current Specifications (Sheet 2 of 3)
Sym Parameter Litho (nm) Density (Mbit) 1.7 V – 2.0 V Unit Typ Max VCC = VCC Max VCCQ = VCCQ M ax CE# = VCCQ RST# = VCCQ ECR[15] = VCCQ DPD = VCCQ or VSSQ All inputs are at rail to rail (VCCQ or VSSQ). VCC = VCCMAX CE# = VIL OE# = VIH Inputs: VIL or VIH VCC = VCCMAX CE# = VIL OE# = VIH Inputs: VIL or VIH VCC = VCCMAX CE# = VIL OE# = VIH Inputs: VIL or VIH VCC = VCCMAX CE# = VIL OE# = VIH Inputs: VIL or VIH VCC = VCCMAX CE# = VIL OE# = VIH Inputs: VIL or VIH VPP = VPPL or VPP = VPPH, program/erase in progress Test Conditions Notes
IDPD
DPD
2
30
µA
8
ICCR
Average VCC Read: Asynchronous Single Word Read f = 5 MHz, (1 CLK)
25
30
mA
1,3,4,5
ICCR
Average VCC Read: Page Mode Read f = 13 MHz, (17 CLK)
Burst = 16 Word
11
15
mA
1,3,4,5
ICCR
Average VCC Read: Synchronous Burst Read f = 66 MHz, LC = 7
Burst = 8 Word Burst = 16 Word Burst = Continuous Burst = 8 Word Burst = 16 Word Burst = Continuous Burst = 8 Word Burst = 16 Word Burst = Continuous
22 19 25 26 23 30 26 24 33 35 256 35 50 45 50 60 70 0.2 2 0.05
32 26 34 36 30 42 35 33 46 50 95 120 115 130 160 185 5 15 0.1
mA mA mA mA mA mA mA mA mA mA
1,3,4,5
ICCR
Average VCC Read: Synchronous Burst Read f = 108 MHz, LC = 10
1,3,4,5
ICCR
Average VCC Read: Synchronous Burst Read f = 133 MHz, LC = 13 VCC Program VCC Erase VCC Blank Check
1,3,4,5
ICCW, ICCE ICCBC
1,3,4, 5,7
90 512 ICCWS, ICCES VCC Program Suspend VCC Erase Suspend 65 512 1,024 IPPS, IPPWS, IPPES IPPR IPPW VPP Standby VPP Program Suspend VPP Erase Suspend VPP Read VPP Program 128 256
µA
CE# = VCCQ; suspend in progress
1,3,6
µA µA mA
VPP = VPPL; suspend in progress VPP ≤ VCC VPP = VPPL = VPPH, program in progress
3 3 3
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Table 13: DC Current Specifications (Sheet 3 of 3)
Sym Parameter Litho (nm) Density (Mbit) 1.7 V – 2.0 V Unit Typ 0.05 0.05 Max 0.1 0.1 mA mA VPP = VPPL = VPPH, erase in progress VPP = VPPL = VPPH, blank check in progress 3 3 Test Conditions Notes
IPPE IPPBC Notes: 1. 2. 3. 4. 5. 6. 7. 8.
VPP Erase VPP Blank Check
All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C. ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted. Sampled, not 100% tested. VCC read + program current is the sum of VCC read and VCC program currents. VCC read + erase current is the sum of VCC read and VCC erase currents. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR ICCW, ICCE measured over typical or max times specified in Section 7.4, “Program and Erase
Characteristics” on page 68
IDPD is the current measured 40 µs after entering DPD.
6.3
DC Voltage Specifications
Table 14: DC Voltage Specifications
Symbol VIL VIH VOL Parameter Input Low Voltage Input High Voltage Output Low Voltage V CCQ 1.7 V – 2.0 V Unit Min 0 VCCQ –0.4 — Max 0.4 VCCQ 0.1 V — — VCC = VCCMIN VCCQ = VCCQMIN IOL = 100 µA VCC = VCCMIN VCCQ = VCCQMIN IOH = –100 µA — — — 1 — — Test Condition Notes
VOH VPPLK VLKO VLKOQ
Output High Voltage VPP Lock-Out Voltage VCC Lock Voltage VCCQ Lock Voltage
VCCQ –0.1 — 1.0 0.9
— 0.4 — —
— 2 — —
Notes: 1. During signal transitions, voltage can undershoot to –1.0 V and overshoot to maximum VCCQ+1.0 V for durations of < 2 ns. 2. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
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6.4
Capacitance
Table 15: Capacitance
Symbol CIN COUT Parameter Input Capacitance (Address, CLK, CE#, OE#, ADV#, WE#, WP#, DPD and RST#) Output Capacitance (Data and WAIT) Min 2 2 Typ 4 5 Max 6 6 Unit Condition VIN = 0 - 2.0 V VOUT = 0 - 2.0 V Notes
pF
1,2
Notes: 1. TC = +25°C, f = 1 MHz. 2. Sampled, not 100% tested. 3. Silicon die capacitance only. Add 1 pF for discrete packages; for SCSP total capacitance equals 2 pF + sum of silicon die capacitance.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.0
NOR Flash AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the following conventions:
Figure 17: Timing Symbol Notation Convention
t
Source Signal Source State
Signal Address Data - Read Data - Write Chip Enable (CE#) Output Enable (OE#) Write Enable (WE#) Address Valid (ADV#) Reset (RST#) Clock (CLK) WAIT
ELQV
Target State Target Signal
Table 16: Codes for Timing Signals and Timing States
Code A Q D E G W V P C T State High Low High-Z Low-Z Valid Invalid — — — — Code H L Z X V I — — — —
Note:
Exceptions to this conventions include tACC and tAPA. tACC is a generic timing symbol that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash device datasheet, and is the address-to-data delay for subsequent page-mode reads.
7.1
AC Test Conditions
Figure 18: AC Input/Output Reference Waveform
VC CQ Input 0V V CC Q/2
V IH
Test Points
V IL tRISE/FALL
VC CQ /2
Output
Note:
AC test inputs are driven at VCCQ for Logic ‘1’ and 0.0 V for Logic ‘0’. Input/output timing begins and ends at VCCQ/2.
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Table 17: AC Input Requirements
Symbol tRISE/FALL tASKW Parameter Inputs rise/fall time (Address, CLK, CE#, OE#, ADV#, WE#, WP#) Address-Address skew Frequency @133MHz, 108MHz @66MHz Min 0.3 0 0 Max 1.2 3 3 ns Unit Condition VIL to VIH or VIH to VIL At VCCQ/2
Figure 19: Transient Equivalent Testing Load Circuit
Device Under Test
CL
Out
Notes: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance.
Table 18: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration 1.7 V Standard Test 2.0 V Standard Test CL (pF) 30 30
Figure 20: Clock Input AC Waveform
R201
R202
CLK [C] V CCQ /2
V IL R203
CLKINPUT.vsd
V IH
7.2
Read Specifications
Read specifications for 108 MHz and 133 MHz M18 devices are included here. For additional information on lithography, density, and frequency combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description. Devices which support frequencies up to 133 MHz must meet additional timing specifications for synchronous reads (for address latching with CLK) as listed in Table 20, “AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V” on page 51.
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Table 19: AC Read, 108 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 1 of 2)
96 ns Nbr. Symbol Parameter1 Min Asynchronous Specifications R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGHTV tGLTV tGLTX tGHTZ Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# high to WAIT valid (AD-Mux only) OE# low to WAIT valid OE# low to WAIT in low-Z OE# low to WAIT in high-Z (non-mux only) 96 — — — — 0 0 — — 0 7 — — — — 0 0 — 96 96 20 150 — — 9 9 — — 11 9 7 7 — 9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns — — 3 — — 3 3 3 — — — 2 — 3 2,3 Max Unit Notes
Latching Specifications R101 R102 R103 R104 R105 R106 R107 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tVHGL tAPA tPHVH Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high ADV# high to OE# low (AD-Mux only) Page address access (non-mux only) RST# high to ADV# high 5 9 — 7 7 5 7 — 30 — — 96 — — — — 15 — ns ns ns ns ns ns ns ns ns — — — — — 4 — — —
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time — 9.26 0.45 0.3 108 — 0.55 1.2 MHz ns CLK period ns — — — —
Synchronous Specifications R301 R302 tAVCH tVLCH Address setup to CLK high ADV# low setup to CLK high 5 5 — — ns ns — —
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Table 19: AC Read, 108 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
96 ns Nbr. Symbol Parameter 1 Min R303 R304 R305 R306 R307 R311 R312 tELCH tCHQV tCHQX tCHAX tCHTV tCHVL tCHTX CE# low setup to CLK high CLK to output valid Output hold from CLK high Address hold from CLK high CLK high to WAIT valid CLK high to ADV# Setup WAIT hold from CLK 5 — 2 5 — 2 2 Max — 7 — — 7 — — ns ns ns ns ns ns ns — — — 4 — — — Unit Notes
Notes: 1. See Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 1 of 2)
96 ns Nbr. Symbol Parameter 1 Min Asynchronous Specifications R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGHTV tGLTV tGLTX tGHTZ Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# high to WAIT valid (AD-Mux only) OE# low to WAIT valid OE# low to WAIT in low-Z OE# high to WAIT in high-Z (non-mux only) 96 — — — — 0 0 — — 0 7 — — — — 0 0 — 96 96 7 150 — — 7 7 — — 8 7 5.5 5.5 — 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns — — 3 — — 3 3 3 — — — 2 — 3 2,3 Max Units Notes
Latching Specifications R101 R102 R103 tAVVH tELVH tVLQV Address setup to ADV# high CE# low to ADV# high ADV# low to output valid 5 7 — — 96 ns ns ns — — —
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Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
96 ns Nbr. Symbol Parameter1 Min R104 R105 R106 R107 R108 R111 tVLVH tVHVL tVHAX tVHGL tAPA tPHVH ADV# pulse width low ADV# pulse width high Address hold from ADV# high ADV# high to OE# low (AD-Mux only) Page address access (non-mux only) RST# high to ADV# high 7 7 5 2 — 30 Max — — — — 15 — ns ns ns ns ns ns — — — — — — Units Notes
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time — 7.5 0.45 0.3 133 — 0.55 1.2 MHz ns CLK Period ns — — 4 —
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 R311 R312 R313 R314 R315 R316 R317 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV tCHVL tCHTX tCHVH tCHGL tACC tVLVH tVHCH Address setup to CLK high ADV# low setup to CLK high CE# low setup to CLK high CLK to output valid Output hold from CLK high Address hold from CLK high CLK high to WAIT valid CLK high to ADV# Setup WAIT hold from CLK high ADV# hold from CLK high CLK to OE# low (AD-Mux only) Read access time from address latching clock ADV# pulse width low for sync reads ADV# high to CLK high 2 2 2.5 — 2 2 — 2 2 2 2 96 1 2 — — — 5.5 — — 5.5 — — — — — 2 — ns ns ns ns ns ns ns ns ns ns ns ns clks ns — — — — — — — — — — — — — —
Notes: 1. See Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested.
7.2.1
Read Timing Waveforms
The following sections show the timing waveforms for Asynchronous and Synchronous read specifications for Non-Mux and AD-Mux M18 devices. The Synchronous read timing waveforms apply to both the 108 and 133 MHz devices. However please note that M18 devices which only support up to 108 MHz need not meet the R313 to R317 timing specifications.
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Please note that the WAIT signal polarity in all the timing waveforms is low-true (RCR10 = 0). WAIT is shown as de-asserted with valid data (RCR8 = 0). WAIT is deasserted during asynchronous reads.
Table 21: List of Read Timing waveforms
M18 Device Async Page-Mode Read Non-Mux Synchronous 8- or 16-word Burst Read Synchronous Continuous Mis-aligned Burst Read Synchronous Burst with Burst-Interrupt Async Single-Word Read ADMux Synchronous 8- or 16-word Burst Read Synchronous Continuous Mis-aligned Burst Read Synchronous Burst with Burst-Interrupt Description
7.2.2
Timings: Non-Mux Device, Async Read
Figure 21: Async Page-Mode Read (Non-Mux)
R1 R2 R106 A[MAX:4] A[3:0] R101
R111 R105 R104 R103 ADV# R102 R3 CE# R4 OE# R12 R15 R16 WAIT R9 R8 R7 R6 DQ[15:0] R5 RST# R108 R10 R108 R10 R108 R10 R10 R17 R11 R13
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.2.3
Timings: Non-Mux Device, Sync Read
Figure 22: Sync Single-Word Array/Non-Array Read, 108 MHz
Latency Count R301 CLK [C] R2 Address [A] R101 R105 R104 ADV# [V] R303 R102 R3 CE# [E] R7 OE# [G] R16 WAIT [T] R4 R304 Data [D/Q] R305 R8 R9 R307 R13 R106 R306
Figure 23: Synchronous 8- or 16-word Burst Read (Non-Mux)
R1 Latency Count R201 R202 R202
CLK R306 R302 A[MAX:0] R301 R101 R106 R317 R104 R316 R311 ADV# R11 R102 R303 CE# OE# R16 R15 R12 WAIT R315 R7 R4 R103 R3 R2 DQ[15:0] R111 R5 RST# R304 R8 R305 R304 R305 R304 R9 R307 R307 R312 R17 R13 R313 R105
Notes: 1. 8-word and 16-word burst are always wrap-only.
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2. 3.
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only. For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation.
.
Figure 24: Synchronous Continuous Mis-aligned Burst (Non-Mux)
R1 Latency Count R201 R202 R202
CLK R306 R302 A[MAX:0] R301 R101 R106 R317 R104 R316 R311 ADV# R102 R303 CE# OE# R12 R15 R16 WAIT R315 R4 R103 R7 R6 R2 R3 DQ[15:0] R111 R5 RST # Q R304 R305 R304 Q Q End of WL Q Q R307 R307 R312 R307 R312 R17 R13 R11 R313 R105
R10 R10 R9 R305 R304 R8 Q
Notes: 1. R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only. 2. For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation.
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Numonyx™ StrataFlash® Cellular Memory (M18)
. Figure 25: Sync Burst with Burst-Interrupt (Non-Mux)
R202 Latency Count CLK R302 A[M AX:0] R301 R101 R106 R317 R313 R311 ADV# R303 R102 CE# OE# R12 R16 R15 WAIT R315 R7 R4 R103 R6 R2 R3 DQ[15:0] R111 R5 RST# Q R304 R304 R305 Q Q Q R305 R307 R307 R312 R11 R102 R303 R104 R316 R311 R105 R104 R316 R313 R301 R101 R10 R306 R302 R306 R1 R201 R202
Notes: 1. R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only 2. For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation. 3. A burst can be interrupted by toggling CE# or ADV#. If ADV# interrupts burst, then R105 applies.
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7.2.4
Timings: AD-Mux Device, Async Read
Figure 26: Async Single-Word Read (AD-Mux)
R1 R2 A[MAX:16] A R7 A/DQ[15:0] A Q A R101 R101 R106 R106 A R7 Q R2 R1
R111 R103 R104 R105 ADV# R10 R8 R11 R104 R103
R102 R3 CE# R4 R107 OE# R12 WAIT R5 RST#
R102 R3
R10 R8
R4 R9 R107 R9
R13
R12
R13
Note:
Diagram shows back-to-back read operations.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.2.5
Timings: AD-Mux Device, Sync Read
.
Figure 27: Synchronous 8- or 16-word burst read (AD-Mux)
Latency Count R202 R202 CLK A[MAX:16] A R315 R302 A/DQ[15:0] A R313 R301 R101 R106 R317 R104 R103 R311 ADV# R303 R102 R3 CE# R7 R107 R314 OE# R307 R12 WAIT R111 R5 RST# R15 R16 R4 R10 R9 R11 R316 R105 R311 R316 R104 R301 R101 R10 R306 R2 Q Q Q R304 R304 R305 R302 A R313 R306 A R1 R201
R303 R102
Notes: 1. 8-word and 16-word burst are always wrap-only. 2. R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
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Figure 28: Synchronous Continuous Mis-Aligned Burst (AD-Mux)
R1 Latency Count R201 R202 R202
CLK A[MAX:16] A R306 R315 R2 R302 A/DQ[15:0] A R104 R301 R101 R106 R317 R316 R103 R311 ADV# R102 R3 R303 CE# R107 R314 OE# R307 R12 WAIT R111 R5 RST# R15 R16 R307 R312 R307 R312 R14 R13 R7 R4 R10 R9 R11 R8 R10 R313 R304 Q Q Q End of WL Q Q Q R304 R305 R304 R305
R105
Note:
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
Figure 29: Synchronous Burst with Burst-Interrupt (AD-Mux)
R1 R201 R202 R202 CLK A[MAX:16] A R315 R302 A/DQ[15:0] A R313 R301 R101 R106 R317 R104 R103 R311 ADV# R303 R102 R3 CE# R7 R107 R314 OE# R307 R12 WAIT R111 R5 RST# R15 R16 R4 R10 R9 R11 R316 R105 R311 R316 R104 R301 R101 R10 R306 R2 Q Q Q R304 R304 R305 R302 A R313 R306 A
Latency Count
R303 R102
Notes: 1. R2, R3 and R103 apply to legacy-latching only (ADV# OR CLK latching); R315 and R316 apply to clock-only latching only 2. A burst can be interrupted by toggling CE# or ADV#.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.3
Write Specifications
The M18 device includes specifications for different lithographies, densities, and frequencies. For additional information on combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description.
Table 22: AC Write Specifications
N umber W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Symbol tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL tVLWH tWHQV Parameter
(1, 2)
Min 150 0 40 40 40 0 0 0 20 200 0 0 200 0 55 tAVQV +30
Max — — — — — — — — — — — — — — — —
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1,2,3 1,2 1,2,4
RST# high recovery to WE# low CE# setup to WE# low WE# write pulse width low Data setup to WE# high Address setup to WE# high CE# hold from WE# high Data hold from WE# high Address hold from WE# high (non-mux only) WE# pulse width high VPP setup to WE# high VPP hold from Status read WP# hold from Status read WP# setup to WE# high WE# high to OE# low ADV# low to WE# high (AD-Mux only) WE# high to read valid
1,2
1,2,5
1,2,3,7
1,2,8 1,2 1,2,3,9
Write to Synchronous Read Specifications W19 W27 W28 tWHCH tWHEL tWHVL WE# high to Clock high WE# high to CE# low WE# high to ADV# low 15 9 7 — — — ns ns ns 1,2,3,6,9 1,2,3,6,9 1,2,3,6,9
Bus Write with Active Clock Specifications W21 W22 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. tVHWL tCHWL ADV# high to WE# low Clock high to WE# low — — 27 27 ns ns 1,2,10,11
Write timing characteristics during erase suspend are the same as write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL). tWHCH must be met when transitioning from a write cycle to a synchronous burst read. In addition there must be a CE# toggle after WE# goes high. VPP and WP# should be at a valid level until erase or program success is determined. When doing a Read Status operation following any command that alters the Status Register data, W14 is 20ns. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. This specification is applicable only if the part is configured in synchronous mode and an active clock is running. Either tVHWL or tCHWL must be met depending on the whether the address is latched on ADV# or CLK. These specifications are not applicable to 133 MHz devices.
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7.3.1
Write Timing Waveforms
The following sections show the timing waveforms for write specifications and write-toread and read-to-write transitions for Non-Mux and AD-Mux M18 devices. The Synchronous read timings apply to both the 108 and 133 MHz devices. However please note that M18 devices which only support up to 108 MHz need not meet the R313 to R317 timing specifications. Please note that the WAIT signal polarity in all the timing waveforms is low-true (RCR10 = 0). WAIT is de-asserted during asynchronous reads.
Table 23: List of Write Timing waveforms
M18 Device Write to Write Async Read to Write Non-Mux Write to Async Read Sync Read to Write Write to Sync Read Write to Write Async Read to Write ADMux Write to Async Read Sync Read to Write Write to Sync Read Description
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7.3.2
Timings: Non Mux Device
Figure 30: Write to Write (Non-Mux)
W5 Addres s [A] ADV# W2 CE# [E} W3 WE# [W] OE# [G] W7 W4 Data [D/Q] W1 RST# [P] W13 WP# W4 W7 W9 W3 W6 W2 W6 W8 W5 W8
Figure 31: Async Read to Write (Non-Mux)
Address [A]
A R105
A
ADV# [V] R11 CE# [E] OE# [G] W6 W2 W15 WE# [W] R4 R2 R3 D/Q[15:0] R15 WAIT [T] Q R17 R10 R8 R9 W3
W7 W4 D
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Figure 32: Write to Async Read (Non-Mux)
A ddress [A] ADV# [V] W2 CE# [E] W5
Write Ad r
Read Adr
R11
W6 W3 W8
WE# [W] W14 OE# [G] High-Z R15 R17
WAIT [T]
R4 W7 W4 Data [D/Q] D W16 Q R3 R2 R9 R10 R8
. Figure 33: Sync Read to Write (Non-Mux)
R311 CLK [C] R301 Address [A] R303 CE# [E] R302 R316 ADV# [V] W3 WE# [W] OE# [G] R305 R304 Q0 High-Z R307 Q1 High-Z R11 R306 W5 R313 W22
R105
R304 Data [D/Q]
R305
W4 D
W7
WAIT [T]
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Figure 34: Write to Sync Read (Non-Mux)
W19 R302 R303 CLK R301 Address [A] Wrt Addr R311 R105 ADV# [V] W9 R11 W27 CE# [E] W3 W22 WE# [W] W14 OE# [G] W7 W4 Data [D/Q] D R307 R15 WAIT [T] R304 R304 R305 Q0 R304 R305 Q1 W28 R313 Rd Addr
R305 Q2
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7.3.3
Timings: AD-Mux Device
Figure 35: Write to Write (AD-Mux)
A[max-16] [A] W5 W4 R101 A/DQ[15-0] [A/D] A R106 ADV# [v] W2 CE# [E] W3 WE# [W] OE# [G] W1 RST# [P] W13 WP# W9 W3 W6 W2 W6 D W7 A W15 D
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Figure 36: Async Read to Write (AD-Mux)
A[Max:16]
A R2 R10 Q R105
A
A/DQ[15:0] R101 ADV# [V]
A
A
D
R3 CE# [E] R4 R107 OE# [G]
R8 R11
R9
W7 W3 W4 W15 WE# [W] R12 WAIT [T] R13 R12 R13
Figure 37: Write to Async Read (AD-Mux)
W5 A[Max:16] A W4 W7 A/DQ[15:0] A D R11 W6 CE# [E] R105 W15 ADV# [V] W2 WE# [W] R4 R107 W14 OE# [G] R12 R13 R9 W3 R3 R8 A R2 Q A
R12 WAIT [T]
R13
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Figure 38: Sync Read to Write (AD-Mux)
R311 CLK [C] R301 A[Max:16] A R305 R304 Q0 Q1 R11 R306 A W5 R313 W22
R304 A /DQ[15:0] A R303 CE# [E] R302 R316 ADV# [V]
R305 A D
W15
W7 W4 WE# [W] OE# [G] High-Z R307 High-Z
WAIT [T]
Notes: 1. CLK may be stopped during write cycle. 2. W22 is the time between the Address-latching-CLK and WE#. In case of ADV#-latching, W21 must be met instead.
Figure 39: Write to Sync Read (AD-Mux)
W19 CLK W5 A[Max:16] A W4 W7 A /DQ[15:0] A D A R307 R15 WAIT [T ] R105 W15 ADV# [V] R11 CE# [E] W3 W22 WE# [W] W14 OE# [G] W27 W28 R304 A R305 R304 Q0 R305 R304 Q1
R305 Q2
Note:
CLK may be stopped during write cycle.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.4
Program and Erase Characteristics
The M18 device includes specifications for different lithographies, densities, and frequencies. For additional information on combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description.
Table 24: Program-Erase Characteristics
VPPL/V PPH Nbr. Symbol Parameter Litho (nm) Conventional Word Programming Single word (first word) Single word (subsequent word) — — — — — — 115 50 230 µs 230 1,2 Density (Mbit) Unit Min Typ Max Notes
W200
tPROG/W
Program Time
Buffered Programming W200 tPROG/W Program Time Single word One Buffer (512 words) — 90 65 — 256, 512 128, 256, 512, 1024 — 1.02 2.05 — 250 2.15 500 4.3 ms µs 1
W250
tPROG/PB
Buffered Enhanced Factory Programming 90 W451 tBEFP/W tBEFP/
Setup
256, 512 — 128, 256, 512 — 5
4.2 — 2.0 — — µs 1 1,3,4
Program Time
Single word 65 Buffered EFP Setup —
W452
Erasing and Suspending W501 W600 W601 tERS/MAB tSUSP/P tSUSP/E Erase Time Suspen d Latency 128-Kword Main Array Block Program suspend Erase suspend — — — — — — — — — 0.9 20 20 4 30 30 s 1 1 1
µs
Blank Check W702 tBC/MB Blank Check Main array block — — — 3.2 — ms 1
Notes: 1. Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Sampled, but not 100% tested. 2. First and subsequent words refer to first word and subsequent words in Control Mode programming region. 3. Averaged over entire device. 4. BEFP not validated at VPPL.
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7.5
Reset Specifications
Table 25: Reset Specifications
Nbr. P1 P2 P3 Notes: 1. 2. 3. 4. 5. 6. 7. Symbol tPLPH tPLRH tVCCPH Parameter RST# pulse width low RST# low to device reset during erase RST# low to device reset during program VCC Power valid to RST# de-assertion (high) Min 100 — — 300 25 25 — µs Max Unit ns Notes 1,2,3,4,7 1,3,4,7 1,3,4,7 1,4,5,6
These specifications are valid for all device versions (packages and speeds). The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed. Not applicable if RST# is tied to Vccq. Sampled, but not 100% tested. If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥ VCC(min). Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Figure 40: Reset Operation Timing
P1 R5
(A) Reset during read mode
RST# [P]
VIH VIL
P2
(B) Reset during program or block erase P1 ≤ P2
Abort Complete
R5
RST# [P]
VIH VIL
P2
(C) Reset during program or block erase P1 ≥ P 2
Abort Complete
R5
RST# [P]
VIH VIL
P3
(D) VCC Power-up to RST# high
VCC
VCC 0V
7.6
Deep Power Down Specifications
Table 26: Deep Power Down Specifications (Sheet 1 of 2)
Nbr. S1 Symbol tSLSH (tSHSL) Parameter DPD asserted pulse width Min 100 Max — Unit ns Notes 1,2,3
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Table 26: Deep Power Down Specifications (Sheet 2 of 2)
Nbr. S2 S3 S4 Symbol tEHSH (tEHSL) tSHEL (tSLEL) tPHEL Parameter CE# high to DPD asserted DPD deasserted to CE# low RST# high during DPD state to CE# low (DPD deasserted to CE# low) Min 0 75 75 Max — — — µs Unit Notes 1,2 1,2 1,2
Notes: 1. These specifications are valid for all device versions (packages and speeds). 2. Sampled, but not 100% tested. 3. DPD must remain asserted for the duration of Deep Power Down mode. DPD current levels are achieved 40 µs after entering the DPD mode.
Figure 41: Deep Power Down Operation Timing
S2 S1 DPD [S] S3 CE# [E] RST# [P]
Note: DPD pin is low-true (ECR14 = 0)
Figure 42: Reset During Deep Power Down Operation Timing
RST# [P] S2 DPD [S] S4 CE# [E]
Note: DPD pin is low-true (ECR14 = 0)
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8.0
NOR Flash Bus Interface
The flash device uses low-true control signal inputs, and is selected by asserting the chip enable (CE#) input. The output enable (OE#) input is asserted for read operations, while the write enable (WE#) input is asserted for write operations. OE# and WE# should never be asserted at the same time; otherwise, indeterminate device operation will result. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Commands are written to the device to control all operations. Table 27 shows the logic levels that must be applied to the control-signal inputs of the device for the various bus operations.
Table 27: Flash Memory Control Signals
Operation Reset Read Output Disable RST# Low High High High Write High Standby Deep Power-Down High High High High Low High High High X X Low X X Valid X X Input High-Z High-Z DPD2 High High High High CE#1 X Low Low Low OE#1 X Low High High WE# 1 X High High Address1 X Valid X Valid Data I/O High-Z Output High-Z Input
Notes: 1. X = Don’t care (High or Low) 2. DPD polarity determined by ECR14. Shown low-true here.
8.1
Bus Reads
To perform a read operation, both CE# and OE# must be asserted; #RST# and WE# must be deasserted. OE# is the data-output control and when asserted, the output data is driven on to the data I/O bus. All read operations are independent of the voltage level on VPP. The Automatic Power Savings (APS) feature provides low power operation following reads during active mode. After data is read from the memory array and the address lines are quiescent, APS automatically places the device into standby. In APS, device current is reduced to ICCAPS. The device supports two read configurations: • Asynchronous reads. RCR15 = 1. This is the default configuration after power-up/ reset. — Non-multiplexed devices support asynchronous page-mode reads. ADMultiplexed devices support only asychronous single-word reads. • Synchronous Burst reads. RCR15 = 0.
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8.1.1
Asynchronous single-word reads
In asynchronous single-word read mode, a single word of data corresponding to the address is driven onto the data bus after the initial access delay. The address is latched when ADV# is deasserted. For AD-multiplexed devices, ADV# must be deasserted before OE# is asserted. If only asynchronous reads are to be performed, CLK must be tied to a valid VIH or VIL level, and the WAIT signal can be floated. In addition, for non-multiplexed devices, ADV# must be tied to ground.
8.1.2
Asynchronous Page Mode (Non-multiplexed devices only)
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address is driven onto the data bus after the initial access delay. Subsequent words in the page are output after the page access delay. A[3:0] bits determine which page word is output during a read operation. A[MAX:4] and ADV# must be stable throughout the page access. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored.
8.1.3
Synchronous Burst Mode
Synchronous burst mode is a clock-synchronous read operation that improves the read performance of flash memory over that of asynchronous reads. Synchronous burst mode is enabled by programming the Read Configuration Register (RCR) of the flash memory device. The RCR is also used to configure the burst parameters of the flash device, including Latency Count, burst length of 8, 16 and continuous, and WAIT polarity. Three additional signals are used for burst mode: CLK, ADV#, and WAIT. The address for synchronous read operations is latched on the ADV# rising edge or the first rising CLK edge after ADV# low, whichever occurs first for devices that support up to 108 MHz. For devices that support up to 133 MHz, the address is latched on the last CLK edge when ADV# is low. During synchronous read modes, the first word is output from the data buffer on the rising CLK edge after the initial access latency delay. Subsequent data is output on rising CLK edges following a tCHQV delay. However, for a synchronous non-array read, the same word of data will be output on successive rising clock edges until the burst length requirements are satisfied.
8.1.3.1
WAIT Operation
Upon power up or exit from reset, WAIT polarity defaults to low-true operation (RCR10 = 0). During synchronous reads (RCR15 = 0), WAIT asserts when read data is invalid, and deasserts when read data is valid. During asynchronous reads (RCR15 = 1), WAIT is deasserted. During writes, WAIT is High-Z on non-mux devices, and deasserted on AD-mux devices. Table 28 summarizes WAIT behavior.
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Table 28: WAIT Behavior Summary
Device Operation Device not selected Standby Output Disable Non-Mux Device Sync Read Async Read Write Output Disable AD-Mux Device Sync Read Async Read Write Low CE# High X High Low Low High High Low Low High OE# X High High High Low High High High Low WE# WAIT High-Z High-Z Active Deasserted High-Z Deasserted Active Deasserted Deasserted 2 2 1 Notes
Notes: 1. X = don’t care (high or low). 2. Active: WAIT asserted = invalid data; WAIT deasserted = valid data.
8.2
Bus Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. All device write operations are asynchronous, with CLK being ignored, but CLK can be kept active/toggling. During a write operation in non-muxed devices, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. During a write operation in muxed devices, address is latched during the rising edge of ADV# OR CE# whichever occurs first and Data is latched during the rising edge of WE# OR CE# whichever occurs first.
8.3
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. The device shuts down any operation in progress, a process which takes a minimum amount of time to complete. To return from reset mode, RST# must be deasserted. Normal operation is restored after a wake-up interval.
8.4
Deep Power-Down
The device enters DPD mode when the following two conditions are met: ECR15 is set(1) and DPD is asserted. The two conditions can be satisfied in any order. ECR14 bit determines the DPD asserted logic level. While in this mode, RST# and CE# must be deasserted. The device exits DPD mode when DPD is deasserted. There is an exit latency before the device returns to standby mode and any operations are allowed. See the datasheet for the timing specifications. The device should not be placed in DPD mode when a program/erase operation is ongoing or suspended. If the device enters DPD mode in the middle of a program, erase or suspend, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid.
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While in DPD mode, the read-mode of each partition, configuration registers (RCR and ECR), and block lock bits, are preserved. Status register is reset to 0080h; i.e., if the Status register contains error bits, they will be cleared.
8.5
Standby
When CE# is deasserted, the device is deselected and placed in standby, substantially reducing power consumption. In standby, data outputs are placed in high-Z, independent of the level placed on OE#. If deselected during a Program or Erase operation, the device continues to consume active power until the operation is complete. There is no additional latency for subsequent read operations.
8.6
Output Disable
When OE# is deasserted with CE# asserted, the device outputs are disabled. Output pins are placed in a high-impedance state. WAIT is deasserted in AD-muxed devices and driven to High-Z in non-multiplexed devices.
8.7
Bus Cycle Interleaving
When issuing commands to the device, a read operation can occur between the two write cycles of a 2-cycle command. (See Figure 43 and Figure 44) However, a write operation cannot occur between the two write cycles of a 2-cycle command and will cause a command sequence error (See Figure 45).
Figure 43: Operating Mode with Correct Command Sequence Example
A ddress [A] WE# [W] OE# [G] Data [D/Q]
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
Figure 44: Operating Mode with Correct Command Sequence Example
Address [A] WE# [W] OE# [G] Data [D/Q]
P artition A
Partition B
Partition A
0x20
Valid Array Data
0xD0
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Figure 45: Operating Mode with Illegal Command Sequence Example
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition A
Partition B
Partition A
Partition A
0x20
0xFF
0xD0
SR[7:0]
8.7.1
Read Operation During Program Buffer fill
Due to the large buffer size of devices, the system interrupt latency may be impacted during the buffer fill phase of a buffered programming operation. Please refer to the relevant Application Note listed in Section 1.4, “Additional Information” on page 7 to implement a software solution for your system.
8.8
Read-to-Write and Write-to-Read Bus Transitions
Consecutive read and write bus cycles must be properly separated from each other to avoid bus contention. These cycle separation specs are described in the sections below.
8.8.1
Write to Asynchronous read transition
To transition from a bus write to an asynchronous read operation, either CE# or ADV# must be toggled after WE# goes high.
8.8.2
Write to synchronous read transition
To transition from a bus write to a synchronous read operation, either CE# or ADV# must be toggled after WE# goes high. In addition, W19 (tWHCH -WE# high to CLK high) must be met.
8.8.3
Asynchronous/Synchronous read to write transition
To transition from a asynchronous/synchronous read to a write operation, either CE# or ADV# must be toggled after OE# goes high.
8.8.4
Bus write with active clock
To perform a bus write when the device is in synchronous mode and the clock is active, W21 (tVHWL- ADV# High to WE# Low) or W22 (tCHWL -Clock high to WE# low) must be met.
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9.0
NOR Flash Operations
This section describes the operational features of NOR flash memory. Operations are command-based—command codes are first issued to the device, and then the device performs the desired operation. All command codes are issued to the device using buswrite cycles as explained in Section 3.0, “NOR Flash Bus Interface” on page 10. A complete list of available command codes can be found in Section 5.0, “Device Command Codes” on page 40.
9.1
Status Register
The Status Register (SR) is a 16-bit, read-only register that indicates device and partition status, and operational errors. To read the Status Register, issue the Read Status Register command. Subsequent reads output Status Register information on AD/DQ[15:10]. SR status bits are set and cleared by the device. SR error bits are set by the device, and must be cleared using the Clear Status Register command. Upon power-up or exit from reset, the Status Register defaults to 0080h.
Table 29: Status Register Bit Definitions (Sheet 1 of 2)
Status Register (SR) Bits Region Program Status 9-8 Erase Suspend Status 6 Program /Erase Voltage Error 3 Program Suspend Status 2 Default Value = 0080h BlockLocked Error 1
Reserved
Ready Status
Erase Error
Program Error
Partition Status
15-10
7
5
4
0
Bit 15-10 Reserved
Name
Description Reserved for future use; these bits will always be set to zero. SR9 0 1 SR8 0 = Region program successful. 0 = Region program error - Attempted write with object data to Control Mode region. 1 = Region program error - Attempted rewrite to Object Mode region. 1 = Region program error - Attempted write using illegal command. SR4 will also be set along with SR[8,9] for the above error conditions.
9-8
Region Program Status
0 1
7 6
Ready Status Erase Suspend Status Erase Error / Blank Check Error Program Error V PP Error
0 1 0 1
= Device is busy; SR[9:8], SR[6:1] are invalid; = Device is ready; SR[9:8], SR[6:1] are valid. = Erase suspend not in effect. = Erase suspend in effect. SR4 0= 1= 0= 1=
5
Command Sequence Error
4 3
SR5 0 0 1 1 0 1
Program or erase operation successful. Program error - operation aborted. Erase error: operation aborted / Blank check error: operation failed. Command sequence error - command aborted.
= VPP within acceptable limits during program or erase operation. = VPP not within acceptable limits during program or erase operation.
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Table 29: Status Register Bit Definitions (Sheet 2 of 2)
Status Register (SR) Bits Region Program Status 9-8 Erase Suspend Status 6 Program /Erase Voltage Error 3 Program Suspend Status 2 Default Value = 0080h BlockLocked Error 1
Reserved
Ready Status
Erase Error
Program Error
Partition Status
15-10
7
5
4
0
Bit 2 1
Name Program Suspend Status Block-Locked Error 0 1 0 1
Description = Program suspend not in effect. = Program suspend in effect. = Block NOT locked during program or erase - operation successful. = Block locked during program or erase - operation aborted. SR0 0 = Active program or erase operation in addressed partition. BEFP: Program or Verify complete, or Ready for data. 1 = Active program or erase operation in other partition. BEFP: Program or Verify in progress. 0 = No active program or erase operation in any partition. BEFP: Operation complete 1 = Reserved.
SR7 0 0 Partition Status 0 1 1
9.1.1
Clearing the Status Register
The Status Register (SR) contain status and error bits which are set by the device. SR status bits are cleared by the device; however, SR error bits are cleared by issuing the Clear Status Register command. Resetting the device also clears the Status Register.
Table 30: Clear Status Register Command Bus Cycles
Setup Write Cycle Command Address Bus Clear Status Register Device Address Data Bus 0050h --Address Bus --Data Bus Confirm Write Cycle
Depending on the current state of the partition, issuing the Clear Status Command will place the addressed partition in Read Status mode. Please see 'Next State' Table for further details. Other partitions are not affected. Note: Care should be taken to avoid Status Register ambiguity. If a command sequence error occurs while in an Erase Suspend condition, the Status Register will indicate a Command Sequence error by setting SR4 and SR5. When the erase operation is resumed (and finishes), any errors that may have occurred during the erase operation will be masked by the Command Sequence error. To avoid this situation, clear the Status Register prior to resuming a suspended erase operation. The Clear Status Register command functions independent of the voltage level on VPP.
9.2
Read Configuration Register
The Read Configuration Register (RCR) is a 16-bit read/write register used to select bus-read modes, and to configure synchronous-burst read characteristics of the flash device. All Read Configuration Register bits are set and cleared using the Program Read Configuration Register command.
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Upon power-up or exit from reset, the Read Configuration Register defaults to asynchronous mode (RCR15 = 1; RCR[14:11] and RCR[9:0] are ignored). To read the RCR value, issue the Read Device Information command to the desired partition. Subsequent reads from the + 05h will output RCR[15:0] on the data bus. When using a Latency Count of Code 2 and a Data Hold of two cycles (CR9 = 1), WAIT must be configured to deassert with valid data (CR8 = 0).
Table 31: Read Configuration Register Bit Definitions
Read Configuration Register (RCR) Read Mode 15 14 Latency Count 13 12 11 WAIT Polarity 10 R 9 WAIT Delay 8 Reserved 7:3 Default: CR15 = 1 Burst Length 2 1 0
Bit 15 Read Mode
Name
Description 0 = Synchronous burst-mode reads 1 = Asynchronous page-mode reads (default) Bits: 14 13 12 11 0011= 0100= 0101= 0110= 0111= 1000= 1001= 1010= 1011= 1100= (Other bit settings are 0 1 3 4 5 6 7 8 9 10 11 12 reserved)
14:11
Latency Count
10 9 8 7:3
WAIT Polarity Reserved WAIT Delay Reserved
= WAIT signal is active low (default) = WAIT signal is active high
Write 0 to reserved bits 0 1 = WAIT de-asserted with valid data = WAIT de-asserted one cycle before valid data (default)
Write 0 to reserved bits 0 0 1 1 1 1 0 1 1 = 8-word burst (wrap only) = 16-word burst (wrap only) = Continuous-word burst (no-wrap; default) (Other bit settings are reserved)
2:0
Burst Length
9.2.1
Latency Count
The Latency Count value programmed into RCR[14:11] is the number of valid CLK edges from address-latch to the start of the data-output delay. When the Latency Count has been satisfied, output data is driven after tCHQV.
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Figure 46: Latency Count Period
Latency Count CLK Latch (1) CLK ADV# (1) ADV#-Latch (2) ADV# (2) A[Max:0] CE# OE# tCHQV DQ[15:0]
Notes: 1. Address latched on valid clock edge with ADV# low and LC count begins. 2. Address latched on ADV# rising edge. LC count begins on subsequent valid CLK edge.
Table 32: CLK Frequencies for LC Settings
VCCQ = 1.7 V to 2.0 V Latency Count Setting 3 4 5 6 7 8 9 10 11 12 13 ≤ 32.6 MHz ≤ 43.5 MHz ≤ 54.3 MHz ≤ 65.2 MHz ≤ 76.1 MHz ≤ 87 MHz ≤ 97.8 MHz ≤ 108.7 MHz ≤ 119.6 MHz ≤ 130.4 MHz ≤ 133.3 MHz Frequency Supported (MHz)
9.3
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile 16-bit, read/write register used to select Deep Power Down (DPD) operation and to modify the output-driver strength of the flash device. All Enhanced Configuration Register bits are set and cleared using the Program Enhanced Configuration Register command. Upon power-up or exit from reset, the Enhanced Configuration Register defaults to 0004h. To read the value of the ECR, issue the Read Device Information command to the desired partition. Subsequent reads from the + 06h returns ECR[15:0].
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Table 33: Enhanced Configuration Register Bit Definitions
Enhanced Configuration Register Deep Power Down (DPD) Mode 15 DPD Polarity 14 Reserved 13:3 2 Default = 0004h Output Driver Control 1 0
Bit 15 14 13:3
Name Deep Power Down (DPD) Mode DPD Pin Polarity Reserved 0 1 0 1
Description = DPD Disabled (default) = DPD Enabled = Active Low (default) = Active High
Write 0 to reserved bits Bits: 210 001=1 010=2 011=3 1 0 0 = 4 (default) 101=5 110=6 (Other bit settings are reserved)
2:0
Output Driver Control
9.3.1
Output Driver Control
Output Driver Control enables the user to adjust the device’s output-driver strength of the data I/O bus and WAIT signal. Upon power-up or reset, ECR[2:0] defaults to an output impedance setting of 30 Ohms. To change the output-driver strength, ECR[2:0] must be programmed to the desired setting as shown in Table 34, “Output Driver Control Characteristics”.
Table 34: Output Driver Control Characteristics
Control Bits ECR[2:0] 001 010 011 100 101 110 (1) (2) (3) (4) default (5) (6) Impedance @ VCCQ/2 (Ohm) 90 60 45 30 20 15 Driver Multiplier 1/3 1/2 2/3 1 3/2 2 Load Driven at Same Speed (pF) 10 15 20 30 35 40
9.3.2
Programming the ECR
The ECR is programmed by issuing the Program Enhanced Configuration Register command. This is a two-cycle command sequence requiring a Setup command to be issued first, followed by a Confirm command. Bus-write cycles to the flash device between the setup and confirm commands are not allowed—a command sequence error will result. However, flash bus-read cycles between the Setup and Confirm commands are allowed.
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Table 35: Program Enhanced Configuration Register Command Bus Cycles
Setup Write Cycle Command Address Bus Program Enhanced Configuration Register Register Data Data Bus 0060h Address Bus Register Data Data Bus 0004h Confirm Write Cycle
To program the Enhanced Configuration Register, the desired settings for ECR[15:0] are placed on the address bus. The setup command (0060h) is driven on the data bus. Upon issuing the setup command, the device/addressed partition is automatically changed to Read Status Register mode. Next, the Confirm command (0004h) is driven on the data bus. After issuing the Confirm command, the addressed partition is automatically switched to Read Array mode. This command functions independently of the applied VPP voltage. Note: Since the desired register value is placed on the address lines, any hardwareconnection offsets between the host’s address outputs and the flash device’s address inputs must be considered, similar to programming the RCR.
9.4
Read Operations
The following types of data can be read from the device: array data, device information, CFI data, and device status Upon power-up or return from reset, the device defaults to Read Array mode. To change the device’s read mode, the appropriate command must be issued to the device. Table 36, “Read Mode Command Bus Cycles” shows the command codes used to configure the device for the desired read mode. The following sections describe each read mode.
Table 36: Read Mode Command Bus Cycles
Setup Write Cycle Command Address Bus Read Array Read Status Register Read Device Information CFI Query Partition Address Partition Address Partition Address Partition Address Data Bus 00FFh 0070h 0090h 0098h --------Address Bus --------Data Bus Confirm Write Cycle
9.4.1
Read Array
Upon power-up or exit from reset, the device defaults to Read Array mode. Issuing the Read Array command places the addressed partition in Read Array mode. Subsequent reads output array data. The addressed partition remains in Read Array mode until a different read command is issued, or a program or erase operation is performed in that partition, in which case, the read mode is automatically changed to Read Status. To changea partition to Read Array mode while it is programming or erasing, first issue the Suspend command. After the operation has been suspended, issue the Read Array command to the partition. When the program or erase operation is subsequently resumed, the read state of the partition will not change. To change the read state of the partition to Status read mode, issue a Read Status command to the partition.
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Note:
Issuing the Read Array command to a partition that is actively programming or erasing causes subsequent reads from that partition to output invalid data. Valid array data is output only after the program or erase operation has finished. The Read Array command functions independent of the voltage level on VPP.
9.4.2
Read Status Register
Issuing the Read Status Register command places the addressed partition in Read Status Register mode. Subsequent reads from that partition output Status Register information. The addressed partition remains in Read Status Register mode until a different read-mode command is issued to that partition. Performing a program, erase, or block-lock operation also changes the partition’s read mode to Read Status Register mode. The Status Register is updated on the falling edge of CE#, or OE# when CE# is low. Status Register contents are valid only when SR7 = 1. The Read Status Register command functions independent of the voltage level on VPP.
9.4.3
Read Device Information
Issuing the Read Device Information command places the addressed partition in Read Device Information mode. Subsequent reads output device information on the data bus. The address offsets for reading the available device information are shown here.
Table 37: Device Information Summary
Device Information Device Manufacturer Code (Numonyx) Device ID Code Main Block Lock Status Read Configuration Register Enhanced Configuration Register OTP Lock Register 0 OTP Register - Factory Segment OTP Register - User-Programmable Segment OTP Lock Register 1 OTP Registers 1 through 16 Address Bus Partition Base Address + 00h Partition Base Address + 01h Block Base Address + 02h Partition Base Address + 05h Partition Base Address + 06h Partition Base Address + 80h Partition Base Address + 81h to 84h Partition Base Address + 85h to 88h Partition Base Address + 89h Partition Base Address + 8Ah to 109h 0089h Device IDs D0 = Lock Status D1 = Lock-Down Status Configuration Register Data Enhanced Configuration Register Data Lock Register 0 Data Factory-Programmed Data User Data Lock Register 1 Data User Data Data Bus
The addressed partition remains in Read Device Information mode until a different read command is issued. Also, performing a program, erase, or block-lock operation changes the addressed partition to Read Status Register mode. Note: Issuing the Read Device Information command to a partition that is actively programming or erasing changes that partition’s read mode to Read Device Information mode. Subsequent reads from that partition will return invalid data until the program or erase operation has completed. The Read Device Information command functions independent of the voltage level on VPP.
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9.4.4
CFI Query
Issuing the CFI Query command places the addressed partition in CFI Query mode. Subsequent reads from that partition output CFI information. The addressed partition remains in CFI Query mode until a different read command is issued, or a program or erase operation is performed, which changes the read mode to Read Status Register mode.
Note:
Issuing the CFI Query command to a partition that is actively programming or erasing changes that partition’s read mode to CFI Query mode. Subsequent reads from that partition will return invalid data until the program or erase operation has completed. The CFI Query command functions independent of the voltage level on VPP.
9.5
Programming Modes
To understand programming modes, it is also important to understand the fundamental memory array configuration. The flash device main array is divided as follows: • The main array of the 128-Mbit device is divided into eight 16-Mbit partitions. Each parition is divided into eight 256-KByte blocks: 8 x 8 = 64 blocks in the main array of a 128-Mbit device. • The main array of the 256-Mbit device is divided into eight 32-Mbit partitions. Each partition is divided into sixteen 256-KByte blocks: 8 x 16 = 128 blocks in the main array of a 256-Mbit device. • The main array of the 512-Mbit device is divided into eight 64-Mbit partitions. Each partition is divided into thirty-two 256-KByte blocks: 8 x 32 = 256 blocks in the main array of a 256-Mbit device. • The main array of the 1-Gbit device is divided into eight 128-Mbit partitions. Each partition is divided into sixty-four 256-KByte blocks: 8 x 64 = 512 blocks in the main array of a 1-Gbit device. Each block is divided into as many as two-hundred-fifty-six 1-KByte programming regions. Each region is divided into as many as thirty-two 32-Byte segments. Each programming region in a flash block can be configured for one of two programming modes: Control Mode or Object Mode. The programming mode is automatically set based on the data pattern when a region is first programmed. The selection of either Control Mode or Object Mode is done according to the specific needs of the system with consideration given to two types of information: • Control Mode: Flash File System (FFS) or Header information, including frequently changing code or data • Object Mode: Large, infrequently changing code or data, such as objects or payloads By implementing the appropriate programming mode, software can efficiently organize how information is stored in the flash memory array. Control Mode programming regions and Object Mode programming regions can be intermingled within the same erase block. However, the programming mode of any region within a block can be changed only after erasing the entire block.
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9.5.1
Control Mode
Control Mode programming is invoked when only the A-half (A3 = 0) of the programming region is programmed to 0s, as shown in Figure 47, “Configurable Programming Regions: Control Mode and Object Mode” on page 85. The B-half (A3 = 1) remains erased. Control mode allows up to 512 bytes of data to be programmed in the region. The information can be programmed in bits, bytes, or words. Control Mode supports the following programming methods: — Single-word Programming (0041h) — Buffered Programming (00E9h/00D0h), and — Buffered Enhanced Factory Programming (0080h/00D0h) When buffered programming is used in Control Mode, all addresses must be in the Ahalf of the buffer (A3 = 0). During buffer fill, the B-half (A3 = 1) addresses do not need to be filled with 0xFFFF. Control Mode programming is useful for storing dynamic information, such as FFS Headers, File Info, and so on. Typically, Control Mode programming does not require the entire 512 bytes of data to be programmed at once. It may also contain data that is changed after initial programming using a technique known as “bit twiddling”. Header information can be augmented later with additional new information within a Control Mode-programmed region. This allows implementation of legacy file systems, as well as transaction-based power-loss recovery. In a control mode region, programming operations can be performed multiple times. However, care must be taken to avoid programming any zero’s in the B-half (A3 = 1) of the region. Violation of this usage will cause SR4 and SR9 to be set, and the program operation will be aborted. See Table 38, “Programming Region Next State Table” on page 88 for details.
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Figure 47: Configurable Programming Regions: Control Mode and Object Mode
Main Array
256 KBytes 256 KBytes
256-Kbyte Block
256 programming regions of 1-Kbyte in each 256-Kbyte block
. . . . . . . . . . . . . . . . . . .
256 KBytes 256 KBytes
1 KByte
Programming region in Object Mode Address Bit A3 = 0: Allows up to 1 KByte of data to be programmed .
256 KBytes
512 Bytes A half (Control Mode )
512 Bytes Programming region in Control Mode B half (Erased) Address Bit A3 = 1: Allows up to 512 Bytes of data to be programmed to the A half by bit, byte, or word.
. . .
1 KByte
Programming region in Object Mode
256 KBytes 256 KBytes
1 KByte
Programming region in Object Mode
. .
256 KBytes
. .
9.5.2
Object Mode
Object mode programming is invoked when one or more bits are programmed to zero in the B-half of the programming region (A3 = 1). Object mode allows up to 1KB to be stored in a programming region. Multiple regions are used to store more than 1Kbyte of information. If the object is less than 1Kbyte, the unused content will remain as 0xFFFF (erased). Object Mode supports two programming methods: — Buffered Programming (00E9h/00D0h), and — Buffered Enhanced Factory Programming (0080h/00D0h)
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Single-word programming (0041h) is not supported in Object mode. To perform multiple programming operations within a programming region, Control mode must be used. Object mode is useful for storing static information, such as objects or payloads, that rarely change. Once the programming region is configured in Object mode, it cannot be augmented or over-written without first erasing the entire block containing the region. Subsequent programming operations to a programming region configured in Object mode will cause SR4 and SR8 to be set and the program operation to be aborted. See Table 38, “Programming Region Next State Table” on page 88 for details. Note: Issuing the 41h command to the B-half of an erased region will set error bits SR8 and SR9, and the programming operation will not proceed. See Table 38, “Programming Region Next State Table” on page 88 for more details.
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Figure 48: Configurable Programming Regions: Control Mode and Object Mode Segments
Segments
31 30 Object Object . . Object Object Object Object Program up to 1 KByte of data Programming region in Object Mode Object Object
32 Bytes
Object Object
...
3 2 1 0
1 KByte
. . .
256-Kbyte Block
1 KByte
512 Bytes A half (Control Mode)
512 Bytes B half (Erased)
Program up to 512 Bytes of data
Segments
31 30 Sequence Table Entry Header
Programming region in Control Mode Header Header . . F F F F F F F F F F F F F F F F
...
3 2 1 0
Header File Information Header
Directory Information Header Sequence Table Entry Header
F F F F
F F F F
F F F F
F F F F
F F F F
F F F F
F F F F
F F F F
16 Bytes
16 Bytes
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Table 38: Programming Region Next State Table
Current State of Programming Region Command Issued 0041h to B-half (A3 = 1) 0041h to A-half (A3 = 0) Program Successful SR[4,8,9] = 0 Region configured to Control Mode Program Fail; Illegal Command SR[4,8,9] = 1 00E9h to B-half (A3 = 1) Program Successful SR[4,8,9] = 0 Region configured to Object Mode Program Fail; Object data to Control mode region SR[4,9] = 1 SR8 = 0 00E9h to A-half (A3 = 0) Program Successful SR[4,8,9] = 0 Region configured to Control Mode
Erased
Control Mode
Program Successful SR[4,8,9] = 0
Program Successful SR[4,8,9] = 0
Object Mode
Program Fail; Rewrite to Object mode region SR[4,8] = 1 SR9 = 0
9.6
Programming Operations
Programming the flash array changes ‘ones’ to ‘zeros’. To change zeros to ones, an Erase operation must be performed. Only one programming operation can occur at a time. Programming is permitted during Erase Suspend. Information is programmed into the flash array by issuing the appropriate command. Table 39, “Programming Commands Bus Cycles” shows the two-cycle command sequences used for programming.
Table 39: Programming Commands Bus Cycles
Setup Write Cycle Command Address Bus Single-Word Program Buffered Program Buffered Enhanced Factory Program Device Address Device Address Device Address Data Bus 0041h 00E9h 0080h Address Bus Device Address Device Address Device Address Data Bus Array Data 00D0h 00D0h Confirm Write Cycle
Caution:
All programming operations require the addressed block to be unlocked, and a valid VPP voltage applied throughout the programming operation. Otherwise, the programming operation will abort, setting the appropriate Status Register error bit(s). The following sections describe each programming method.
9.6.1
Single-Word Programming
Main array programming is performed by first issuing the Single-Word Program command. This is followed by writing the desired data at the desired array address. The read mode of the addressed partition is automatically changed to Read Status Register mode, which remains in effect until another read-mode command is issued.
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Note:
Issuing the Read Status Register command to another partition switches that partition’s read mode to Read Status Register mode, thereby allowing programming progress to be monitored from that partition’s address. Single-Word Programming is supported in Control mode only. The array address specified must be in the A-half of the programming region. During programming, the Status Register indicates a busy status (SR7 = 0). Upon completion, the Status Register indicates a ready status (SR7 = 1). The Status Register should be checked for any errors, then cleared. The only valid commands during programming are Read Array, Read Device Information, CFI Query, Read Status and Program Suspend. After programming has finished, any valid command can be issued.
Note:
Issuing the Read Array, Read Device Information, or CFI Query command to a partition that is actively programming causes subsequent reads from that partition to output invalid data. Valid data is output only after the program operation has finished. Standby power levels are not realized until the programming operation has finished. Asserting RST# immediately aborts the programming operation, and array contents at the addressed location are indeterminate. The addressed block should be erased, and the data re-programmed.
9.6.2
Buffered Programming
Buffered Programming programs multiple words simultaneously into the flash memory array. Data is first written to a write buffer and then programmed into the flash memory array in buffer-size increments. This can significantly reduce the effective word-write time. Section 6.0, “Flow Charts” on page 41 contains a flow chart of the buffered-programming operation.
Note:
Optimal performance and power consumption is realized only by aligning the start address on 32-word boundaries, e.g., A[4:0] = 00000b. Crossing a 32-word boundary during a Buffered Programming operation can cause the programming time to double. Buffered Programming is supported in both Control mode and Object mode. In Object mode, the region must be programmed only once between erases. However in Control mode, the region may be programmed multiple times.
Caution:
When using the Buffered Program command in Object mode, the start address must be aligned to the 512-word buffer boundary. In Control mode, the programming array address specified must be in the A-half of the programming region. First issue the Read Status command to the desired partition. The read mode of the addressed partition is changed to Read Status Register mode. Poll SR7 to determine write-buffer availability (0 = not available, 1 = available). If the write buffer is not available, re-issue the Read Status command and check SR7; repeat until SR7 = 1. If desired issue a Read Array command to the desired partition to change the read mode of the partition to Array reads. To perform a buffered programming operation, issue the Buffered Program setup command at the desired starting address. Next, issue a word count at the desired starting address. The word count is the total number of words to be written into the write buffer, minus one. This value can range from 0000h (one word) up to a maximum of 01FFh (512 words). Exceeding the allowable range causes the operation to abort.
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Following the word count, subsequent bus-write cycles fill the write buffer with userdata up to the word count. Note: User-data is programmed into the flash array at the address issued when filling the write buffer. The Confirm command (00D0h) is issued after all user-data is written into the write buffer. The read mode of the device/addressed partition is automatically changed to Read Status Register mode. If other than the Confirm command is issued to the device, a command sequence error occurs and the operation aborts. After the Confirm command has been issued, the write-buffer contents are programmed into the flash memory array. The Status Register indicates a busy status (SR7 = 0) during array programming. During array programming, the only valid commands are Read Array, Read Device Information, CFI Query, Read Status, and Program Suspend. After array programming has completed (SR7 = 1), any valid command can be issued. Reading from another partition is allowed while data is being programmed into the flash memory array from the write buffer. Note: Issuing the Read Array, Read Device Information, or CFI Query command to a partition that is actively programming or erasing causes subsequent reads from that partition to output invalid data. Valid data is output only after the program or erase operation has finished. Upon completion of array programming, the Status Register indicates ready (SR7 = 1b). A full Status Register check should be performed to check for any programming errors. Then the Status Register should be cleared using the Clear Status Register command. A subsequent buffered programming operation can be initiated by repeating the buffered programming sequence. Any errors in the Status Register caused by the previous operation must be cleared to prevent them from masking any errors that may occur during the subsequent operation.
9.6.3
Buffered Enhanced Factory Programming (BEFP)
Buffered Enhanced Factory Programming (BEFP) improves programming performance through the use of the write buffer, elevated programming voltage (VPPH), and enhanced programming algorithm. User-data is written into the write buffer, then the buffer contents are automatically written into the flash array in buffer-size increments. BEFP is allowed in both Control Mode and Object Mode. The programming mode selection for the entire flash array block is driven by the specific type of information, such as header or object data. Header/object data is aligned on a 1 KB programming region boundary in the main array block. Internal verification during programming (inherent to MLC technology) and Status Register error checking are used to determine proper completion of the programming operation. This eliminates delays incurred when switching between single-word program and verify operations. BEFP consists of three distinct phases: 1. Setup Phase: VPPH and block-lock checks 2. Program/Verify Phase: buffered programming and verification 3. Exit Phase: block-error check
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Section 6.0, “Flow Charts” on page 41 contains a flow chart of the BEFP operation. Table 40, “BEFP Requirements and Considerations” on page 91 lists specific BEFP requirements and considerations. Note: For BEFP voltage and temperature operating restrictions, see the datasheet. The block erase cycles in Table 40, “BEFP Requirements and Considerations” are recommended for optimal performance. If exceeded some degradation in performance may occur; however, the internal algorithm will still function correctly.
Table 40: BEFP Requirements and Considerations
Temperature (TCASE) must be 25 °C, ± 5 °C BEFP Requirements Voltage on VCC must be within the allowable operating range Voltage on VPP must be within the allowable operating range Block being programmed must be erased and unlocked Block cycling below 100 erase cycles BEFP Considerations Reading from another partition during EFP (RWW) is not allowed BEFP programs within one block at a time BEFP cannot be suspended
9.6.3.1
Setup Phase
Issuing the BEFP Setup and Confirm command sequence starts the BEFP algorithm. The read mode of the addressed partition is automatically changed to Read Status Register mode. The address used when issuing the setup/confirm commands must be buffer-size aligned within the block being programmed -- buffer contents cannot cross block boundaries.
Caution:
The Read Status Register command must not be issued -- it will be interpreted as data to be written to the write buffer. A setup delay (tBEFP/Setup) occurs while the internal algorithm checks VPP and block-lock status. If errors are detected, the appropriate Status Register error bits are set and the operation aborts. The Status Register should be polled for successful BEFP setup, indicated by SR[7,0] = 0 (Device Busy, Buffer Ready for Data).
9.6.3.2
Program/Verify Phase
Data is first written into the write buffer, then programmed into the flash array. During the buffer-fill sequence, the address used must be buffer-size aligned. Use of any other address will cause the operation to abort with a program fail error, and any data previously loaded in the buffer will not be programmed into the array. The buffer-fill data is stored in sequential buffer locations starting at address 00h. A word count equal to the maximum buffer size is used, therefore, the buffer must be completely filled. If the amount of data is less than the maximum buffer size, the remaining buffer locations must be “padded” with FFFFh to completely fill the buffer. Flash array programming starts as soon as the write buffer is full. Data words from the write buffer are programmed into sequential array locations. SR0 = 1 indicates the write buffer is not available while the BEFP algorithm programs the array.
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The Status Register should be polled for SR0 = 0 (Buffer Ready for Data) to determine when the array programming has completed, and the write buffer is again available for loading. The internal address is automatically incremented to enable subsequent array programming to continue from where the previous buffer-fill/array-program sequence ended within the block. This cycle can be repeated to program the entire block. To exit the Program/Verify Phase, write FFFFh to an address outside of the block.
9.6.3.3
Exit Phase
The Status Register should be polled for SR7 = 1 (Device Ready) indicating the BEFP algorithm has finished running, and the device has returned to normal operation. A full error check should be performed to ensure the block was programmed successfully.
9.7
Block Erase Operations
Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation must be performed (see Section 9.6, “Programming Operations). Erasing is performed on a block basis— an entire block is erased each time an erase command sequence is issued. Once a block is fully erased, all addressable locations within that block read as logical ‘ones’ (FFFFh). Only one block-erase operation can occur at a time. A block-erase operation is not permitted during Program Suspend. To perform a block-erase operation, issue the Block Erase command sequence at the desired block address. Table 41 shows the two-cycle Block Erase command sequence.
Table 41: Block-Erase Command Bus Cycles
Command Setup Write Cycle Address Bus Block Erase Device Address Data Bus 0020h Confirm Write Cycle Address Bus Block Address Data Bus 00D0h
Caution:
All block-erase operations require the addressed block to be unlocked, and a valid voltage applied to VPP throughout the block-erase operation. Otherwise, the operation aborts, setting the appropriate Status Register error bit(s). The Erase Confirm command latches the address of the block to be erased. The addressed block is preconditioned (programmed to all zeros), erased, and then verified. The read mode of the addressed partition is automatically changed to Read Status Register mode, and remains in effect until another read-mode command is issued.
Note:
Issuing the Read Status Register command to another partition switches that partition’s read mode to the Read Status Register, thereby allowing block-erase progress to be monitored from that partition’s address. SR0 indicates whether the addressed partition or other partition is erasing. During a block-erase operation, the Status Register indicates a busy status (SR7 = 0). Upon completion, the Status Register indicates a ready status (SR7 = 1). The Status Register should be checked for any errors, and then cleared. The only valid commands during a block erase operation are Read Array, Read Device Information, CFI Query, Read Status and Erase Suspend. After the block-erase operation has completed, any valid command can be issued.
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Note:
Issuing the Read Array command to a partition that is actively erasing a main block causes subsequent reads from that partition to output invalid data. Valid array data is output only after the block-erase operation has finished. Standby power levels are not realized until the block-erase operation has finished. Asserting RST# immediately aborts the block-erase operation, and array contents at the addressed location are indeterminate. The addressed block should be erased, and the data re-programmed.
9.8
Blank Check Operation
Blank Check is used to see if a main-array block is completely erased. A Blank Check operation is performed one block at a time, and cannot be used during Program Suspend or Erase Suspend. To use Blank Check, first issue the Blank Check setup command followed by the confirm command. The read mode of the addressed partition is automatically changed to Read Status Register mode, which remains in effect until another read-mode command is issued.
Table 42: Blank Check Command Bus Cycles
Setup Write Cycle Command Address Bus Blank Check Block Address Data Bus 00BCh Address Bus Block Address Data Bus 00D0h Confirm Write Cycle
During a blank check operation, the Status Register indicates a busy status (SR7 = 0). Upon completion, the Status Register indicates a ready status (SR7 = 1). Note: Issuing the Read Status Register command to another partition switches that partition’s read mode to Read Status Register mode, thereby allowing the blank check operation to be monitored from that partition’s address. The Status Register should be checked for any errors, and then cleared. If the Blank Check operation fails, i.e., the block is not completely erased, then the Status Register will indicate a Blank Check error (SR[7,5] = 1). The only valid command during a Blank Check operation is Read Status. Blank Check cannot be suspended. After the blank check operation has completed, any valid command can be issued.
9.9
Suspend and Resume
Program and erase operations of the main array can be suspended to perform other device operations, and then subsequently resumed. However, OTP Register programming or blank check operations cannot be suspended. To suspend an on-going erase or program operation, issue the Suspend command to any device address; the corresponding partition is not affected. Table 43 shows the Suspend and Resume command bus-cycles.
Note:
Issuing the Suspend command does not change the read mode of the partition. The partition will be in Read Status Register mode from when the erase or program command was first issued, unless the read mode was changed prior to issuing the Suspend command.
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Table 43: Suspend and Resume Command Bus Cycles
Setup Write Cycle Command Address Bus Suspend Resume Device Address Device Address Data Bus 00B0h 00D0h Address Bus --------Data Bus Confirm Write Cycle
The program or erase operation suspends at pre-determined points during the operation after a delay of tSUSP. Suspend is achieved when SR[7,6] = 1 (erasesuspend) or SR[7,2] = 1 (program-suspend). Note: Throughout the Block Erase Suspend or Program Suspend period, the addressed block must remain unlocked and a valid voltage applied to VPP. Otherwise, the erase or program operation will abort, setting the appropriate Status Register error bit(s). Also, WP# must remain unchanged. Asserting RST# aborts suspended block-erase and programming operations -- array contents at the addressed locations are indeterminate. The addressed block should be erased, and the data re-programmed. Not all commands are allowed when the device is suspended. Table 44 shows which device commands are allowed during Program Suspend or Erase Suspend. Table 44: Valid Commands During Suspend
Device Command Read Array Read Status Register Clear Status Register Read Device Information CFI Query Word Program Buffered Program Buffered Enhanced Factory Program Block Erase Program/Erase Suspend Program/Erase Resume Program Suspend Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Allowed Erase Suspend
During Suspend, reading from a block that is being erased or programmed is not allowed. Also, programming to a block that is in erase-suspend state is not allowed, and if attempted, will result in Status Register program error to be set (SR4 = 1). A block-erase under program-suspend is not allowed. However, word-program under erase-suspend is allowed, and can be suspended. This results in a simultaneous erasesuspend/ program-suspend condition, indicated by SR[7,6,2] = 1. To resume a suspended program or erase operation, issue the Resume command to any device address. The read mode of the resumed partition is unchanged; issue the Read Status Register command to return the partition to Read Status mode. The operation continues where it left off, and the respective Status Register suspend bits are cleared.
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When the Resume command is issued during a simultaneous erase-suspend/ programsuspend condition, the programming operation is resumed first. Upon completion of the programming operation, the Status Register should be checked for any errors, and cleared. The resume command must be issued again to complete the erase operation. Upon completion of the erase operation, the Status Register should be checked for any errors, and cleared.
9.10
Simultaneous Operations
The multi-partition architecture of the flash device allows programming or erasing to occur in one partition while reads are performed from another partition. Only status reads are allowed in partitions that are busy programming or erasing.
Note:
When OTP Registercommands are issued to a parameter any partition address, the OTP Registeris mapped onto that partition. Table 45, “Read-While-Program and Read-While-Erase Rules” shows the rules for reading from a partition while simultaneously programming or erasing within another partition.
Table 45: Read-While-Program and Read-While-Erase Rules
Read modes allowed when program/erase busy in partition A Active Operation Main-Array Program Main-Array Erase OTP Register Program Note: Read Status All partitions All partitions All partitions Array Reads All partitions except busy partition A All partitions except busy partition A All partitions except busy partition A Non-Array Reads1 All partitions except busy partition A All partitions except busy partition A Not allowed
OTP Register, Device Information, CFI Query.
9.11
Security
The flash device incorporates features for protecting main-array contents and for implementing system-level security schemes. The following sections describe the available features.
9.11.1
Block Locking
Two methods of block-lock control are available: software and hardware. Software control uses the Block Lock and Block Unlock commands; hardware control uses WP# along with the Block Lock-Down command. Upon power up or exit from reset, all main array blocks are locked, but not locked down. Locked blocks cannot be erased or programmed. Block lock and unlock operations are independent of the voltage level on VPP. Table 46 summarizes the command bus-cycles.
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Table 46: Block Locking Command Bus Cycles
Setup Write Cycle Command Address Bus Lock Block Unlock Block Lock-Down Block Block Address Block Address Block Address Data Bus 0060h 0060h 0060h Address Bus Block Address Block Address Block Address Data Bus 0001h 00D0h 002Fh Confirm Write Cycle
To lock, unlock, or lock-down a block, first issue the setup command to any address within the desired block. The read mode of the addressed partition is automatically changed to Read Status Register mode. Next, issue the desired confirm command to the block’s address. Note that the confirm command determines the operation performed. The Status Register should be checked for any errors, and then cleared. The lock status of a block can be determined by issuing the Read Device Information command, and then reading from + 02h. DQ0 indicates the lock status of the addressed block (0 = unlocked, 1 = locked), and DQ1 indicates the lockdown status of the addressed block (0 = lock-down not issued; 1 = locked-down issued). Section 9.4.3, “Read Device Information” on page 82 summarizes the details of this operation. Blocks cannot be locked or unlocked while being actively programmed or erased. Blocks can be locked or unlocked during erase-suspend, but not during program-suspend. Note: If a block-erase operation is suspended, and then the block is locked or locked down, the lock status of the block will be changed immediately. When resumed, the erase operation will still complete. Block lock-down protection is dependent on WP#. When WP# = VIL , blocks locked down are locked, and cannot be unlocked using the Block Unlock command. When WP# = VIH, block lock-down protection is disabled—locked-down blocks can be individually unlocked using the Block Unlock command. Subsequently, when WP# = VIL, previously locked-down blocks are once again locked and locked-down, including locked-down blocks that may have been unlocked while WP# was de-asserted. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to the locked-down state, a Lock-Down command must be issued prior to asserting WP#. Issuing the Block Lock-Down command to an unlocked block does not lock the block. However, asserting WP# after issuing the Block Lock-Down command locks (and locks down) the block. Lock-down for all blocks is cleared upon power-up or exit from reset. Figure 49 summarizes block-locking operations.
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Figure 49: Block Locking Operations
Locked [X,0,1]
Locked Down2 [0,1,1]
Hardware Locked2 [0,1,1]
WP# = V IL
Power Up -orExit from Reset
WP# = VIH
Unlocked [X,0,0] Software Locked [1,1,1] Unlocked [1,1,0]
Software Control (Lock, Unlock, Lock-Down Command) Hardware Control (WP#)
Notes: 1. [n,n,n] denotes logical state of WP#, DQ1,and DQ0, respectively; X = Don’t Care. 2. [0,1,1] states should be tracked by system software to differentiate between the Hardware-Locked state and the LockDown state.
9.11.2
One-Time Programmable (OTP) Registers
The device contains seventeen 128-bit One-Time Programmable (OTP) Registers, and twoa 16-bit OTP Lock Registers, as shown in Figure 50, “2-Kbit OTP Registers” on page 98. The OTP Lock Register 0 is used for locking the OTP Register 0, and OTP Lock Register 1 is used for locking OTP Registers 1 through 16. The OTP Register 0 consists of two 64-bit segments: a lower segment that is preprogrammed with a unique 64-bit value and locked at the factory; and an upper segment that contains all “ones” and is user-programmable. OTP Registers 1 through 16 contain all “ones” and are user-programmable.
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Figure 50: 2-Kbit OTP Registers
0x109
128-bit OTP Register 16
(User-Programmable) 0x102
0x91
128-bit OTP Register 1
(User-Programmable) 0x8A 0x89
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTP Lock Register 1
0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-Bit OTP Register 0
64-bit Segment (Factory-Programmed)
OTP Lock Register 0
Each register contains OTP bits that can only be programmed from “one” to “zero” register bits cannot be erased from “zero” back to “one”. This feature makes the OTP registers particularly useful for implementing system-level security schemes, for permanently storing data, or for storing fixed system parameters. OTP Lock Register bits “lock out” subsequent programming of the corresponding OTP register. Each OTP Register can be locked by programming its corresponding lock bit to zero. As long as an OTP register remains unlocked (that is, its lock bit = 1), any of its remaining “one” bits can be programmed to “zero”. Caution: Once an OTP Register is locked, it cannot be unlocked. Attempts to program a locked OTP Register will fail with error bits set. To program any OTP bits, first issue the Program OTP Register setup command at any device address. Next, write the desired OTP Register data at the desired OTP Register address. OTP Register and OTP Lock Register programming is performed 16 bits at a time; only “zeros” within the data word affect any change to the OTP register bits.
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Table 47: Program OTP Register Command Bus Cycles
Setup Write Cycle Command Address Bus Program OTP Register Device Address Data Bus 00C0h Address Bus OTP Register Address Data Bus Register Data Confirm Write Cycle
Attempting to program an OTP register outside of the OTP register space causes a program error (SR4 = 1). Attempting to program a locked OTP Register causes a program error and a lock error (SR4 = 1, SR1 = 1). To read from any of the OTP registers, first issue the Read Device Information command. Then read from the desired OTP Register address offset. For additional details, refer to Section 9.4.3, “Read Device Information” on page 82.
9.11.3
Global Main-Array Protection
Global main-array protection can be implemented by controlling VPP. When programming or erasing main-array blocks, VPP must be equal to, or greater than VPPL (min). When VPP is below VPPLK, program or erase operations are inhibited, thus providing absolute protection of the main array. Various methods exist for controlling VPP, ranging from simple logic control to off-board voltage control. Figure 51 shows example VPP supply connections that can be used to support program/erase operations and main-array protection.
Figure 51: Example VPP Supply Connections
VCC VPPH
VCC VPP
VCC VPPL PROT#
VCC VPP
≤ 10ΚΩ
• •
Factory Programming: VPP = VPPH Program/Erase Protection: VPP ≤ VPPLK
• •
Program/Erase Enable: PROT# = VIH Program/Erase Protection: PROT# = VIL
VCC VPPL
VCC VPP VPPH
VCC VPPL
VCC VPP
• •
Low-Voltage Programming: VPP = VPPL - orFactory Programming: VPP = VPPH
• •
Low-Voltage Programming: VPP = VCC Program/Erase Protection: None
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10.0
Device Command Codes
Table 48: Command Bus Operations
Command Program Read Configuration Register Registers Program Enhanced Configuration Register Program OTP Register Read Array Read Status Register Read Modes Clear Status Register Read Device Information Code (Setup/Confirm) 0060h/0003h Description Issuing this command sequence programs the Read Configuration Register. The RCR value is placed on the address bus. Issuing this command sequence programs the Enhanced Configuration Register. The ECR value is placed on the address bus. Issuing this command programs the Protection Registers or the Lock Registers associated with them. Issuing this command places the addressed partition in Read Array mode. Subsequent reads outputs array data. Issuing this command places the addressed partition in Read Status mode. Subsequent reads outputs Status Register data. Issuing this command clears all error bits in the Status Register. Issuing this command places the addressed partition in Read Device Information mode. Subsequent reads from specified address offsets outputs unique device information. Issuing this command places the addressed partition in CFI Query mode. Subsequent reads from specified address offsets outputs CFI data. This command prepares the device for programming a single word into the flash array. On the next bus write cycle, the address and data are latched and written to the flash array. The addressed partition automatically switches to Read Status Register mode. This command sequence initiates and executes a buffered programming operation. Additional bus write/read cycles are required between the setup and confirm commands to properly perform this operation. The addressed partition automatically switches to Read Status Register mode. This command sequence initiates and executes a BEFP operation. Additional bus write/read cycles are required after the confirm command to properly perform the operation. The addressed partition automatically switches to Read Status Register mode. Issuing this command sequence erases the addressed block. The addressed partition automatically switches to Read Status mode. Issuing this command to any device address initiates a suspend of a program or block-erase operation already in progress. SR6 = 1 indicates erase suspend, and SR2 = 1 indicates program suspend. Issuing this command to any device address resumes a suspended program or block-erase operation. A program suspend nested within an erase suspend is resumed first. This command sequence initiates the blank check operation on a block. Issuing this command sequence sets the lock bit of the addressed block. Issuing this command sequence clears the lock bit of the addressed block. Issuing this command sequence locks down the addressed block.
0060h/0004h
00C0h 00FFh 0070h 0050h 0090h
CFI Query
0098h
Word Program
0041h
Buffered Program Program/Erase Operations
00E9h/00D0h
Buffered Enhanced Factory Program
0080h/00D0h
Block Erase
0020h/00D0h
Program/Erase Suspend
00B0h
Program/Erase Resume
00D0h
Blank Check Lock Block Security Unlock Block Lock Down Block
00BCh/00D0h 0060h/0001h 0060h/00D0h 0060h/002Fh
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11.0
Flow Charts
Figure 52: Word Program for Main Array Flowchart
WORD PROGRAM PROCEDURE
Start Bus Command Operation Write
( Setup )
Comments Data = 0x41 Addr = Location to program Data = Data to program Addr = Location to program Main or Parameter status register data
Write 0x41, Word Address
Program Setup Data
Write Write Data, Word Address
(Confirm)
Read Read Status Register
No
None
Program Suspend Loop
Idle
None
Check SR[7] 1 = WSM Ready 0 = WSM Busy
SR[7] =
1
0
Suspend?
Yes
Repeat for subsequent Word Program operations. Full Status Register check can be done after each program or , after a sequence of program operations. Write 0xFF after the last operation to set to the Read Array state.
Full Status Check (if desired)
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Idle SR[4] =
1 1 0
Comments Check SR[4]: 1 = Data Program Error Check SR[1]: 1 = Block locked; operation aborted Check SR[3]: 1 = VPP Error Check SR[8] AND SR[9]:
None
Program Success Idle Device Protect Error None
SR[1] =
0
Idle
None
SR[3] =
0
1
Vpp Range Error Idle None
0 0=Region program successful . 1 0= Attempted write with object data to C ontrol Mode region . 0 1= Attempted rewrite to Object Mode region . 1 1=Attempted write using illegal command. SR[3] MUST be cleared before the Write State Machine will allow further program attempts. If an error is detected clear the Status Register before , continuing operations - only the Clear Staus Register command clears the Status Register error bits .
SR[8] or SR[9] =
0
1
See Table on the right for explantion
Program Fail
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 53: Program Suspend/Resume Flowchart
PR OG R AM SUSPEN D / RESUM E PRO CEDUR E
S ta rt
P ro g ra m S uspend
W rite B 0 h A n y A d d re s s
R ead S ta tu s
Bus Com m and O p e ra tio n W rite
C o m m e n ts
P ro g ra m D a ta = B 0 h S u s p e n d A d d r = B lo c k to s u s p e n d (B A ) R ead S ta tu s D a ta = S R ( 1 ) A d d r = S a m e p a rtitio n S ta tu s re g is te r d a ta A d d r = S u s p e n d e d b lo c k (B A ) C h e c k S R .7 1 = W S M re a d y 0 = W S M busy C h e c k S R .2 1 = P ro g ra m s u s p e n d e d 0 = P ro g ra m c o m p le te d R ead A rra y D a ta = F F h A d d r = A n y a d d re s s w ith in th e s u s p e n d e d p a rtitio n R e a d a rra y d a ta fro m b lo c k o th e r th a n th e o n e b e in g p ro g ra m m e d P ro g ra m R esum e D a ta = D 0 h A d d r = S u s p e n d e d b lo c k (B A )
W rite S R ( 1 ) S a m e P a rtitio n R e a d S ta tu s R e g is te r
W rite
R ead
S R .7 =
1
0
S ta n d b y
S R .2 =
R ead 1 A rra y
0
P ro g ra m C o m p le te d
S ta n d b y
W rite
W rite F F h S u s p P a rtitio n R ead R e a d A rra y D a ta
W rite
No
D one R e a d in g
P ro g ra m Yes R esum e
If th e s u s p e n d e d p a rtitio n w a s p la c e d in R e a d A r ra y m o d e : W rite
R ead A rra y
R ead S ta tu s
R e tu rn p a rtitio n to S ta tu s m o d e : D a ta = S R ( 1 ) A d d r = S a m e p a rtitio n
W rite D 0 h A n y A d d re s s P ro g ra m R esum ed
R ead S ta tu s
W rite F F h P g m 'd P a rtitio n R e a d A rra y D a ta
W rite 7 0 h S a m e P a rtitio n
P G M _ S U S .W M F
Datasheet 102
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 54: Buffered Program Flowchart
Buffer Programming Procedure
Bus Operation Read (Note 1) Issue Read Status Register Command at Partition Address
No
Command None
Comments SR[7] = Valid Addr = Block Address Check SR[7]: 1 = Write Buffer available 0 = No Write Buffer available Data = 0xFF Addr = Block Address Data = 0xE9 Addr = Block Address Data = N = Word Count - 1 (N = 0 corresponds to count = 1) Addr = Buffer Address Data = Write Buffer Data Addr = Word Address Data = Write Buffer Data Addr = Word Address Data = 0xD0 Addr = Block Address Status register Data Addr = Block Address Check SR[7]: 1 = WSM Ready 0 = WSM Busy
Idle Write (Note 2)
None
Read Array Buffer Prog. Setup None
Flash Ready? SR[7] = 1 = Yes
0 = No
Timeout?
Write (Note 3) Write (Notes 4,5) Write (Notes 6, 7) Write (Notes 6, 7) Write (Note 8) Read (Note 9) Standby
Yes Timeout error
No write commands are allowed during this period. Current and other partitions of the device can be read by addressing the location and driving OE# low.
Issue Read Array Command at Partition 1 = Yes Address Set Timeout or Loop Counter
None None Buffer Prog. Conf. None
Issue Buffer Prog. Cmd. 0xE9, Block Address Write Word Count-1, Buffer Address Buffer Program Data , Word Address
None
X=X+1
X= 0
Write Buffer Data, Word Address No No Abort Buffer Program? Yes
X = N?
Yes Write Confirm 0xD0 and Block Address
Write to another Block Address
Only other partitions of the device can be read
Buffer Program Aborted
NOTES: 1. The device outputs the Status Register when read. 2. The device outputs the array data when read . 3. Buffer Programming is available in the main array only. This algorithm may be used for MLC or PSBC programming Upon . issuing 0xE9 the partition state does not changed. 4. Word count value on D[8:0] is loaded into the word count register. Count ranges for this device are N = 0x000 to 0x1FF. 5. Buffer address on A[MAX:9] specifies a single 512-word buffer-size array region. This is latched and held constant during the entire operation. 6. The word address within the buffer specified by A [8:0], is , provided. Upper address bits are ignored. 7. The device aborts the Buffer Program command if the current address is outside the original block address . 8. Upon issuing 0xD0 the partition is placed in Status Read mode. If block address changes, Buffer Program will abort. 9. The Status Register indicates an improper command sequence if the Buffer Program command is aborted use the ; Clear Status Register command to clear error bits . Full status check can be done after all erase and write sequences complete. For a detailed flowchart, please refer to ‘Full Status Check Procedure’ flowchart under ‘Word Program for Main Array’ flowchart.
Commands may be issued to the device.
Read Status Register No SR[7] =? 1 Full Status Check if Desired 0 Suspend Program? Yes
Suspend Program Loop
Write 0xFF after the last operation to place the partition in the Read Array state.
Program Complete
. .
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 55: Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Start
Program & Verify Phase
Data Stream Ready
Exit Phase
Read Status Reg .
VPP applied , Block unlocked
Initialize Count : X= 0
No (SR [7]=0)
BEFP Exited? Yes (SR [7]=1)
Write 0x80 @ 1 ST W ord Address
Write Data @ 1 Word Address
ST
Full Status Check Procedure
Write 0xD0 @ 1ST W ord Address
Increment Count : X = X+1
Program Complete
BEFP setup delay
N
X = 512? Y
Read Status Reg . Read Status Reg . No (SR[0]=1) Program Done ? Yes (SR[0]=0) N Last Data? Y Write 0xFFFF, Address Not within Current Block
BEFP Setup Done ?
Yes (SR[7]=0)
No (SR[7]=1) Check V PP , Lock Errors (SR[3,1])
Exit
BEFP Setup Bus State Write Write (Note 2) Write Read Operation Unlock Block BEFP Setup BEFP Confirm Status Register BEFP Setup Done ? Error Condition Check Comments VPPH applied to VPP Data = 0x80 @ 1 Address
ST
BEFP Program & Verify Bus State Operation Read W ord Standby Status Register Data Stream Ready ? Initialize Count Load Buffer Increment Count Buffer Full? Status Register Program Done? Last Data? Comments Data = Status Register Data Address = 1ST W ord Addr . Check SR [ 0]: 0 = Ready for Data 1 = Not Ready for Data X=0 Data = Data to Program Address = 1ST W ord Addr . X = X+1 X = 512? Yes = Read SR [0] No = Load Next Data Word Data = Status Reg . data Address = 1ST W ord Addr . Check SR [ 0]: 0 = Program Done 1 = Program in Progress No = Fill buffer again Yes = Exit Bus State Read
BEFP Exit Operation Status Register Check Exit Status Comments Data = Status Reg . Data Address = 1ST Word Addr Check SR [7]: 0 = Exit Not Completed 1 = Exit Completed
Standby
D ata = 0xD0 @ 1ST Word Address Data = Status Reg . Data Address = 1ST W ord Addr Check SR [7]: 0 = BEFP Ready 1 = BEFP Not Ready If SR[ 7] is set , check: SR[3] set = VPP Error SR[1] set = Locked Block Standby Write (Note 3) Standby
Repeat for subsequent blocks ; After BEFP exit , a full Status Register check can determine if any program error occurred ; See full Status Register check procedure in the Word Program flowchart . Write 0xFF to enter Read Array state .
Standby
Standby
Standby
Read
Standby
Standby
Write
Exit Prog & Data = 0xFFFF @ address not in Verify Phase current block
NOTES: 1. BEFP is available in the main array only . 2. First-word address to be programmed within the target block must be aligned on a write -buffer boundary . 3. Write-buffer contents are programmed sequentially to the flash array starting at the first word address ; WSM internally increments addressing .
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 56: Block Erase for Main Array Flowchart
BLOCK ERASE PROCEDURE
Start Bus Command Comments Operation Block Data = 0x20 Erase Write Addr = Block to be erased (BA) Setup Write Write 0xD0, (Erase Confirm ) Block Address Read Read Status (2) Register
No
Write 0x20 Block Address
( Block Erase)
Erase Confirm None
Data = 0xD0 Addr = Block to be erased (BA) Status Register data
Suspend Erase Loop
Idle
None
Check SR[7]: 1 = WSM ready 0 = WSM busy
SR[7] =
1
0
Suspend Erase
Yes
Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode .
Full Erase Status Check (if desired)
Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Idle SR[4,5] =
0 1,1
Comments Check SR[4,5]: Both 1 = Command Sequence Error Check SR[5]: 1 = Block Erase Error Check SR[1]: 1 = Attempted erase of locked block ; erase aborted. Check SR[3]: 1 = VPP R ange Error
None None
Command Sequence Error Idle
SR[5] =
1
0
Block Erase Success
Idle
None
SR[1] =
0
1
Block Locked Error VPP R ange Error
Idle
None
SR[3] =
0
1
SR[1,3] must be cleared before the Write State Machine will allow further erase attempts. Only the Clear Status Register command clears SR 3, 4, 5]. [1, If an error is detected clear the Status register before , attempting an erase retry or other error recovery.
Erase Fail
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 57: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus Command Operation
(Read Status)
Comments Data = 0x70 Addr = Any partition address Data = 0xB0 Addr = Same partition address as above Status Register data. Addr = Same partition Check SR[7]: 1 = WSM ready 0 = WSM busy Check SR[6]: 1 = Erase suspended 0 = Erase completed
Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register
Write
Read Status Erase Suspend None
(Erase Suspend)
Write
Read
Idle SR[7] =
1 0 0
None
Idle Erase Completed Write Read or Write Write
None
SR[6] =
1
Read Array Data = 0xFF or 0x40 Addr = Any address within the or Program suspended partition None Read array or program data from/to block other than the one being erased
Read
Read or Program?
No
Program
Read Array Data
Program Loop
Program Data = 0xD0 Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Read Status Register Return partition to Status mode: Data = 0x70 Addr = Same partition
Done
(Erase Resume)
Write 0xD0, Any Address Erase Resumed Write 0x70, Same Partition
Write
Write 0xFF, (Read Array) Erased Partition Read Array Data
(Read Status)
Datasheet 106
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 58: Main Array Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Bus Command Operation
(Lock Setup)
Comments Data = 0x60 Addr = Block to lock/unlock/lock-down
Write 0x60, Block Address
Write
Lock Setup
Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address
Write
Lock, Data = 0x01 (Block Lock) Unlock, or 0xD0 (Block Unlock) Lock-Down 0x2F (Lock-Down Block) Confirm Addr = Block to lock/unlock/lock-down
Write 0x90
(Read Device ID)
Write Read Data = 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data (Optional) Status Addr = Block address + offset 2
Optional
Read Block Lock Status
Locking Change?
Yes
No
Idle
None
Confirm locking change on D[1,0].
Write
Read Array
Data = 0xFF Addr = Block address
Write 0xFF (Read Main Array) Partition Address Lock Change Complete
d
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 59: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start Bus Command Operation Write
( Program Setup )
Comments
Write 0xC0, PR Address
Program Data = 0xC0 PR Setup Addr = First Location to Program Protection Data = Data to Program Program Addr = Location to Program None Status Register Data .
Write Write PR Address & Data
(Confirm Data)
Read
Read Status Register
Idle
None
Check SR[7]: 1 = WSM Ready 0 = WSM Busy
SR[7] =
1
0
Program Protection Register operation addresses must be within the Protection Register address space Addresses . outside this space will return an error . Repeat for subsequent programming operations.
Full Status Check (if desired)
Full Status Register check can be done after each program or , after a sequence of program operations. Write 0xFF after the last operation to set Read Array state .
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data Bus Command Operation Idle SR[4] =
1 1 0
Comments Check SR[4]: 1 =Programming Error Check SR[1]: 1 = Block locked; operation aborted Check SR[3]: 1 =VPP R ange Error
None
Protection Register Program Pass Idle None
SR[1] =
0
Register Locked; Program Aborted
Idle
None
SR[3] must be cleared before the Write State Machine will allow further program attempts.
1
SR[3] =
0
VPP R ange Error
Only the Clear Staus Register command clears SR , 3, 4]. [1 If an error is detected clear the Status register before , attempting a program retry or other error recovery.
Protection Register Program Fail
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 60: Blank Check Operation Flowchart
BLANK CHECK PROCEDURE
Start Bus Command Operation Blank Write Check Setup Blank Write Check Confirm Read Read Status Register
No
Comments Data = 0xBC Addr = Block to be read (BA) Data = 0xD0 Addr = Block to be read (BA) Status Register data. Check SR[7]: 1 = WSM ready 0 = WSM busy
Write 0xBC, Block Address Write 0xD0, Block Address
None
Idle
None
SR[7] =
0
0
Repeat for subsequent block Blank Check. Full Status register check should be read after Blank Check has been performed on each block.
1
Full Blank Check Status Read
Blank Check
FULL BLANK CHECK STATUS CHECK PROCEDURE
Read Status Register Command Sequence Error
Bus Command Operation Idle None None
Comments Check SR[4,5]: Both 1 = Command Sequence Error Check SR[5]: 1 = Blank Check Error
SR[4,5] =
0
1,1
Idle
1
SR[5] =
0
Blank Check Error
SR[1,3] must be cleared before the Write State Machine will allow Blank Check to be performed. Only the Clear Status Register command clears SR[1, 3, 4, 5]. If an error is detected, clear the Status register before attempting a Blank Check retry or other error recovery.
Blank Check Successful
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Numonyx™ StrataFlash® Cellular Memory (M18)
12.0
Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. It describes the database structure containing the data returned by a read operation after issuing the CFI Query command. System software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device.
12.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (A/DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (A/DQ7-0) and 00h in the high byte (A/DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of wordwide devices is always “00h,” the leading “00” has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 49: Summary of Query Structure Output as a Function of Device and Mode
Device 00010: 00011: Hex Offset 51 52 Hex Code “Q” “R” ASCII
Device Addresses
Table 50: Example of Query Structure Output of x16 Devices (Sheet 1 of 2)
Word Addressing Offset AX - A0 00010h 00011h 00012h 00013h 00014h 0051 0052 0059 P_IDLO P_IDHI Hex Code A15 - A0 “Q” “R” “Y” PrVendor ID# Value Offset AX - A0 00010h 00011h 00012h 00013h 00014h 0051 0052 0059 P_IDLO P_IDLO Byte Addressing Hex Code A7 - A0 “Q” “R” “Y” PrVendor ID# Value
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 50: Example of Query Structure Output of x16 Devices (Sheet 2 of 2)
Word Addressing Offset AX - A0 00015h 00016h 00017h 00018h PLO PHI A_IDLO A_IDHI Hex Code A15 - A0 PrVendor TblAdr AltVendor ID# Value Offset AX - A0 00015h 00016h 00017h 00018h P_IDHI Byte Addressing Hex Code A7 - A0 ID# Value
12.2
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR[1]) allows system software to determine the success of the last block erase operation. BSR[1] can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. Only issuing another operation to the block resets this bit. The Block Status Register is accessed from word address 02h within each block.
Table 51: Block Status Register
Offset (BA + 2)h (BA + 2)h Length 1 1 Description Block Lock Status Register BSR.0 Block Lock Status: 0 = Unlocked 1 = Locked BSR.1 Block Lock Down Status: 0 = Not Locked Down 1 = Locked Down BSR.2-3, 6-7: Reserved for future use Address BA + 2 BA + 2 Value -00 or -01 (bit 0): 0 or 1
(BA + 2)h (BA + 2)h Note:
1 1
BA + 2 BA + 2
(bit 0): 0 or 1 (bit 0): 0 or 1
BA = The beginning of a Block Address; that is, 020000h is the beginning location in word mode of the 256-KB block 1.
12.3
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 52: CFI Identification (Sheet 1 of 2)
Offset Length Description Address 10 10h 3 Query unique ASCII string “QRY” 11 12 Hex Code --51 --52 --59 Value “Q” “R” “Y”
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 52: CFI Identification (Sheet 2 of 2)
Offset 13h Length 2 Description Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms. Extended Query Table primary algorithm address. Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists. Secondary algorithm Extended Query Table address. 0000h means none exists. Address 13 14 15 16 17 18 19 1A Hex Code --00 --02 --0A --01 --00 --00 --00 --00 Value
15h
2
17h
2
19h
2
Table 53: System Interface Information (Sheet 1 of 2)
Offset Length Description VCC logic supply minimum program/erase voltage. bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage. bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage. bits 0-3 BCD 100 mV bits 4-7 hex volts VPP [programming] supply maximum program/erase voltage. bits 0-3 BCD 100 mV bits 4-7 hex volts “n” such that typical single word program timeout = 2n µs. Address Hex Code Value
1Bh
1
1B
--17
1.7 V
1Ch
1
1C
--20
2.0 V
1Dh
1
1D
--85
8.5 V
1Eh
1
1E
--95
9.5 V
1Fh
1
1F
--06 --0B (256, 512 Mbit - 90 nm; 1024 Mbit - 65 nm) --0A (128. 256, 512 Mbit 65 nm) --0A --00
64 µs 2048 µs (256, 512 Mbit 90 nm; 1024 Mbit - 65 nm) 1024 µs (128. 256, 512 Mbit - 65 nm) 1s NA
20h
1
“n” such that typical full buffer write timeout = 2n µs.
20
21h 22h
1 1
“n” such that typical block erase timeout = 2n ms. “n” such that typical full chip erase timeout = 2 n ms. “n” such that maximum word program timeout = 2n times typical.
21 22
23h
1
23
--02
256 µs
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Table 53: System Interface Information (Sheet 2 of 2)
Offset Length Description Address Hex Code --02 (256, 512 Mbit - 90 nm; 128, 256, 512 Mbit - 65 nm) --01 (1024 Mbit - 65 nm) Value 8192 µs (256, 512 Mbit 90 nm; 128, 256, 512 Mbit - 65 nm) 4096 µs (1024 Mbit - 65 nm) 4s NA
24h
1
“n” such that maximum buffer write timeout = 2n times typical.
24
25h 26h
1 1
“n” such that maximum block erase timeout = 2n times typical. “n” such that maximum chip erase timeout = 2n times typical.
25 26
--02 --00
12.4
Device Geometry Definition
Table 54: Device Geometry Definition
Offset 27h Length 1 Description n such that device size in bytes = 2 n. Address 27: Hex Code Value
Flash device interface code assignment: n such that n + 1 specifies the bit field that represents the flash device width capabilities as described here: 7 28h 2 — 15 — 2Ah 2 6 — 14 — 5 — 13 — 4 — 12 — 3 x64 11 — 2 x32 10 — 1 x16 9 — 0 x8 8 —
Table 55, “Device Geometry Definition: Addr, Hex Code, Value” on page 114
28: --01 x16 29: 2A: 2B: --00 --0A --00 1024
n such that maximum number of bytes in write buffer = 2n. Number of erase block regions (x) within the device: 1) x = 0 means no erase blocking; the device erases in bulk. 2) x specifies the number of device regions with one or more contiguous, same-size erase blocks. 3) Symmetrically blocked partitions have one blocking region. Erase block region 1 information: bits 0 - 15 = y, y + 1 = number of identical-size erase blocks. bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.
2Ch
1
2C:
2Dh
4
2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
Table 55, “Device Geometry Definition: Addr, Hex Code, Value” on page 114
31h
4
Reserved for future erase block region information.
35h
4
Reserved for future erase block region information.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 55: Device Geometry Definition: Addr, Hex Code, Value
128 Mbit Address B 27 28 29 2A 2B 2C 2D 2E 2F 30 18 01 00 0A 00 01 3F 00 00 04 T — — — — — — — — — — B 19 01 00 0A 00 01 7F 00 00 04 T — — — — — — — — — — B 1A 01 00 0A 00 01 FF 00 00 04 T — — — — — — — — — — B 1B 01 00 0A 00 01 FF 01 00 04 T — — — — — — — — — — 256 Mbit 512 Mbit 1 Gbit
12.5
Numonyx-Specific Extended Query Table
Table 56: Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset P = 10Ah (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h 1 1 Major version number, ASCII Minor version number, ASCII 3 Primary extended query table. Unique ASCII string PRI Length Description (Optional flash features and commands Address 10A: 10B: 10C: 10D: 10E: Hex Code --50 --52 --49 --31 --34 Value P R I 1 4
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 56: Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset P = 10Ah Length Description (Optional flash features and commands Optional feature and command support: (1 = yes; 0 = no) Bits 10 - 31 are reserved; undefined bits are 0. If the value in bit 31 is 1, an additional 31 bit field of optional features follows the bit 30 field. Bit 0: Chip erase supported. Bit 1: Suspend erase supported. (P+5)h (P+6)h (P+7)h (P+8)h Bit 2: Suspend program supported. 4 Bit 3: Legacy lock/unlock supported. Bit 4: Queued erase supported. Bit 5: Instant individual block locking supported. Bit 6: OTP bits supported. Bit 7: Page mode read supported. Bit 8: Synchronous read supported. Bit 9: Simultaneous operations supported. Bit 30: CFI links to follow. Bit 31: Another Optional Features field to follow. Supported functions after Suspend: Read Array, Status, Query. Other supported options include: Bits 1 - 7: Reserved; undefined bits are 0. Bit 0: Program supported after Erase Suspend. 2 (P+A)h (P+B)h 2 2 Block Lock Status Register mask: Bits 2 - 3 and 6 - 15 are reserved; undefined bits are 0. Bit 0: Block Lock Bit Status register active. Bit 1: Block Lock Down bit Status active. Vcc logic supply highest performance program/erase voltage: Bits 0 - 3: BCD value in 100 mV Bits 4 - 7: BCD value in volts VPP optimum program/erase supply voltage: Bits 0 - 3: BCD value in 100 mV Bits 4 - 7: Hex value in volts 114: 115: 113: Address 10F: 110: 111: 112: Hex Code --E6 (Non-Mux) --66 (A/D Mux) --07 --00 --00 Bit 0 = 0 Bit 1 = 1 Bit 2 = 1 Bit 3 = 0 Bit 4 = 0 Bit 5 = 1 Bit 6 = 1 Bit 7 = 0 Bit 8 = 1 Bit 9 = 1 Bit 30 = 0 Bit 31 = 0 --01 Bit 0 = 1 --33 --00 Bit 0 = 1 Bit 1 = 1 Yes Yes Yes No Yes Yes No No Yes Yes No: A/D Mux Yes: Non-Mux Yes Yes No No Value
(P+9)h
1
(P+C)h
1
116:
--18
1.8 V
(P+D)h
1
117:
--90
9.0 V
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 57: One Time Programmable (OTP) Register Information
Offset P = 10Ah (P+E)h Length 1 Description Number of OTP register fields in JEDEC ID space. 00h indicates that 256 OTP fields are available. OTP Field 1: OTP Description: This field describes user available OTP register bytes. Some are preprogrammed with device-unique serial numbers. Others are user programmable. Bits 0 - 15 point to the OTP register Lock byte, the register’s first byte. The following bytes are factory preprogrammed and userprogrammable: Bits 0 - 7 = Lock/bytes JEDEC plane physical low address. Bits 8 - 15 = Lock/bytes JEDEC plane physical high address. Bits 16 - 23 = n w here 2 equals factory preprogrammed bytes. Bits 24 - 31 = n w here 2n equals user programmable bytes. OTP Field 2: OTP Description Bits 0 - 31 point to the OTP register physical Lock word address in the JEDEC plane. (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h The following bytes are factory or user programmable: Bits 32 - 39 = n where n equals factory programmed groups (low byte). Bits 40 - 47 = n w here n equals factory programmed groups (high byte). Bits 48 - 55 = n w here 2n equals factory programmed bytes/ groups. Bits 56 - 63 = n w here n equals user programmed groups (low byte). Bits 64 - 71 = n w here n equals user programmed groups (high byte). Bits 72 - 79 = n w here n equals user programmable bytes/ groups. 11D: 11E: 11F: 120: --89 --00 --00 --00 89h 00h 00h 00h
n
Address 118:
Hex Code --02
Value 2
(P+F)h (P+10)h (P+11)h (P+12)h
4
119: 11A: 11B: 11C:
--80 --00 --03 --03
80h 00h 8 byte 8 byte
10
121: 122: 123:
--00 --00 --00
0 0 0
124: 125: 126:
--10 --00 --04
16 0 16
Datasheet 116
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 58: Burst Read Information
Offset P = 10Ah Length Description (Optional flash features and commands) Page Mode Read capability: Bits 0 - 7 = n where 2n hex value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1: Bits 3 - 7 = Reserved. Bits 0 - 2 = n where 2n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This fields’s 3-bit value can be written directly to the Read Configuration Register bits 0 - 2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2. Synchronous mode read capability configuration 3. Address Hex Code Value
(P+1D)h
1
127:
--05 (Non Mux) --00 (A/D Mux
32-byte (Non Mux) 0 (AD Mux)
(P+1E)h
1
128:
--03
3
(P+1F)h
1
129:
--02
8
(P+20)h (P+21)h
1 1
12A: 12B:
--03 --07
16 Cont
Table 59: Partition and Erase Block Information—Region 1 (Sheet 1 of 2)
Offset P = 10Ah Bottom Top Number of device hardware partition regions with the device: x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. Address Description (Optional flash features and commands) Length Bottom Top
(P+22)h
(P+22)h
1
12C:
12C:
Partition Region 1 Information (P+23)h (P+24)h (P+25)h (P+26)h (P+27)h (P+23)h (P+24)h (P+25)h (P+26)h (P+27)h Data size of this Partition Region information field: (number of addressable locations, including this field. Number of identical partitions within the partition region. Number of Program or Erase operations allowed in a partition: Bits 0 - 3 = Number of simultaneous Program operations. Bits 4 - 7 = Number of simultaneous Erase operations. Number of Program or Erase operations allowed in other partitions while a partition in this region is in Program mode: Bits 0 - 3 = Number of simultaneous Program operations. Bits 4 - 7 = Number of simultaneous Erase operations. Number of Program or Erase operations allowed in other partitions while a partition in this region is in Erase mode: Bits 0 - 3 = Number of simultaneous Program operations. Bits 4 - 7 = Number of simultaneous Erase operations. 2 12D: 12E: 12F: 130: 131: 12D: 12E: 12F: 130: 131:
1
1
(P+28)h
(P+28)h
1
132:
132:
(P+29)h
(P+29)h
1
133:
133:
April 2008 309823-10
Datasheet 117
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 59: Partition and Erase Block Information—Region 1 (Sheet 2 of 2)
Offset P = 10Ah Bottom Top Types of erase block regions in this partition region: x = 0: No erase blocking; the partition region erases in bulk. x = Number of erase block regions with contiguous, same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks) x (Type 1 block sizes) + (Type 2 blocks) x (Type 2 block sizes) +...+ (Type n blocks) x (Type n block sizes). Partition region 1 erase block type 1 information: Bits 0 - 15 = y, y + 1: Number of identical-sized erase blocks in a partition. Bits 16 - 30 = z, where region erase block(s) size is z x 256 bytes. Partition 1 (Erase Block Type 1): Block erase cycles x 1000 Partition 1 (Erase Block Type 1) bits per cell; internal EDAC: Bits 0 - 3 = bits per cell in erase region Bit 4 = internal EDAC used (1=yes, 0=no) Bit 5 - 7 = reserved for future use Partition 1 (Erase Block Type 1) page mode and synchronous mode capabilities: Bits 0 = page mode host reads permitted (1=yes, 0=no) Bit 1 = synchronous host reads permitted (1=yes, 0=no) Bit 2 = synchronous host writes permitted (1=yes, 0=no) Bit 3 - 7 = reserved for future use Partition 1 (Erase Block Type 1) programming region information: Bits 0 - 7 = x, 2x: programming region aligned size (bytes) Bit 8 - 14 = reserved for future use Bit 15 = legacy flash operation; ignore 0:7 Bit 16 - 23 = y: control mode valid size (bytes) Bit 24 - 31 = reserved for future use Bit 32 - 39 = z: control mode invalid size (bytes) Bit 40 - 46 = reserved for future use Bit 47 = legacy flash operation (ignore 23:16 and 39:32) Address Description (Optional flash features and commands) Length Bottom Top
(P+2A)h
(P+2A)h
1
134:
134:
(P+2B)h (P+2C)h (P+2D)h (P+2E)h (P+2F)h (P+30)h
(P+2B)h (P+2C)h (P+2D)h (P+2E)h (P+2F)h (P+30)h
135: 4 136: 137: 138: 2 139: 13A:
135: 136: 137: 138: 139: 13A:
(P+31)h
(P+31)h
1
13B:
13B:
(P+32)h
(P+32)h
1
13C:
13C:
(P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h
(P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h
13D: 13E: 13F: 6 140: 141: 142:
13D: 13E: 13F: 140: 141: 142:
Table 60: Partition and Erase Block Region Information (Sheet 1 of 2)
128 Mbit Address B 12C: 12D: 12E: 12F: 130: 131: 132: 133: --01 --16 --00 --08 --00 --11 --00 --00 T — — — — — — — — B --01 --16 --00 --08 --00 --11 --00 --00 T — — — — — — — — B --01 --16 --00 --08 --00 --11 --00 --00 T — — — — — — — — B --01 --16 --00 --08 --00 --11 --00 --00 T — — — — — — — — 256 Mbit 512 Mbit 1 Gbit
Datasheet 118
April 2008 309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 60: Partition and Erase Block Region Information (Sheet 2 of 2)
128 Mbit Address B 134: 135: 136: 137: 138: 139: 13A: 13B: 13C: 13D: 13E: 13F: 140: 141: 142: --01 --07 --00 --00 --04 --64 --00 --12 --02 Mux --03 Non Mux --0A --00 --10 --00 --10 --00 T — — — — — — — — — — — — — — — B --01 --0F --00 --00 --04 --64 --00 --12 --02 Mux --03 Non Mux --0A --00 --10 --00 --10 --00 T — — — — — — — — — — — — — — — B --01 --1F --00 --00 --04 --64 --00 --12 --02 Mux --03 Non Mux --0A --00 --10 --00 --10 --00 T — — — — — — — — — — — — — — — B --01 --3F --00 --00 --04 --64 --00 --12 --02 Mux --03 Non Mux --0A --00 --10 --00 --10 --00 T — — — — — — — — — — — — — — — 256 Mbit 512 Mbit 1 Gbit
April 2008 309823-10
Datasheet 119
Numonyx™ StrataFlash® Cellular Memory (M18)
13.0
Next State
The Next State Table shows command inputs and the resulting next state of the chip. The Output Next State Table shows command inputs and the resulting output multiplexed next state of the chip.
Table 61: Next State Table (Sheet 1 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh )
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h ) Lo ck / RC R / EC R Se tu p
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
Ready
Re ad y
Pr og rm Se tu p
BP Se tu p
Er as e Se tu p
BE FP Se tu p
Ready
BC Se tu p
OT P Se tu p
Ready
N/ A
Ready
Lock/RCR/ECR Setup
Ready (Lock Error [Botch])
Re ad y (U nlo ck Blo ck)
Ready (Lock Error [Botch])
Re ad y (L oc k Er ror [B ot ch ])
Re ad y (L oc k Bl oc k)
Re ad y (L oc k do wn Bl oc k)
Re ad y (S et CR )
N/ A
Ready (Lock Error [Botch])
Setup
OTP Busy IS in OT P Bu sy
OTP Busy
N/ A
OTP Busy
OTP
Busy
OT P Bu sy
OT P Bu sy
IS in OTP Busy
OTP Busy
Illegal State in OTP Busy
OTP Busy
N/ A
OTP Busy
IS in OTP Busy
OTP Busy
OTP Busy
Datasheet 120
April 2008 309823-10
WSM Operation Completes N/ A N/ A N/ A Re ad y
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 2 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh )
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh ) N/ A
other
Setup IS in Pg m Bu sy
Word Program Busy
Pgm Busy
Busy
Pg m Bu sy
Pg m Bu sy
IS in Pgm Busy
Pg m Bu sy
Pg m Su sp
Word Pgm Busy
IS in Word Pgm Busy
Word Pgm Busy
N/ A
Pgm Busy
Word Progra m
IS in Pgm Busy
Word Pgm Busy Pg m Su sp (E r bit s cle ar)
Suspend
Pg m Su sp
IS in Pg m Su sp
Pg m Su sp en d
IS in Pgm Susp
Pg m Bu sy
Pgm Susp
W or d Pg m Su sp
Illegal State in Pgm Suspend
Word Program Suspend
N/ A
Word Pgm Susp
IS in Pgm Suspend
Word Program Suspend
April 2008 309823-10
Datasheet 121
WSM Operation Completes N/ A Re ad y N/ A
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 3 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh ) Setup BP Load 1
(10)
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
BP Load 1 BP Load 2 if word count >0, else BP confirm Re ad y (E rro r [B ot ch ])
BP Load 2
(10)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP Confirm if data load in program buffer is complete, else BP load 2
BP Confirm
Re ad y (E rro r [B ot ch ]) Ill eg al St at e in BP Bu sy
BP Bu sy
Re ad y (E rro r [B ot ch ])
Buffer Progra m (BP) BP Busy
BP Bu sy
IS in BP Bu sy
BP Bu sy
BP Bu sy
BP Su sp
BP Bu sy
IS in BP Bu sy
BP Bu sy
BP Bu sy
IS in BP Busy
BP Bu sy Ill eg al St at e in BP Bu sy BP Su sp (E r bit s cle ar)
BP Suspend
BP Su sp
IS in BP Su sp
BP Su sp en d
BP Bu sy
BP Su sp en d
BP Su sp
IS in BP Su sp
BP Su sp en d
N/ A
BP Susp N/ A
IS in BP Suspend Datasheet 122
BP Su sp en d April 2008 309823-10
WSM Operation Completes N/ A Re ad y
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 4 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh )
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h ) Era se Bu sy
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
Setup
Ready (Error [Botch])
Ready (Error [Botch])
N/ A
Ready (Err Botch0])
Busy
Er as e Bu sy
IS in Er as e Bu sy
Er as e Bu sy
IS in Erase Busy
Era se Bu sy
Er as e Su sp
Erase Busy
IS in Erase Busy
Erase Busy
N/ A
Erase Busy
IS in Erase Busy Erase W or d Pg m Se tu p in Er as e Su sp
Erase Busy Lo ck / RC R/ EC R Se tu p in Er as e Su sp
Suspend
Er as e Su sp
BP Se tu p in Er as e Su sp
IS in Erase Suspen d
Era se Bu sy
Erase Suspen d
Er as e Su sp (E r bit s cle ar)
Er as e Su sp
Er as e Su sp
IS in Er as e Su sp
Erase Suspend
N/ A
Erase Susp
IS in Erase Susp Setup W or d Pg m bu sy in Er as e Su sp W or d Pg m bu sy in Er as e Su sp
Erase Suspend N/ A Word Pgm Busy in Ers Suspend N/ A
Word Pgm busy in Erase Suspend
Word Progra m in Erase Suspe nd
Busy
IS in Pg m bu sy in Er s Su sp
IS in Word Pgm busy in Ers Susp
Wo rd Pg m bu sy in Era se Su sp
W or d Pg m Su sp in Er s Su sp
Word Pgm busy in Erase Susp
IS in Word Pgm busy in Ers Susp
Word Pgm busy in Erase Susp
April 2008 309823-10
Datasheet 123
WSM Operation Completes N/ A Re ad y N/ A Er as e Su sp
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 5 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh )
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
Illegal State (IS) in Pgm busy in Erase Suspend
Word Pgm busy in Erase Suspend
Word Pgm busy in Erase Suspend
Word Progra m in Erase Suspe nd
Suspend
W or d Pg m su sp in Er as e Su sp
iS in pg m su sp in Er as e Su sp
W or d Pg m su sp in Er as e Su sp
IS in pgm susp in Erase Susp
Wo rd Pg m bu sy in Era se Su sp
W or d Pg m su sp in Er as e Su sp
W or d Pg m Su sp in Er as e Su sp
W or d Pg m Su sp in Er as e Su sp : Er ror bit s cle ar
W or d Pg m Su sp in Er as e Su sp
IS in Word Pgm Susp in Erase Susp
Word Pgm Susp in Erase Susp
N/ A
Word Pgm Susp in Erase Susp N/ A
Illegal State in Word Program Suspend in Erase Suspend
Word Pgm Suspend in Erase Suspend
Word PgmSuspen d in Erase Suspend
Datasheet 124
April 2008 309823-10
WSM Operation Completes IS in Er as e Su sp
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 6 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh ) Setup BP Load 1
(10)
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
BP Load 1 BP Load 2 if word count >0, else BP confirm Er as e Su sp : Er ror [B ot ch ]
BP Load 2
(10)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP Confirm in Erase Suspend when count=0, ELSE BP load 2
BP Confirm
Erase Suspend (Error [BotchBP])
BP Bu sy in Ers Su sp BP Su sp in Er as e Su sp
Erase Susp: Error [Botch BP]
BP in Erase Suspe nd
BP Busy
BP Bu sy in Er as e Su sp
IS in BP Bu sy in Er as e Su sp
BP Bu sy in Er as e Su sp
Illegal State in BP Busy in Erase Susp
BP Busy in Erase Susp
IS in BP Busy in Erase Suspend
BP Busy in Erase Susp
N/ A
BP Busy in Erase Susp
IS in BP Busy
BP Busy in Erase Suspend
BP Susp
April 2008 309823-10
BP Su sp in Er as e Su sp
IS in BP Su sp in Er as e Su sp
BP Su sp in Er as e Su sp
Illegal State in BP Busy in Erase Susp
BP Bu sy in Era se Su sp
BP Susp in Erase Susp
BP Su sp in Er as e Su sp : Er ror bit s cle ar
BP Su sp in Er as e Su sp
IS in BP Busy in Erase Suspend
BP Susp in Erase Susp
N/ A
BP Susp in Erase Susp
Datasheet 125
WSM Operation Completes N/ A Er as e Su sp IS in Er as e Su sp N/ A
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 7 of 7)
Command Input and Resulting Chip Next State
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
(4,12)
Read ID/Query
(5)
Other Commands
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh )
(4 1h )
(E 9h )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h ) Er as e Su sp : Er ror [B ot ch ]
(0 1h )
(2 Fh )
(0 3h , 04 h)
(x xh )
other
Lock/RCR/ECR Setup in Erase Suspend
Erase Suspend: Lock Error [Botch]
Era se Su sp: Un loc k Blo ck BC Bu sy
Erase Susp: Lock Error [Botch]
Er as e Su sp Bl k Lo ck
Er as e Su sp Bl k Lk Do wn
Er as e Su sp CR Se t
N/ A
Erase Susp: Error [Botch]
Setup
Ready (Error [Botch]) IS in BC Bu sy
Ready: Error [Botch]
Ready: Error [Botch]
Blank Check (BC)
Blank Check Busy IS in Blank Check Busy
BC Bu sy
BC Bu sy
IS in BC Busy
BC Busy
IS in BC Busy
BC Busy
N/ A
BC Busy
BC Busy BE FP Lo ad Da ta
BC Busy
Setup BEFP
Ready: Error [Botch]
Ready: Error [Botch]
BEFP Busy
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
Re ad y
BEFP Busy
Datasheet 126
April 2008 309823-10
WSM Operation Completes N/ A N/ A Re ad y N/ A Re ad y
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 62: Output Next State Table
Command Input to Chip and Resulting Output MUX Next State Generic Command Setup
(4,5,12) (5) (9) (9)
Block Address Change
Write ECR/RCR Confirm
(9)
Lock-down Blk Confirm
(4,5,12)
Lock/RCR/ECR Setup
Pgm/Ers Suspend
( 4,12)
Read ID/Query
(5)
Other Commands ot he r Output MUX does not Change
(3)
Lock Blk Confirm
(2)
Current Chip State
(F Fh ) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Confirm WordPgmSetup, Word Pgm Setup in Erase Susp, BP Confirm in Erase Suspend, Blank Check Setup, Blank Check Busy Lock/RCR/ECR Setup, Lock/RCR/ECR Setup in Erase Susp BP Setup, Load 1, Load 2 BP Setup, Load1, Load 2 in Erase Susp. BP Busy BP Busy in Erase Suspend Word Program Busy, Word Prgm Busy in Erase Suspend, Erase Busy
(4 1h )
(E 9h )
(E Bh )
(2 0h )
(8 0h )
(D 0h )
(B 0)
(7 0h )
(5 0h )
(9 0h , 98 h)
(6 0h )
(B Ch )
(C 0h )
(0 1h )
(2 Fh )
(0 3h , 04 h)
Status Read
Status Read
Status Read
Output MUX will not change
Output MUX does not Change
Output MUX does not change
Status Read
Status Read
Status Read
Array Read
ID/Query Read
Ready, Word Prgm Suspend, BP Suspend, Phase-1 BP Suspend, Erase Suspend, BP Suspend in Erase Suspend OTP Busy
Output MUX does not Change
Status Read
Status Read
Output MUX does not change
Status Read
SR Re ad
Notes: 1. The Partition Data When Read field shows what users read from the flash chip after issuing the appropriate command, given the Partition Address is not changed from the address given during the command. Read-while-write functionality gives more flexibility in data output from the device. The data read from the chip depends on the Partition Address applied to the device. Depending on the command issued to the chip, each partition is placed into one of the following three output states during commands: Read Array, Read Status or Read ID/CFI. This partition's output state is retained until a
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Output MUX does not change
Ar ra y Re ad
WSM Operation Completes
(13)
Read Status
Word Pgm Setup
(9)
(6)
Blank Check
Array Read
BEFP Setup
Erase Setup
OTP Setup
BP Setup
Clear SR
Confirm
(5)
Numonyx™ StrataFlash® Cellular Memory (M18)
2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
new command is issued to the chip at that Partition Address. This allows the user to set partition #1's output state to Read Array, and partition #4's output state to Read Status. Each time the partition address is changed to partition #4 (without issuing a new command), the Status will be read from the chip. Illegal commands include commands outside of the allowed command set (allowed commands: 41H [pgm], 20H [erase], etc.) All partitions default to Read Array on powerup. If a Read Array is attempted from a busy partition, the result is unreliable data. When the user returns to this partition address later, the output mux will be in the “Read Array” state from its last visit. the Read ID and Read Query commands perform the same function in the device. The ID and Query data are located at different locations in the address map. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. The Clear Status command clears only the error bits in the status register if the device is not in the following modes: 1) WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2) Suspend states (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend). BEFP writes are allowed only when the status register bit #0 = 0 or else the data is ignored. The current state is that of the chip and not of the partition. Each partition remembers w hich output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the chip, but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the operation and then move to the Ready State. Buffered programming will botch when a different block address (as compared to address given with E9 command) is written during the BP Load1 and BP Load2 states. WA0 refers to the block address latched during the first write cycle of the current operation. All two cycle commands are considered as a contiguous whole during device suspend states. Individual commands are not parsed separately; that is, the 2nd cycle of an erase command issued in program suspend will NOT resume the program operation. The Buffered Program setup command (0xE9) will not change the partition state. The Buffered Program Confirm command (0xD0) will place the partition in read status mode.
Appendix A AADM Mode
A.1 AADM Feature Overview
The following is a list of general requirements for AADM mode. Additional details can be found in subsequent sections. • Feature Availability: AADM mode is available in devices that are configured as A/ D MUX. With this configuration, AADM mode is enabled by setting a specific volatile bit in the RCR. • High Address Caputure (A[MAX:16]): When AADM mode is enabled, A[MAX:16] and A[15:0] are captured from the A/DQ[15:0] balls. The selection of A[MAX:16] or A[15:0] is determined by the state of the OE# input, as A[MAX:16] is captured when OE# is at VIL. • Read & Write Cycle Support: In AADM mode, both asynchronous and synchronous Cycles are supported. • Customer Requirements: For AADM operation, the customer is required to ground A16-Amax. • Other Characteristics: For AADM, all other device characteristics (pgm time, erase time, ICCS, etc.) are the same as A/D MUX unless otherwise stated.
A.2
AADM Mode Enable (RCR[4]=1)
Setting RCR.4 to its non-default state (‘1b) enables AADM mode: • The default device configuration upon Reset or Powerup is A/D MUX Mode • Upon setting RCR[4]=1, the upper Addresses A[max:16] are latched as all 0’s by default.
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A.3
Bus Cycles and Address Capture
AADM bus operations have one or two address cycles. For two address cycles, the upper address (A[MAX:16]) must be issued first, followed by the lower address (A[15:0]). For bus operations with only one address cycle, only the lower address is issued. The upper address that applies is the one that was most recently latched on a previous bus cycle. For all read cycles, sensing begins when the lower address is latched, regardless of whether there are one or two address cycles. In bus cycles, the external signal that distinguishes the upper address from the lower address is OE#. When OE# is at VIH, a lower address is captured; when OE# is at VIL, an upper address is captured. When the bus cycle has only one address cycle, the timing waveform is similar to A/D MUX mode. The lower address is latched when OE# is at VIH, and data is subsequently outputted after the falling edge of OE#.
Note:
When the device initially enters AADM mode, the upper address is internally latched as all 0’s.
A.3.1
WAIT Behavior
The WAIT behavior in AADM mode functions the same as the legacy M18 non-MUX WAIT behavior (ADMux WAIT behavior is unique). In other words, WAIT will always be driven whenever DQ[15:0] is driven, and WAIT will tri-state whenever DQ[15:0] tristate. In asynchronous mode (RCR[15] = ‘1b), WAIT always indicates “valid data” when driven. In synchronous mode (RCR[15] = ‘0b), WAIT indicates “valid data” only after the latency count has lapsed and the data output data is truly valid.
A.3.2
Asynchronous Read and Write Cycles
For asynchronous read and write cycles, ADV# must be toggled high-low-high a minimum of one time and a maximum of two times during a bus cycle. If ADV# is toggled low twice during a bus cycle, OE# must be held low for the first ADV# rising edge and OE# must be held high for the second ADV# rising edge. The first ADV# rising edge (with OE# low) captures A[MAX:16]. The second ADV# rising edge (with OE# high) captures A[15:0]. Each bus cycle must toggle ADV# high-low-high at least one time in order to capture A[15:0]. For asynchronous reads, sensing begins when the lower address is latched. During asynchronous cycles, it is optional to capture A[MAX:16]. If these addresses are not captured, then the previously captured A[MAX:16] contents will be used.
A.3.2.1
Asynchronous Read Cycles
For asynchronous read and latching specifications, refer to Table 63, “AADM Aynchronous and Latching Timings” on page 130. For asynchronous read timing diagrams, refer to Figure 61, “AADM Asynchronous Read Cycle (Latching A[MAX:0])” on page 130 and Figure 62, “AADM Asynchronous Read Cycle (Latching A[15:0] only)” on page 131. For AADM, note that asynchronous read access is from the rising edge of ADV# rather than the falling edge. (i.e. TVHQV rather than TVLQV)
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Table 63: AADM Aynchronous and Latching Timings
Num R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R15 R16 Sym tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGLTV tGLTX 0 0 7 11 9 7 0 0 9 9 Min (nS) Max (nS) 20 150 Num R17 R101 R102 R104 R105 R106 R107 R109 R111 R127 R128 R129 Sym tGHTZ tAVVH tELVH tVLVH tVHVL tVHAX tVHGL tVHQV(1) tPHVH tGHVH tGLVH tVHGH 30 3 3 3 5 9 7 7 5 3 96 Min (nS) Max (nS) 9
Notes: 1. TVHQV applies to asynchronous read access time. 2. A read cycle may be restarted prior to completing a pending read operation, but this may occur only once before the sense operation is allowed to complete.
Figure 61: AADM Asynchronous Read Cycle (Latching A[MAX:0])
A/DQ[15:0]
A[MAX:16] R101 R106 R105 R101 R104
A[15:0] R106
DQ[15:0]
R104
R109
ADV# R8 R102 CE# R128 R129 OE# R15 R16 WAIT R17 R13 R127 R107 R7 R4 R9 R127+R107 R11
Notes: 1. Diagram shows WAIT as active low (RCR.10=0)
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1
Figure 62: AADM Asynchronous Read Cycle (Latching A[15:0] only)
A/DQ[15:0] R101
A[15:0] R106
DQ[15:0]
R104 ADV#
R109
R8 R102 CE# R7 R107 OE# R15 R16 WAIT R17 R13 R4 R9 R127+R107 R11
Notes: 1. Diagram shows WAIT as active low (RCR.10=0). 2. Without latching A[MAX:16] in the Asynchronous Read Cycle, the previously latched A[MAX:16] applies.
A.3.2.2
Asynchronous Write Cycles
For asynchronous write specifications, refer to Table 64, “AADM Write Timings” on page 132. For asynchronous write timing diagrams, refer to Figure 63, “AADM Asynchronous Write Cycle (Latching A[MAX:0])” on page 132 and Figure 64, “AADM Asynchronous Write Cycle (Latching A[15:0] only)” on page 132.
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Table 64: AADM Write Timings
Num W1 W2 W3 W4 W6 W7 Symbol tPHWL tELWL tWLWH tDVWH tWHEH tWHDX Min(nS) 150 0 40 40 0 0 Num W9 W10 W11 W13 W14 W23 Symbol tWHWL tVPWH tWVVL tBHWH tWHGL tGHWL Min(nS) 20 200 0 200 0 0
Figure 63: AADM Asynchronous Write Cycle (Latching A[MAX:0])
W7 A/DQ[15:0] ADV# W6 CE# OE# W14 W23 W2 WE# W13 WP# W1 RST# W3 W4 W9 W2 A[MAX:16] A[15:0] DQ[15:0]
Figure 64: AADM Asynchronous Write Cycle (Latching A[15:0] only)
W7 A/DQ[15:0] ADV# W6 CE# OE# W14 W4 W2 WE# W13 WP# W1 RST# W3 W9 W2 A[15:0] DQ[15:0]
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A.3.3
Synchronous Read and Write Cycles
Just as asynchronous bus cycles, synchronous bus cycles (RCR[15] = ‘0b) can have one or two address cycles. If the are two address cycles, the upper address must be latched first with OE# at VIL followed by the lower address with OE# at VIH. If there is only one address cycle, only the lower address will be latched and the previously latched upper address applies. For reads, sensing begins when the lower address is latched, but for synchronous reads, addresses are latched on a rising clock CLK instead of a rising ADV# edge. For synchronous bus cycles with two address cycles, it is not necessary to de-assert ADV# between the two address cycles. This allows both the upper and lower address to be latched in only two clock periods.
A.3.3.1
Synchronous Read Cycles
For synchronous read specifications, refer to Table 65, “AADM Synchronous Timings” on page 133. For synchronous read timing diagrams, refer to the following: • Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address Cycles)” on page 134 • Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address Cycles)” on page 134 • Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135
Table 65: AADM Synchronous Timings
Num Sym Target (104 MHz) (108MHz) Min (nS) R201 R203 R301 R302 R303 R304 R305 R306 R307 tCLK tRISE/FALL tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV 2 5 7 4 3 3 3.5 7 2 9 Max (nS) See note 1.5 Notes (3) 1 5 Num Sym Target (104 MHz) (108MHz) Min (nS) R311 R312 R313 R314 R316 R317 R318 R319 R320 tCHVL tCHTX tCHVH tCHGL tVLVH tVHCH tCHGH tGHCH tGLCH 2.5 2 2 2.5 tCLK 3 2 3 3 2*tCLK 2 4 Max (nS) Notes (3)
Notes: 1. The device must operate down to 9.6MHz in synchronous burst mode. 2. During the address capture phase of a read burst bus cycle, OE# timings relative to CLK shall be identical to those of ADV# relative to CLK. 3. In synchronous burst read cycles, the asynchronous OE# to ADV# setup and hold times must also be met (Tghvh & Tvhgl) to signify that the address capture phase of the bus cycle is complete. 4. To prevent A/D bus contention between the host and the memory device, OE# may only be asserted low after the host has satisfied the ADDR hold spec, Tchax. 5. Rise and fall time specified between Vil & Vih 6. A read cycle may only be terminated (prior to the completion of sensing data) one time before a full bus cycle must be allowed to complete.
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Figure 65: AADM Sync Burst Read Cycle (ADV# De-asserted between Address Cycles)
A/DQ[15:0]
A[MAX:16] R306 R301
A[15:0] R306 R315 R301 R304
DQ[15:0]
DQ[15:0]
A
R305
CLK R302 R317 R311 R316 ADV# R303 CE# R318 R320 OE# WE# R307 WAIT R312 R319 R314 R313 R311 R316 R302 R317 R313
Notes: 1. Diagram shows WAIT as active low (RCR.10=0) and asserted w ith Data (RCR.8=0). 2. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram).
Figure 66: AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address Cycles)
A/DQ[15:0]
A[MAX:16] R306 R301 R301
A[15:0] R306 R315 R304
DQ[15:0] R305
DQ[15:0]
A
CLK R302 R311 ADV# R303 CE# R318 R320 OE# WE# R307 WAIT R312 R319 R314 R317 R313
Notes: 1. Diagram shows WAIT as active low (RCR.10=0) and asserted w ith Data (RCR.8=0)
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Figure 67: AADM Sync Burst Read Cycle (Latching A[15:0] only)
A/DQ[15:0]
A[15:0] R306 R315 R301 R304
DQ[15:0] R305
DQ[15:0]
A
CLK R302 R311 ADV# R303 CE# R314 R317 R313
OE# WE# R307 WAIT R312
Notes: 1. Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0). 2. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram) 3. Without latching A[MAX:16] in the Sync Read Cycle, the previously latched A[MAX:16] applies.
A.3.4
Synchronous Write Cycles
For synchronous writes, only the address latching cycle(s) are synchronous. Synchronous address latching is depicted in the timing diagrams for synchronous read cycles: • Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address Cycles)” on page 134 • Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address Cycles)” on page 134 • Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135 The actual write operation (rising WE# edge) is asynchronous and is independent of CLK. Asynchronous writes are depicted in the timing diagrams for asynchronous write cycles: • Figure 63, “AADM Asynchronous Write Cycle (Latching A[MAX:0])” on page 132 • Figure 64, “AADM Asynchronous Write Cycle (Latching A[15:0] only)” on page 132
A.3.5
System Boot
Systems that use the AADM mode will boot from the bottom 128k Bytes of device memory because A[MAX:16] are expected to be grounded in-system. The 128k Byte boot region is sufficient to perform required boot activities before setting RCR[4] to enable AADM mode.
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Appendix B Additional Information
Order Number 315567 307654 310048 309311 315651 310058 Document/Tool Numonyx™ StrataFlash® Cellular Memory (M18) Developer’s Manual Numonyx™ StrataFlash® Cellular Memory (M18 SCSP); 2048-Mbit M18 (Non-Mux and AD-Mux I/O) Family with Synchronous PSRAM Datasheet Designing with Numonyx™ StrataFlash Cellular Memory, Application Note 822 Numonyx™ StrataFlash Note 841
® Wireless Memory and Pre-enabling Numonyx™ StrataFlash® ®
PrimeCellTM Design Guide, Application
®
Cellular Memory (M18 SCSP) to ARM
Migration Guide for Numonyx™ StrataFlash 860
® C ellular Memory (M18) 90 nm to 65 nm, Application Note
Effect of Program Buffer Size on System Interrupt Latency, Application Note 816
Notes: 4. Visit Numonyx’s World Wide Web home page at http://www.numonyx.com for technical documentation and tools or for the most current information on Numonyx flash products.
Appendix C Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please contact your local Numonyx representative.
Table 66: 38F Type Stacked Components
PF Package Designator 38F Product Line Designator 5070 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = RAM die #1 Stacked NOR Flash + RAM Char 4 = RAM die #2 (See First character applies to Flash die #1 Second character applies to Flash die #2 (See V= 1.8 V Core and I/O; Separate Chip Enable per die (See 0= No parameter blocks; NonMux I/O interface (See M0 NOR Flash Prodcut Family Y Voltage/NOR Flash CE# Configuration 0 Parameter / Mux Configuration B Ballout Identifier 0 Device Details
B= x16D Ballout (See 0= Original released version of this product
PF = SCSP, RoHS RD = SCSP, Leaded
details)
Table 68, “38F / 48F Density Decoder” on page 137 for
details)
Table 69, “NOR Flash Family Decoder” on page 138 for
Table 70, “Voltage / NOR Flash CE# Configurati on Decoder” on page 138
for details)
for details)
Table 71, “Parameter / Mux Configurati on Decoder” on page 138
Table 72 , “Ballout Decoder ” on page 13 9 for
details)
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Table 67: 48F Type Stacked Components
PC Package Designator PC = Easy BGA, RoHS RC = Easy BGA, Leaded JS = TSOP, RoHS TE = TSOP, Leaded PF = SCSP, RoHS RD = SCSP, Leaded 48F Product Line Designator 4400 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = Flash die #3 Stacked NOR Flash only Char 4 = Flash die #4 (See First character applies to Flash dies #1 and #2 Second character applies to Flash dies #3 and #4 (See Table 69, “NOR Flash Family Decoder” on page 138 for P0 NOR Flash Prodcut Family V Voltage/NOR Flash CE# Configuration B Parameter / Mux Configuration 0 Ballout Identifier 0 Device Details
V= 1.8 V Core and 3 V I/O; Virtual Chip Enable (See
B= Bottom parameter; Non-Mux I/O interface (See
0= Discrete Ballout (See
Table 68, “38F / 48F Density Decoder” on page 137 for
details)
details)
for details)
Table 70, “Voltage / NOR Flash CE# Configurati on Decoder” on page 138
Table 71, “Parameter / Mux Configurati on Decoder” on page 138
for details)
Table 72 , “Ballout Decoder ” on page 13 9 for
details)
0= Original released version of this product
Table 68: 38F / 48F Density Decoder
Code 0 1 2 3 4 5 6 7 8 9 A B C D E F No Die 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit 128-Gbit 256-Gbit 512-Gbit Flash Density No Die 4-Mbit 8-Mbit 16-Mbit 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit RAM Density
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Table 69: NOR Flash Family Decoder
Code C C3 J3v.D L18 / L30 M18 P30 / P33 W18 / W30 Family Marketing Name Numonyx™ Advanced+ Boot Block Flash Memory Numonyx™ Embedded Flash Memory Numonyx™ StrataFlash® Wireless Memory Numonyx™ StrataFlash® Cellular Memory Numonyx™ StrataFalsh® Embedded Memory Numonyx™ Wireless Flash Memory No Die
J
L M P W 0(zero)
Table 70: Voltage / NOR Flash CE# Configuration Decoder
Code Z I/O Voltage (Volt) 3.0 1.8 3.0 3.0 1.8 3.0 3.0 1.8 3.0 1.8 1.8 3.0 1.8 1.8 1.8 1.8 1.8 3.0 Core Voltage (Volt) CE# Configuration Seperate Chip Enable per die Seperate Chip Enable per die Seperate Chip Enable per die Virtual Chip Enable Virtual Chip Enable Virtual Chip Enable Virtual Address Virtual Address Virtual Address
Y
X V U T R Q P
Table 71: Parameter / Mux Configuration Decoder (Sheet 1 of 2)
Code, Mux Identification 0 = Non Mux 1 = AD Mux 3 = "Full" AD Mux Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
Any
NA
Notation used for stacks that contain no parameter blocks
1 B = Non Mux C = AD Mux F = "Full" Ad Mux 2 3 4 2 4 X32 X16
Bottom Bottom Bottom Bottom Bottom Bottom
Top Bottom Top Bottom Bottom
Top Bottom Top
Top Top
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Table 71: Parameter / Mux Configuration Decoder (Sheet 2 of 2)
Code, Mux Identification Number of Flash Die 1 T = Non Mux U = AD Mux W = "Full" Ad Mux 2 3 4 2 4 X32 X16 Bus Width Flash Die 1 Top Top Top Top Top Top Bottom Top Bottom Top Top Flash Die 2 Bottom Top Bottom Flash Die 3 Bottom Bottom Flash Die 4
Table 72: Ballout Decoder
Code 0 (Zero) B C Q U V W SDiscrete ballout (Easay BGA and TSOP) x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus) x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus) QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus) x32SH ballout, 106 ball (x32 NOR only Share Bus) x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus Ballout Definition
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