SMC032BFY6E

SMCxxxBF 32MByte, 64MByte, 128MByte, 256MByte, 512MByte, 1GByte, 2GByte, and 4GByte 3.3/5V Supply CompactFlash™ Card Preliminary Data Features ■ Custom-designed, highly-integrated memory controller – Fully compliant with CompactFlashTM specification 3.0 – Fully compatible with PCMCIA specification – PC Card ATA Interface supported – True IDE mode compatible – Up to PIO mode 6 supported – Up to 4 Multi-Word DMA supported – Hardware RS-code ECC (4 Bytes/528 Bytes correction) Small form factor – 36.4mm x 42.8mm x 3.3mm Low-power CMOS technology 3.3V / 5.0V power supply Power saving mode (with Automatic Wake-up) High reliability – MTBF > 3,000,000 hours – Data reliability: < 1 non-recoverable error per 1014 bits read – Endurance: > 2,000,000 Erase/Program cycles – Number of card insertions/removals: >10,000 Hot swappable ■ CompactFlashTM ■ ■ ■ ■ ■ High performance – Up to 23.8MB/s transfer rate – Sustained Write performance (host to card): 12.5MB/s – Sustained Read Performance (Host to Card: 19MB/s) Available densities (formatted) – 32 MBytes to 4 GBytes Operating System support – Standard Software Drivers operation ■ ■ ■ December 2007 Rev 3 1/91 www.numonyx.com 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. SMCxxxBF Table 1. Product List Part Number SMC032BF SMC064BF SMC128BF SMC256BF SMCxxxBF SMC512BF SMC01GBF SMC02GBF SMC04GBF CF Type I 3.3V+-5%, 5V+-10% Package Form Factor Operating Voltage Range Reference 2/91 SMCxxxBF Contents Contents 1 2 3 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Card physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 4.4 Electrical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Additional requirements for CompactFlash Advanced Timing mode . . . . 23 5 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 5.2 5.3 5.4 Attribute Memory Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Common Memory Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 True IDE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Card Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Configuration Option Register (200h in Attribute Memory) . . . . . . . . . . . 34 6.1.1 6.1.2 6.1.3 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LevlREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Conf5 - Conf0 (Configuration Index) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 Card Configuration and Status Register (202h in Attribute Memory) . . . . 35 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SigChg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IOis8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PwrDwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 Pin Replacement Register (204h in Attribute Memory) . . . . . . . . . . . . . . 36 6.3.1 6.3.2 CReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/91 Contents 6.3.3 6.3.4 6.3.5 6.3.6 SMCxxxBF RReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 Socket and Copy Register (206h in Attribute Memory) . . . . . . . . . . . . . . 37 6.4.1 6.4.2 Drive # . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 6.6 6.7 6.8 Attribute Memory Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I/O Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Common Memory Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 True IDE Mode I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 8 Host configuration requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 8.2 8.3 8.4 8.5 CF-ATA Drive Register Set Definition and Protocol . . . . . . . . . . . . . . . . . 43 Memory Mapped Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contiguous I/O Mapped Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Primary and Secondary Address Configurations . . . . . . . . . . . . . . . . 46 True IDE Mode Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9 CF-ATA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1 9.2 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 Bit 7 (BBK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 6 (UNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 4 (IDNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 2 (Abort) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bit 0 (AMNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 9.4 9.5 Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Sector Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Sector Number (LBA 7-0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/91 SMCxxxBF Contents 9.6 9.7 9.8 Cylinder Low (LBA 15-8) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Cylinder High (LBA 23-16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Drive/Head (LBA 27-24) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6 9.8.7 9.8.8 Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 6 (LBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 4 (DRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 3 (HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 2 (HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 1 (HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit 0 (HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.9 Status & Alternate Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.9.8 Bit 7 (BUSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 6 (RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 5 (DWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 4 (DSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 3 (DRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 2 (CORR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 1 (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bit 0 (ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.10 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.10.1 9.10.2 9.10.3 9.10.4 Bit 7 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bit 2 (SW Rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bit 1 (–IEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.11 Card (Drive) Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.11.1 9.11.2 9.11.3 9.11.4 9.11.5 9.11.6 9.11.7 9.11.8 Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 6 (–WTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 5 (–HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 4 (–HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 3 (–HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 2 (–HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 1 (–nDS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bit 0 (–nDS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 CF-ATA command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5/91 Contents SMCxxxBF 10.1 10.2 10.3 10.4 Check Power Mode (98h or E5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Execute Drive Diagnostic (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Erase Sector(s) (C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Identify Drive (ECh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 Word 0: General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Word 1: Default Number of Cylinders . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Word 3: Default Number of Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Word 6: Default Number of Sectors per Track . . . . . . . . . . . . . . . . . . . . 59 Word 7-8: Number of Sectors per Card . . . . . . . . . . . . . . . . . . . . . . . . . 59 Word 10-19: Memory Card Serial Number . . . . . . . . . . . . . . . . . . . . . . 59 Word 23-26: Firmware Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Word 27-46: Model Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Word 47: Read/Write Multiple Sector Count . . . . . . . . . . . . . . . . . . . . . 59 10.4.10 Word 49: Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.11 Word 51: PIO Data Transfer Cycle Timing Mode . . . . . . . . . . . . . . . . . . 59 10.4.12 Word 53: Translation Parameter Valid . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track . . . . 59 10.4.14 Word 57-58: Current Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4.15 Word 59: Multiple Sector Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4.16 Word 60-61: Total Sectors Addressable in LBA Mode . . . . . . . . . . . . . . 60 10.4.17 Word 63: Multi-Word DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4.18 Word 64: Advanced PIO transfer modes supported . . . . . . . . . . . . . . . 61 10.4.19 Word 65: Minimum Multi-Word DMA transfer cycle time . . . . . . . . . . . . 61 10.4.20 Word 66: Recommended Multi-Word DMA transfer cycle time . . . . . . . 61 10.4.21 Word 67: Minimum PIO transfer cycle time without flow control . . . . . . 61 10.4.22 Word 68: Minimum PIO transfer cycle time with IORDY . . . . . . . . . . . . 61 10.4.23 Word 163: Advanced True IDE Timing mode capabilities and settings . 62 10.4.24 Word 164: Advanced PCMCIA I/O and Memory Timing modes capabilities and settings 62 10.5 10.6 10.7 10.8 10.9 Idle (97h or E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Idle Immediate (95h or E1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Initialize Drive Parameters (91h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 NOP (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Read Buffer (E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.10 Read DMA (C8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.11 Read Multiple (C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6/91 SMCxxxBF Contents 10.12 Read Sector(s) (20h or 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.13 Read Verify Sector(s) (40h or 41h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.14 Recalibrate (1Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.15 Request Sense (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.16 Seek (7Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.17 Set Features (EFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.18 Set Multiple Mode (C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.19 Set Sleep Mode (99h or E6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.20 Standby (96h or E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.21 Standby Immediate (94h or E0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.22 Translate Sector (87h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.23 Wear Level (F5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.24 Write Buffer (E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.25 Write DMA (CAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.26 Write Multiple Command (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.27 Write Multiple without Erase (CDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.28 Write Sector(s) (30h or 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.29 Write Sector(s) without Erase (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.30 Write Verify (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11 12 13 14 CIS information (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7/91 List of tables SMCxxxBF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CF capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System Reliability and Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Assignment and Pin Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output Drive Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Attribute Memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Configuration Register (Attribute Memory) Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Common Memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Common Memory Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 True IDE PIO mode Read/Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 True IDE Multi-Word DMA Mode Read/Write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CompactFlash Memory Card Registers and Memory Space Decoding . . . . . . . . . . . . . . . 33 CompactFlash Memory Card Configuration Registers Decoding . . . . . . . . . . . . . . . . . . . . 34 Configuration Option Register (default value: 00h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CompactFlash Memory Card Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Card Configuration and Status Register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Replacement Register (default value: 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Replacement Changed Bit/Mask Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Socket and Copy Register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Attribute Memory Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Common Memory Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 True IDE Mode I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory Mapped Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Contiguous I/O Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Primary and Secondary I/O Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 True IDE Mode I/O Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Data Register Access (Memory and I/O mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data Register Access (True IDE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Drive/Head Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Status & Alternate Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Card (Drive) Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CF-ATA Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8/91 SMCxxxBF Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. List of tables Check Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Execute Drive Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Diagnostic Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Identify Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Identify Drive Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Idle Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Initialize Drive Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Read Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Read DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Read Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Read Verify Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Recalibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Request Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Extended Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Set Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Transfer Mode Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Set Multiple Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Set Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Standby Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Translate Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Translate Sector Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wear level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Write DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Write Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Write Multiple without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Write Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Write Sector(s) without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Write Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9/91 List of figures SMCxxxBF List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. CompactFlash Memory Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Attribute Memory Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Configuration Register (Attribute Memory) Write waveforms . . . . . . . . . . . . . . . . . . . . . . . 25 Common Memory Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Common Memory Write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I/O Write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 True IDE PIO mode Read/Write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 True IDE Multi-Word DMA Mode Read/Write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 32 Type I CompactFlash Memory Card Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10/91 SMCxxxBF Summary description 1 Summary description The CompactFlash is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The Card operates in three basic modes: ● ● ● PCMCIA I/O mode PCMCIA memory mode True IDE mode The CompactFlash also supports Advanced Timing modes. Advanced Timing modes are PCMCIA style I/O modes that are 100ns or faster, PCMCIA Memory modes that are 100ns or faster, True IDE PIO Modes 5,6 and Multi-Word DMA Modes 3,4. It conforms to the PC Card Specification when operating in the PCMCIA I/O mode, and in the PCMCIA Memory mode (Personal Computer Memory Card International Association standard, JEIDA in Japan), and to the ATA specification when operating in True IDE Mode. CompactFlash Cards can be used with passive adapters in a PC-Card Type II or Type III socket. The Card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as hardware RS-code Error Correction Code (ECC), defect handling, diagnostics and clock control. Once the Card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The hardware RS-code ECC allows to detect and correct 4 Bytes per 528 Bytes. The Card has a super Cap on VCC and a powerful power-loss management feature to prevent data corruption after power-down. The specification has been realized and approved by the CompactFlash Association (CFA). This non-proprietary specification enables users to develop CF products that function correctly and are compatible with future CF design. The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7. Related Documentation ● ● ● ● PCMCIA PC Card Standard, 1995 PCMCIA PC Card ATA Specification, 1995 AT Attachment Interface Document, American National Standards Institute, X3.2211994 CF+ and CompactFlash Specification Revision 3.0 11/91 Summary description Table 2. System Performance System Performance Sleep to write Sleep to read Power up to Ready Data transfer Rate (burst) Sustained Read Sustained Write Read Command to DRQ Write 85 Max. 0.07 0.26 150 23.8 (162X)(1) 19 (130X) 12.5(85X) 180 (1) (1) SMCxxxBF Unit ms ms ms MB/s MB/s MB/s µs 1. 162X, 130X and 85X, speed grade markings where 1X = 150 KBytes/s. All values are measured for an ambient temperature of 25°C. They refer to the 1GByte CompactFlash Card in PIO mode 6, cycle time 80ns, File size = 20 MB sequential; sector count = 256. Table 3. Current Consumption(1) Current Consumption (typ) 3.3V 29 65 0.9 0.9 5V 50 76 1.8 1.8 Unit mA mA mA mA Read Write Standby Sleep Mode 1. All values are typical at 25° C and nominal supply voltage and refer to 1GByte CompactFlash Card, operating in PIO mode. Table 4. Environmental Specifications Operating –40 to 85°C N/A N/A N/A N/A Non-Operating –50 to 100°C 85% RH, at 85°C 3% NaCl at 35°C(1) 30Gmax. 3,000Gmax. Environmental Specifications Temperature Humidity (non-condensing) Salt Water Spray Vibration (peak -to-peak) Shock 1. MIL STD METHOD 1009 Table 5. Physical Dimensions Physical Dimensions Unit 42.8 36.4 3.3 10 mm mm mm g Width Height Thickness Weight (typ.) 12/91 SMCxxxBF Capacity specification 2 Capacity specification This section Table 6 shows the specific capacity for the various CF models and the default number of heads, sector/tracks and cylinders. Table 6. Part Number SMC032BF SMC064BF SMC128BF SMC256BF SMC512BF SMC01GBF SMC02GBF SMC04GBF CF capacity specification Default_sectors Default_cylinders Default_heads Sectors_card _track 490 490 980 980 993 1,986 3,970 7,964 4 8 8 16 16 16 16 16 32 32 32 32 63 63 63 63 62,720 125,440 250,880 501,760 1,000,944 2,001,888 4,001,760 8,027,712 Total addressable capacity (Byte) 32,112,640 64,225,280 128,450,560 256,901,120 512,483,328 1,024,966,656 2,048,901,120 4,110,188,544 Capacity 32MB 64MB 128MB 256MB 512MB 1GB 2GB 4GB Table 7. System Reliability and Maintenance MTBF (at 25°C) Insertions/Removals Preventive Maintenance Data Reliability Endurance > 3,000,000 hours > 10,000 None < 1 Non-Recoverable Error per 1014 bits Read 0 +70 C > 2000000 Erase/Program Cycles(1) -40 +85 C > 600000 Erase/Program Cycles(1) 1. Dependent on final system qualification data. 13/91 Card physical SMCxxxBF 3 3.1 Card physical Physical description The CompactFlash Memory Card contains a single chip controller and Flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the Flash memory module(s). Figure 1 shows the Block Diagram of the CompactFlash Memory Card. The Card is offered in a Type I package with a 50-pin connector consisting of two rows of 25 female contacts on 50 mil (1.27mm) centers. Figure 10 shows Type I Card Dimensions. Figure 1. CompactFlash Memory Card Block Diagram Data In/Out Host Interface Controller Control Flash Module(s) CompactFlash Storage Card AI04300 14/91 SMCxxxBF Electrical interface 4 4.1 Electrical interface Electrical description The CompactFlash Memory Card operates in three basic modes: ● ● ● PC Card ATA using I/O Mode PC Card ATA using Memory Mode True IDE Mode, which is compatible with most disk drives The signal/pin assignments are listed in Table 8 Low active signals have a ‘–’ prefix. Pin types are Input, Output or Input/Output. The configuration of the Card is controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the memory card. Table 9 describes the I/O signals. Inputs are signals sourced from the host while Outputs are signals sourced from the Card. The signals are described for each of the three operating modes. All outputs from the Card are totem pole except the data bus signals that are bi-directional tri-state. Refer to the section titled “Electrical Specifications” for definitions of Input and Output type. Table 8. Pin Num 1 2 3 4 5 6 7 8 9(1) 10 11 12 13 14 15 16 Signal Name GND D03 D04 D05 D06 D07 –CE1 A10 –OE A09 A08 A07 VCC A06 A05 A04 I I I I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out Type Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z Signal Name GND D03 D04 D05 D06 D07 –CE1 A10 –OE A09 A08 A07 VCC A06 A05 A04 I I I I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out Type Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z Signal Name GND D03 D04 D05 D06 D07 –CS0 A10(2) –ATASEL A09 (2) Pin Assignment and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode Pin Type In, Out Type Ground I/O I/O I/O I/O I/O I I I I I I I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3Z I1Z I3U I1Z I1Z I1Z Power I I I I1Z I1Z I1Z A08(2) A07(2) VCC A06 (2) A05(2) A04 (2) 15/91 Electrical interface Table 8. Pin Num 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal Name A03 A02 A01 A00 D00 D01 D02 WP –CD2 –CD1 D11(3) D12(3) D13 D14 (3) (3) SMCxxxBF Pin Assignment and Pin Type (continued) PC Card Memory Mode Pin Type I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O In, Out Type I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U OT1 Power I O I O O I I/O I/O I/O I/O I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 PC Card I/O Mode Signal Name A03 A02 A01 A00 D00 D01 D02 –IOIS16 –CD2 –CD1 D11(3) D12(3) D13(3) D14(3) D15(3) –CE2(3) –VS1 –IORD –IOWR –WE -IREQ VCC –CSEL(5) –VS2 RESET –WAIT –INPACK –REG –SPKR –STSCHG D08(3) D09(3) I O I O O I I/O I/O I/O I/O Pin Type I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O In, Out Type I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U OT1 Power I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 Signal Name A03(2) A02 A01 A00 D00 D01 D02 –IOIS16 –CD2 –CD1 D11(3) D12(3) D13(3) D14(3) D15(3) –CS1(3) –VS1 –IORD –IOWR –WE (4) True IDE Mode Pin Type I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O In, Out Type I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 ON3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3Z Ground I3Z I3Z I3U OZ1 Power I O I O O I I/O I/O I/O I/O I2U OPEN I2Z ON1 OZ1 I3U I1U,ON1 I1U,ON1 I1Z,OZ3 I1Z,OZ3 D15(3) –CE2 (3) –VS1 –IORD –IOWR –WE READY VCC –CSEL(5)(3) –VS2 RESET –WAIT –INPACK –REG BVD2 BVD1 D08(3) D09 (3) INTRQ VCC –CSEL(5) –VS2 -RESET IORDY DMARQ -DMACK (6) –DASP –PDIAG D08(3) D09(3) 16/91 SMCxxxBF Table 8. Pin Num 49 50 Signal Name D10(3) GND Pin Type I/O In, Out Type I1Z,OZ3 Ground Signal Name D10(3) GND Pin Type I/O In, Out Type I1Z,OZ3 Ground Signal Name D10(3) GND Electrical interface Pin Assignment and Pin Type (continued) PC Card Memory Mode PC Card I/O Mode True IDE Mode Pin Type I/O In, Out Type I1Z,OZ3 Ground 1. For True IDE Mode, pin 9 is grounded. 2. The signal should be grounded by the host. 3. These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current. 4. The signal should be tied to VCC by the host. 5. The -CSEL signal is ignored by the Card in PC Card modes. However, because it is not pulled up on the Card in these modes it should not be left floating by the host in PC Card modes. In these modes, the pin is normally connected by the host to PC Card A25 or grounded by the host. 6. When the device does not operate in DMA mode, the signal should be held High or tied to VCC by the host. To ensure proper operation with older hosts when DMA mode is disabled, the Card should ignore the –DMACK signal. Table 9. Signal Description Dir. Pin Description Used (with –REG) to select: the I/O port address registers, the memory mapped port address registers, a Byte in the Card information structure and its configuration control and status registers. Same as PC Card Memory Mode Only A2 to A0 are used to select the one of eight registers in the Task File, the remaining lines should be grounded. The battery voltage status of the Card, as no battery is required it is asserted High. I/O 46 Alerts the host to changes in the READY and Write Protect states. Its use is controlled by the Card Configuration and Status Register. The Pass Diagnostic signal in the Master/Slave handshake protocol. The battery voltage status of the Card, as no battery is required it is asserted High. I/O 45 The Binary Audio output from the Card. It is asserted High as audio functions are not supported. This input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. Signal Name A10 to A0 (PC Card Memory Mode) A10 to A0 (PC Card I/O Mode) A2 to A0 (True IDE Mode) BVD1 (PC Card Memory Mode) –STSCHG (PC Card I/O Mode) –PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) –SPKR (PC Card I/O Mode) –DASP (True IDE Mode) I 8,10,11,12, 14,15,16,17, 18,19,20 17/91 Electrical interface Table 9. Signal Description (continued) Dir. Pin Description SMCxxxBF Signal Name D15-D00 (PC Card Memory Mode) D15-D00 (PC Card I/O Mode) D15-D00 (True IDE Mode) GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) –INPACK (PC Card Memory Mode) I/O 31,30,29,28, 27,49,48,47, 6,5,4,3,2, 23,22,21 Carry the Data, Commands and Status information between the host and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word. Same as PC Card Memory Mode. All Task File operations occur in Byte mode on D00 to D07 while all data transfers are 16 bit using D00 to D15. Ground. 1,50 Same for all modes. Same for all modes. Not used, should not be connected to the host. The Input Acknowledge is asserted when the Card is selected and responding to an I/O read cycle at the current address on the bus. It is used by the host to control the enable of any input data buffers between the Card and CPU. The DMARQ input signal is used to request a DMA data transfer between the host and the Card. It is asserted to notify that the Card is ready to transfer data to or from the host. For Multi-Word DMA transfers, the direction of data transfer is controlled by -IORD and -IOWR. DMARQ is used in conjunction with –DMACK to perform handshaking: the Card waits until –DMACK has been asserted by the host to de-assert DMARQ, and re-assert it again if there is still data to be transferred (see Section 10.10). DMARQ is not driven when the Card is not selected. If the host does not support DMA mode, DMARQ should be left unconnected. Not used. –INPACK (PC Card I/O Mode) O 43 DMARQ (True IDE Mode) –IORD (PC Card Memory Mode) –IORD (PC Card I/O Mode) –IORD (True IDE Mode) I 34 I/O Read strobe generated by the host. It gates I/O data onto the bus. Same as PC Card I/O Mode. 18/91 SMCxxxBF Table 9. Signal Description (continued) Dir. Pin Description Electrical interface Signal Name –CD1, –CD2 (PC Card Memory Mode) –CD1, –CD2 (PC Card I/O Mode) –CD1, –CD2 (True IDE Mode) These are connected to ground on the Card. They are used by the host to determine that the Card is fully inserted into its socket. O 26,25 Same for all modes. Same for all modes. Used to select the Card and to indicate whether a Byte or a Word operation is being performed. –CE2 accesses the odd Byte, –CE1 accesses the even Byte or the odd Byte depending on A0 and –CE2. A multiplexing scheme based on A0, –CE1, –CE2 allows 8 bit hosts to access all data on D0 to D7. I 7,32 Same as PC Card Memory Mode. –CS0 is the chip select for the task file registers, while –CS1 selects the Alternate Status Register and the Device Control Register. When –DMACK is asserted, -CS0 and –CS1 must be deasserted and data width is 16 bits. Not used. I 39 Not used. This internally pulled up signal is used to configure the Card as a Master or Slave. When grounded it is configured as a Master, when open it is configured as a Slave. Not used. The I/O Write strobe pulse is used to clock I/O data on the bus into the Card controller registers. Clocking occurs on the rising edge. Same as PC Card I/O Mode. This is an Output Enable strobe generated by the host interface. It reads data and the CIS and configuration registers. I 9 Reads the CIS and configuration registers. This input signal must be driven Low to enable True IDE mode. –CE1, –CE2 (PC Card Memory Mode) –CE1, –CE2 (PC Card I/O Mode) –CS0, –CS1 (True IDE Mode) –CSEL (PC Card Memory Mode) –CSEL (PC Card I/O Mode) –CSEL (True IDE Mode) –IOWR (PC Card Memory Mode) –IOWR (PC Card I/O Mode) –IOWR (True IDE Mode) –OE (PC Card Memory Mode) –OE (PC Card I/O Mode) –ATASEL (True IDE Mode) I 35 19/91 Electrical interface Table 9. Signal Description (continued) Dir. Pin Description SMCxxxBF Signal Name READY (PC Card Memory Mode) O –IREQ (PC Card I/O Mode) INTRQ (True IDE Mode) –REG (PC Card Memory Mode) –REG (PC Card I/O Mode) I –DMACK (True IDE Mode) 44 37 Indicates whether the Card is busy (Low), or ready to accept a new data transfer operation (High). The Host socket must provide a pull-up resistor. At power up and Reset, the READY signal is held Low until the commands are completed. No access should be made during this time. The READY signal is held High whenever the Card has been powered up with RESET continuously disconnected or asserted. Interrupt Request. It is strobed Low to generate a pulse mode interrupt or held Low for a level mode interrupt. Active High Interrupt Request to the host. Used to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. Must be Low during I/O Cycles when the I/O address is on the Bus. The –DMACK input signal is used to acknowledge DMA transfers. It is asserted by the host in response to DMARQ to initiate the transfer. When DMA mode is disabled, the Card should ignore the -DMACK signal. If the host does not support DMA mode, but only True IDE mode, this signal should be driven High or tied to VCC by the host. RESET (PC Card Memory Mode) RESET (PC Card I/O Mode) –RESET (True IDE Mode) VCC (PC Card Memory Mode) VCC (PC Card I/O Mode) VCC (True IDE Mode) 13,38 I 41 Resets the Card (active High). The Card is Reset at power up only if this pin is left High or unconnected. Same as PC Card Memory Mode. Hardware Reset from the host (active Low). +5V, +3.3V power. Same for all modes. Same for all modes. 20/91 SMCxxxBF Table 9. Signal Description (continued) Dir. Pin Description Electrical interface Signal Name –VS1, –VS2 (PC Card Memory Mode) –VS1, –VS2 (PC Card I/O Mode) –VS1, –VS2 (True IDE Mode) –WAIT (PC Card Memory Mode) –WAIT (PC Card I/O Mode) IORDY (True IDE Mode) –WE (PC Card Memory Mode) –WE (PC Card I/O Mode) –WE (True IDE Mode) WP (PC Card Memory Mode) –IOIS16 (PC Card I/O Mode) –IOCS16 (True IDE Mode) Voltage Sense Signals.–VS1 is grounded so that the CIS can be read at 3.3 volts and –VS2 is reserved by PCMCIA for a secondary voltage. O 33,40 Same for all modes. Same for all modes. O 42 Numonyx CF does not assert the WAIT (IORDY) signal Driven by the host to strobe memory write data to the registers. I 36 Used for writing to the configuration registers. Not used, should be connected to VCC by the host. No write protect switch available. It is held Low after the completion of the reset initialization sequence. O 24 Used for the 16 bit Port (–IOIS16) function. Low indicates that a 16 bit or odd Byte only operation can be performed at the addressed port. Asserted Low when the Card is expecting a Word data transfer cycle. 21/91 Electrical interface SMCxxxBF 4.2 Electrical Specification Table 10 defines the DC Characteristics for the CompactFlash Memory Card. Unless otherwise stated, conditions are: ● ● ● VCC = 5V ± 10% VCC = 3.3V ± 5% -40 °C to 85 °C Table 11 shows that the Card operates correctly in both the voltage ranges and that the current requirements must not exceed the maximum limit shown. Table 10. Absolute Maximum Conditions Parameter Input Power Voltage on any pin except VCC with respect to GND Symbol VCC V Conditions − 0.3V to 6.5V − 0.5V to VCC + 0.5V Table 11. Input Power Maximum Average RMS Current 85 100 Measurement Conditions − 40 +85 °C − 40 +85°C Voltage 3.3V ± 5% 5V ± 10% 4.3 Current Measurement The current is measured by connecting an amp meter in series with the VCC supply. The meter should be set to the 2A scale range, and have a fast current probe with an RC filter with a time constant of 0.1ms. Current measurements are taken while looping on a data transfer command with a sector count of 128. Current consumption values for both read and write commands are not to exceed the Maximum Average RMS Current specified in Table 11 Table 12 shows the Input Leakage Current, Table 11 the Input Characteristics, Table 13 the Output Drive Type and Table 15 the Output Drive Characteristics. Table 12. Type IxZ IxU IxD Input Leakage Current(1) Parameter Input Leakage Current Pull Up Resistor Pull Down Resistor Symbol IL RPU1 RPD1 Conditions VIH = VCC VIL = GND VCC = 5.0V VCC = 5.0V Min. −1 50 50 Typ. Max. 1 500 500 Units µA kΩ kΩ 1. x refers to the characteristics described in Table 13 For example, I1U indicates a pull up resistor with a type 1 input characteristic. 22/91 SMCxxxBF Table 13. Type Electrical interface Input Characteristics Min. Parameter Symbol VCC = 3.3V 1 Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger VIH VIL VIH VIL VTH VTL 1.8 1.0 1.5 0.6 2.8 V 2.0 2.4 0.6 2.0 V 0.8 3.3 V 0.8 VCC = 5.0V Typ. Max. Min. Typ. Max. Units 2 3 Table 14. Output Drive Type(1) Output Type Totempole Tri-State N-P Channel P-Channel Only N-Channel Only Valid Conditions IOH & IOL IOH & IOL IOH Only IOL Only Type OTx OZx OPx ONx 1. x refers to the characteristics described in Table 15 For example, OT3 refers to totem pole output with a type 3 output drive characteristic. Table 15. Type 1 Output Drive Characteristics Parameter Output Voltage Symbol VOH VOL Conditions IOH = -4mA IOL = 4mA IOH = -4mA IOL = 4mA IOH = -4mA IOL = 4mA VOL = Gnd VOH = VCC –10 VCC −0.8V Gnd + 0.4V 10 μA VCC −0.8V Gnd + 0.4V V Min. VCC −0.8V Gnd + 0.4V V Typ. Max. Units V 2 Output Voltage VOH VOL 3 Output Voltage Tri-State Leakage Current VOH VOL X IOZ 4.4 Additional requirements for CompactFlash Advanced Timing mode When operating in a CompactFlash Advanced timing mode, the following conditions must be respected: ● ● ● Only one CompactFlash Card must be connected to the CompactFlash bus. The load capacitance (cable included) for all signals must be lower than 40pF. The cable length must be lower than 0.15m (6inches). The cable length is measured from the Card connector to the host controller. 0.46m (18inches) cables are not supported. 23/91 Command Interface SMCxxxBF 5 Command Interface There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, direct mapped I/O transfer and memory access. Two types of bus cycles are also available in True IDE interface type: PIO transfer and Multi-Word DMA transfer. Table 16, Table 17, Table 18, Table 19, Table 20, Table 21 and Table 22 show the read and write timing parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure and Figure 8 show the read and write timing diagrams. In order to set the card mode, the -OE (-ATASEL) signal must be set and kept stable before applying VCC until the reset phase is completed. To place the card in Memory mode or I/O mode, -OE(-ATASEL) must be driven High, while it must be driven Low to place the card in True IDE mode. 5.1 Figure 2. Attribute Memory Read and Write Attribute Memory Read waveforms tc(R) Address Inputs ta(A) –REG tsu(A) ta(CE) –CE2/–CE1 ta(OE) ten(CE) –OE ten(OE) D0 to D15 (DOUT) VALID AI10080 VALID tv(A) tdis(CE) tdis(OE) 1. DOUT signifies data provided by the CompactFlash Memory Card to the system. The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations. Table 16. Attribute Memory Read timing Speed Version 300ns Parameter Read Cycle Time Address Access Time CE Access Time Min 300 300 300 Max Unit ns ns ns Symbol tc(R) ta(A) ta(CE) IEEE Symbol tAVAV tAVQV tELQV 24/91 SMCxxxBF Table 16. Attribute Memory Read timing (continued) Speed Version Symbol ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) IEEE Symbol tGLQV tEHQZ tGHQZ tELQNZ tGLQNZ tAXQX tAVGL Parameter OE Access Time Output Disable Time from CE Output Disable Time from OE Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change Address Setup Time 5 5 0 30 Min Command Interface 300ns Max 150 100 100 Unit ns ns ns ns ns ns ns Figure 3. Configuration Register (Attribute Memory) Write waveforms tc(W) –REG Address Inputs tsu(A) –WE VALID tw(WE) trec(WE) tsu(D-WEH) –CE2/–CE1 th(D) –OE D0 to D15 (DIN) DATA IN VALID AI10081 1. DIN signifies data provided by the system to the CompactFlash Card. Table 17. Configuration Register (Attribute Memory) Write timing Speed Version 250ns Parameter Write Cycle Time Write Pulse Width Address Setup Time Data Setup Time from WE Data Hold Time Write Recovery Time Min 250 150 30 80 30 30 Max Unit ns ns ns ns ns ns Symbol tc(W) tw(WE) tsu(A) tsu(D-WEH) th(D) trec(WE) IEEE Symbol tAVAV tWLWH tAVWL tDVWH tWMDX tWMAX 25/91 Command Interface SMCxxxBF 5.2 Figure 4. Common Memory Read and Write Common Memory Read waveforms VALID tsu(A) –REG th(CE) –CE2/–CE1 tsu(CE) –OE tv(WT) tdis(OE) VALID AI10083b Address Inputs th(A) ta(OE) D0 to D15 (DOUT) 1. DOUT means data provided by the CompactFlash Memory Card to the system. Table 18. Common Memory Read timing(1) Cycle Time Mode 250ns Min Max 125 100 30 20 0 20 15 15 0 15 120ns Min 100ns 80ns Unit Parameter Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup Time CE Hold Time Max Min Max 60 60 10 15 0 15 50 50 10 10 0 10 Min Max 45 45 ns ns ns ns ns ns Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH 1. Numonyx CF does not assert the WAIT signal. 26/91 SMCxxxBF Figure 5. Common Memory Write waveforms VALID tsu(A) –REG tsu(CE) –CE2/–CE1 tw(WE) –WE tsu(D-WEH) D0 to D15 (DIN) th(D) th(CE) th(A) Command Interface Address Inputs trec(WE) DATA IN VALID AI10082b 1. DIN signifies data provided by the system to the CompactFlash Memory Card. Table 19. Common Memory Write timing(1) Cycle Time Mode 250ns Min 80 30 150 30 0 30 20 20 Max 120ns Min 50 15 70 15 0 15 15 15 Max 100ns Min 40 10 60 10 0 15 15 15 Max 80ns Unit Parameter Data Setup Time from WE Data Hold Time WE Pulse Width Address Setup Time CE Setup Time before WE Write Recovery Time Address Hold Time CE Hold following WE Min 30 10 55 10 0 15 10 10 Max ns ns ns ns ns ns ns ns Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(A) th(CE) IEEE Symbol tDVWH tWMDX tWLWH tAVGL tELWL tWMAX tGHAX tGHEH 1. Numonyx CF does not assert the WAIT signal. 27/91 Command Interface SMCxxxBF 5.3 Figure 6. I/O Read and Write I/O Read waveforms VALID tsuREG(IORD) –REG tsuCE(IORD) –CE2/–CE1 tsuA(IORD) –IORD td(IORD) –INPACK tdfIOIS16(ADR) –IOIS16 th(IORD) D0 to D15 VALID AI10084b Address Inputs thA(IORD) thREG(IORD) tw(IORD) thCE(IORD) tdrINPACK(IORD) tdfINPACK(IORD) tdrIOIS16(ADR) 1. DOUT signifies data provided by the CompactFlash Memory Card or to the system. Table 20. I/O Read timing(1) Cycle Time Mode 250ns Parameter Data Delay after IORD Data Hold IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD 0 165 70 20 5 20 5 0 0 45 45 120ns 100ns 80ns Unit Min Max Min Max Min Max Min Max 100 5 70 25 10 5 10 5 0 0 NA (2) Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) IEEE Symbol tIGLQV tIGHQX tIGLIGH tAVIGL tIGHAX tELIGL tIGHEH tRGLIGL 50 5 65 25 10 5 10 5 0 0 50 5 55 15 10 5 10 5 0 NA (2) 45 ns ns ns ns ns ns ns ns ns tIGHRGH REG Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD tdfINPACK(IORD) tIGLIAL tdrINPACK(IORD) tIGHIAH 0 NA (2) ns ns NA (2) NA (2) NA (2) 28/91 SMCxxxBF Table 20. I/O Read timing(1) (continued) Cycle Time Mode Symbol tdfIOIS16(A) tdrIOIS16(A) IEEE Symbol tAVISL tAVISH Parameter IOIS16 delay falling from Address IOIS16 delay rising from Address 250ns 120ns Command Interface 100ns 80ns Unit Min Max Min Max Min Max Min Max 35 35 ns ns ns ns 1. Numonyx CF does not assert the WAIT signal. 2. -IOIS16 is not supported in this mode. Figure 7. I/O Write waveforms VALID tsuREG(IOWR) thREG(IOWR) –REG tsuCE(IOWR) thCE(IOWR) thA(IOWR) Address Inputs –CE2/–CE1 tsuA(IOWR) –IOWR tdfIOIS16(ADR) –IOIS16 tdrIOIS16(ADR) tw(IOWR) tsu(IOWR) D0 to D15 (DIN) DIN VALID th(IOWR) AI10085b 1. DIN signifies data provided by the system to the CompactFlash Memory Card. 2. -IOIS16 and -INPACK are not supported in this mode. 3. Table 21. I/O Write timing(1) Cycle Time Mode 250ns 120ns 100ns 80ns Unit Parameter Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR Min Max Min Max Min Max Min Max 60 30 165 70 20 5 20 10 70 25 20 5 20 5 65 25 10 5 15 5 55 15 10 5 ns ns ns ns ns ns Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) IEEE Symbol tQVIWH tIWHQX tIWLIWH tAVIWL tIWHAX tELIWL 29/91 Command Interface Table 21. I/O Write timing(1) (continued) Cycle Time Mode Symbol thCE(IOWR) IEEE Symbol tIWHEH Parameter CE Hold following IOWR REG Setup before IOWR 250ns 120ns 100ns SMCxxxBF 80ns Unit Min Max Min Max Min Max Min Max 20 5 0 35 35 20 5 0 NA (2) 10 5 0 NA (2) 10 5 0 NA (2) ns ns ns tsuREG(IOWR) tRGLIWL thREG(IOWR) tdfIOIS16(A) tdrIOIS16(A) tIWHRGH REG Hold following IOWR tAVISL tAVISH IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address NA (2) NA (2) NA (2) 1. Numonyx CF does not assert the WAIT signal. 2. -IOIS16 is not supported in this mode. 5.4 True IDE mode The timing waveforms for True IDE mode and True IDE DMA mode of operation in this section are drawn using the conventions in the ATA-4 specification, which are different than the conventions used in the PCMCIA specification and earlier versions of this specification. Signals are shown with their asserted state as High regardless of whether the signal is actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus. Figure 8. True IDE PIO mode Read/Write waveforms t0 A0-A2, -CS0, -CS1(1) t1 -IORD/-IOWR t2i Write Data D0-D15(2) t3 Read Data D0-D15(2) t5 t7 -IOCS16(3) VALID t6 t6z VALID t4 ADDRESS VALID t2 t9 t8 ai10086b 1. The device addresses consists of − CS0, − CS1, and A2-A0. 2. The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit). 3. − IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored. 30/91 SMCxxxBF Table 22. Symbol t0(2) t1 t2(2) t2(2) t2i(2) t3 t4 t5 t6 t6Z(3) t7(4) t8(4) t9 Command Interface True IDE PIO mode Read/Write timing (1) Parameter Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Unit 600 70 165 290 60 30 50 5 30 90 60 20 383 50 125 290 45 20 35 5 30 50 45 15 240 30 100 290 30 15 20 5 30 40 30 10 180 30 80 80 70 30 10 20 5 30 NA NA 10 120 25 70 70 25 20 10 20 5 30 NA NA 10 100 15 65 65 25 20 5 15 5 20 NA NA 10 80 10 55 55 20 15 5 10 5 20 NA NA 10 ns ns ns ns ns ns ns ns ns ns ns ns ns Cycle time (min) Address Valid to -IORD/-IOWR setup (min) -IORD/-IOWR (min) -IORD/-IOWR (min) Register (8 bit) -IORD/-IOWR recovery time (min) -IOWR data setup (min) -IOWR data hold (min) -IORD data setup (min) -IORD data hold (min) -IORD data tri-state (max) Address valid to -IOCS16 assertion (max) Address valid to -IOCS16 released (max) -IORD/-IOWR to address valid hold 1. The maximum load on -IOCS16 is 1 LSTTL with a 50pF total load. 2. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i have to be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device's identify drive data. A CompactFlash Memory Card implementation should support any legal host implementation. 3. This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by the CompactFlash Memory Card (tri-state). 4. t7 and t8 apply only to modes 0, 1 and 2. The -IOCS16 signal is not valid for other modes. 31/91 Command Interface Figure 9. True IDE Multi-Word DMA Mode Read/Write waveforms tM -CS0, -CS1 tLW, tLR -DMARQ tI -DMACK tE -IORD/-IOWR tF Read Data D0-D15 tG Write Data D0-D15 VALID VALID tH VALID tZ VALID tD tKW tKR tJ t0 tN SMCxxxBF ai13117 Table 23. Symbol t0(1) tD(1) tE tF tG tH tI tJ tKR(1) tKW(1) tLR tLW tM tN tZ True IDE Multi-Word DMA Mode Read/Write timing Parameter Cycle time (min) -IORD / -IOWR asserted width (min) -IORD data access (max) -IORD data hold (min) -IORD/-IOWR data setup (min) -IOWR data hold (min) DMACK to –IORD/-IOWR setup (min) -IORD / -IOWR to -DMACK hold (min) -IORD Low width (min) -IOWR Low width (min) -IORD to DMARQ delay (max) -IOWR to DMARQ delay (max) CS(1:0) valid to –IORD / -IOWR CS(1:0) hold -DMACK Mode 0 480 215 150 5 100 20 0 20 50 215 120 40 50 15 20 Mode 1 150 80 60 5 30 15 0 5 50 50 40 40 30 10 25 Mode 2 120 70 50 5 20 10 0 5 25 25 35 35 25 10 25 Mode 3 100 65 50 5 15 5 0 5 25 25 35 35 10 10 25 Mode 4 80 55 45 5 10 5 0 5 20 20 35 35 5 10 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. t0 is the minimum total cycle time. tD is the minimum command active time. tKR and tKW are the minimum command recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the actual command active time and the actual command inactive time. The timing requirements of t0, tD, tKR, and tKW must be respected. t0 is higher than tD + tKR or tD + tKW, for input and output cycles respectively. This means the host can lengthen either tD or tKR/tKW, or both, to ensure that t0 is equal to or higher than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall support any legal host implementation. 32/91 SMCxxxBF Card Configuration 6 Card Configuration The CompactFlash Memory Card is identified by information in the Card Information Structure (CIS). The Card has four configuration registers (Table 24 and Table 25). ● ● ● ● Configuration Option Register Pin Replacement Register Card Configuration and Status Register Socket and Copy Register They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, in I/O Card mode these registers provide a method for accessing status information that would normally appear on dedicated pins in Memory Card mode. The base address of the card configuration registers is 200h in the Attribute Memory space. No write operation should be performed to the attribute memory area except for the configuration register addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute Memory Function. Table 24. CompactFlash Memory Card Registers and Memory Space Decoding –REG X 0 1 1 1 0 1 1 1 0 0 0 0 0 0 –OE –WE A10 A9 A8-A4 A3 A2 A1 A0 X 0 0 0 0 1 1 1 1 0 1 0 1 0 1 X 1 1 1 1 0 0 0 0 1 0 1 0 1 0 X 0 X X X 0 X X X 0 0 X X X X X 1 X X X 1 X X X 0 0 X X X X XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 X X 0 0 X X 0 0 0 1 1 X X Selected Space Standby Configuration Registers Read Common Memory Read (D7 to D0) Common Memory Read (D15 to D8) Common Memory Read (D15 to D0) Configuration Registers Write Common Memory Write (D7 to D0) Common Memory Write (D15 to D8) Common Memory Write (D15 to D0) Card Information Structure Read Invalid Access (CIS Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) –CE2 –CE1 1 X 1 0 0 X 1 0 0 X 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 33/91 Card Configuration Table 25. CompactFlash Memory Card Configuration Registers Decoding A10 0 0 0 0 0 0 0 0 A9 1 1 1 1 1 1 1 1 A8A4 00 00 00 00 00 00 00 00 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 SMCxxxBF –CE2 –CE1 –REG –OE –WE X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Selected Register Configuration Option Register Read Configuration Option Register Write Card Status Register Read Card Status Register Write Pin Replacement Register Read Pin Replacement Register Write Socket and Copy Register Read Socket and Copy Register Write 6.1 Configuration Option Register (200h in Attribute Memory) The Configuration Option Register is used to configure the Card’s interface, address decoding and interrupt to the Card (see Table 26). 6.1.1 SRESET Setting the SRESET bit to ‘1’ and returning the bit ‘0’ places the CompactFlash Storage Card in the Reset state. Setting this bit to ‘1’ is equivalent to asserting the RESET signal except that the SRESET bit is not cleared. Returning the SRESET bit to ‘0’ leaves the CompactFlash Storage Card in the same un-configured Reset state as after a power-up and hardware reset. This bit is set to ‘0’ at power-up and taking the Card through a hardware reset. 6.1.2 LevlREQ This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to zero (0) after Power Up. 6.1.3 Conf5 - Conf0 (Configuration Index) These bits are used to select the operation mode of the Card as shown in Table 27. This bit is set to ‘0’ after Power Up. Table 26. Operation R/W Configuration Option Register (default value: 00h) D7 SRESET D6 LevlREQ D5 Conf5 D4 Conf4 D3 Conf3 D2 Conf2 D1 Conf1 D0 Conf0 34/91 SMCxxxBF Table 27. CompactFlash Memory Card Configurations Conf3 0 0 0 0 Conf2 0 0 0 0 Conf1 0 0 1 1 Conf0 0 1 0 1 Mapping Mode Memory Contiguous I/O Primary I/O Secondary I/O Card Mode Memory I/O I/O I/O Card Configuration Conf5 Conf4 0 0 0 0 0 0 0 0 Task File Register Address 0h - Fh, 400h - 7FFh xx0h - xxFh 1F0h - 1F7h, 3F6h - 3F7h 170h - 177h, 376h - 377h 6.2 Card Configuration and Status Register (202h in Attribute Memory) The Card Configuration and Status Register contains information about the Card’s status (see Table 28). 6.2.1 Changed Indicates that one or both of the Pin Replacement register (CRDY, or CWProt) bits are set to ‘1’. When the Changed bit is set, –STSCHG (Pin 46) is held Low and if the SigChg bit is ‘1’ the Card is configured for the I/O interface. 6.2.2 SigChg This bit is set and reset by the host to enable and disable a state-change signal from the Status Register (issued on Status Changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the Card is configured for I/O. 6.2.3 IOis8 The host sets this bit to ‘1’ if the Card is to be configured in 8 bit I/O Mode. The Card is always configured for both 8 and 16 bit I/O, so this bit is ignored. 6.2.4 PwrDwn This bit indicates whether the Card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’, the Card enters power down mode. When set to ‘0’, the Card enters active mode. The READY value on Pin Replacement Register becomes BUSY when this bit is changed. READY will not become Ready until the power state requested has been entered. The Card automatically powers down when it is idle and powers back up when it receives a command. 6.2.5 Int This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has been configured. It remains valid until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device Control Register, this bit is ‘0’. 35/91 Card Configuration Table 28. Operation Read Write SMCxxxBF Card Configuration and Status Register (default value: 00h) D7 Changed 0 D6 SigChg SigChg D5 IOIS8 IOIS8 D4 0 0 D3 0 0 D2 PwrDwn PwrDwn D1 Int 0 D0 0 0 6.3 Pin Replacement Register (204h in Attribute Memory) This register contains information on the state of the READY signal when configured in memory mode and the IREQ signal in I/O mode. See Table 29 and Table 30. 6.3.1 CReady This bit is set to ‘1’ when the bit RReady changes state. This bit can also be written by the host. 6.3.2 CWProt This bit is set to '1' when the bit RWProt changes state. This bit can also be written by the host. 6.3.3 RReady This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request. When written, this bit acts as a mask (MReady) for writing the corresponding bit CReady. 6.3.4 WProt This bit is always ‘0’ since the CompactFlash Memory Card does not have a Write Protect switch. When written, this bit acts as a mask for writing the corresponding CWProt bit. 6.3.5 MReady This bit acts as a mask for writing the corresponding CReady bit. 6.3.6 MWProt This bit when written acts as a mask for writing the corresponding CWProt bit. Table 29. Operation Read Write Pin Replacement Register (default value: 0Ch) D7 0 0 D6 0 0 D5 CReady CReady D4 CWProt CWProt D3 1 0 D2 1 0 D1 RReady RReady D0 WProt MWProt 36/91 SMCxxxBF Table 30. Pin Replacement Changed Bit/Mask Bit Values Written by Host Final ‘C’ Bit ‘C’ Bit X X 0 1 ‘M’ Bit 0 0 1 1 0 1 0 1 Card Configuration Initial Value of ‘C’ Status 0 1 X X Comments Unchanged Unchanged Cleared by Host Set by Host 6.4 Socket and Copy Register (206h in Attribute Memory) This register contains additional configuration information which identifies the Card from other cards. This register is always written by the system before writing the Configuration Option Register (see Table 31). 6.4.1 Drive # This value can be used to address two different cards in the case of twin card configuration. 6.4.2 X The socket number is ignored by the Card. Table 31. Operation Read Write Socket and Copy Register (default value: 00h) D7 Reserved 0 D6 0 0 D5 0 0 D4 Drive # Drive # D3 0 X D2 0 X D1 0 X D0 0 X 37/91 Card Configuration SMCxxxBF 6.5 Attribute Memory Function Attribute memory is a space where identification and configuration information are stored. Only 8 bit wide accesses at even addresses can be performed in this area. The Card configuration registers are also located in the Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation. For the Attribute Memory Read function, signals –REG and –OE must be active and –WE inactive during the cycle. As in the Main Memory Read functions, the signals –CE1 and – CE2 control the even and odd Byte address, but only the even Byte data is valid during the Attribute Memory access. Refer to Table 32 for signal states and bus validity. Table 32. Attribute Memory Function –REG X L L –CE2 (1) Function Mode Standby Read Byte Access CIS (8 bits) Write Byte Access CIS (8 bits) Invalid Read Byte Access Configuration (8 bits) Write Byte Access Configuration (8 bits) Read Word Access CIS (16 bits) Write Word Access CIS (16 bits) Invalid Read Word Access Configuration (16 bits) Write Word Access Configuration (16 bits) –CE1 (1) A10 X L L A9 X L L A0 X L L –OE (1) –WE (1) D15 to D8 High-Z High-Z D7 to D0 High-Z Even Byte H H H H L L X L H X H L Don’t Care Even Byte L H L L H L L H High-Z Even Byte L H L L H L H L Don’t Care Even Byte L L L L L L L L L L L L L L L L L L H H X X X X L H L H H L H L Not Valid Even Byte Don’t Care Even Byte Not Valid Even Byte Don’t Care Even Byte 1. The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations. 38/91 SMCxxxBF Card Configuration 6.6 I/O Transfer Function The I/O transfer to or from the Card can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the –IOIS16 signal is asserted by the Card, otherwise it is de-asserted. When a 16 bit transfer is attempted, and the –IOIS16 signal is not asserted, the system must generate a pair of 8 bit references to access the Word’s even and odd Bytes. The Card permits both 8 and 16 bit accesses to all of its I/O addresses, so –IOIS16 is asserted for all addresses (see Table 33). Table 33. . I/O Function –REG –CE2 X L L L L L L H H L H H H H H L L X X L –CE1 A0 H L L L L L L X X H X L H L H L L X X X –IORD X L L H H L H L H L –IOWR X H H L L H L H L H D15 to D8 High Z High Z High Z Don’t Care Don’t Care Odd Byte Odd Byte Don’t Care High Z Odd Byte D7 to D0 High Z Even Byte Odd Byte Even Byte Odd Byte Even Byte Even Byte Don’t Care High Z High Z Function Code Standby Mode Byte Input Access (8 bits) Byte Output Access (8 bits) Word Input Access (16 bits) Word Output Access (16 bits) I/O Read Inhibit I/O Write Inhibit High Byte Input Only (8 bits) High Byte Output Only (8 bits) L L H X H L Odd Byte Don’t Care 39/91 Card Configuration SMCxxxBF 6.7 Common Memory Transfer Function The Common Memory transfer to or from the Card permits both 8 or 16 bit access to all of the Common Memory addresses. (see Table 34). Table 34. Common Memory Function –REG –CE2 X H H H H H H H H H H H L L L L –CE1 A0 H L L L L L L H H X L H L H X X X X X L L H H L H L H –OE X H H L L H L H L –WE D15 to D8 High Z High Z High Z Don’t Care Don’t Care Odd Byte Odd Byte Odd Byte Odd Byte D7 to D0 High Z Even Byte Odd Byte Even Byte Odd Byte Even Byte Even Byte High Z Don’t Care Function Code Standby Mode Byte Read Access (8 bits) Byte Write Access (8 bits) Word Read Access (16 bits) Word Write Access (16 bits) Odd Byte Read Only H (8 bits) Odd Byte Write Only H (8 bits) 6.8 True IDE Mode I/O Function The Card can be configured in a True IDE Mode of operation. It is configured in this mode only when the –OE signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. No Memory or Attribute Registers are accessible to the host. The Set Feature Command can be used to put the device in 8 bit Mode (see Table 35). Removing and reinserting the Card while the host computer’s power is on will reconfigure the Card to PC Card ATA mode. Table 35. True IDE Mode I/O Function –CS1 –CS0 Function Code A2 to A0 X X X X X X 1h-7h -DMACK X L L L L H H –IORD –IOWR D15 to D8 Undefined In/Out Undefined Out Undefined In Undefined Out Undefined In High Z Don’t Care D7 to D0 Undefined In/Out Undefined Out Undefined In Undefined Out Undefined In High Z Data In L L Invalid Mode L X X Standby Mode Task File Write H H L X X L L H L X L X L X X H X X L X L X L 40/91 SMCxxxBF Table 35. True IDE Mode I/O Function (continued) –CS1 –CS0 Card Configuration Function Code Task File Read PIO Data Register Write DMA Data Register Write PIO Data Register Read DMA Data Register Read Control Register Write Alternate Status Read Drive Address A2 to A0 1h-7h 0 X 0 X 6h 6h 7h -DMACK H H L H L H H H –IORD –IOWR D15 to D8 High Z Odd-Byte In Odd-Byte In Odd-Byte Out Odd-Byte Out Don’t Care High Z High Z D7 to D0 Data Out Even-Byte In Even-Byte In Even-Byte Out Even-Byte Out Control In Status Out Data Out H H H H H L L L L L L L H H H H L H H L L H L L H L L H H L H H 41/91 Host configuration requirements SMCxxxBF 7 Host configuration requirements The CompactFlash Advanced Timing modes include PCMCIA-style I/O modes that are faster than the original 250 ns cycle time (see Section 1: Summary description). Before configuring the Card interface for the I/O mode, the host must ensure that all the cards connected to a given electrical interface support I/O transfers faster than 250ns. These modes must be used in the conditions described in Section 4.4. In particular, the host can be connected to one card only. Consequently, the host must not configure a card to operate in an CompactFlash Advanced Timing mode if two cards are sharing the same I/O lines in Master/Slave operation, or if it is connected to the card through a cable which length exceeds 0.15m. 42/91 SMCxxxBF Software interface 8 8.1 Software interface CF-ATA Drive Register Set Definition and Protocol The CompactFlash Memory Card can be configured as a high performance I/O device through: ● Standard PC-AT disk I/O address spaces – – 1F0h-1F7h, 3F6h-3F7h (primary); 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). ● ● Any system decoded 16 Byte I/O block using any available IRQ. Memory space. Communication to or from the Card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 36 is a detailed description of these methods: Table 36. I/O Configurations Standards Configurations Config Index 0 1 2 3 I/O or Memory Memory I/O I/O I/O Address 0h-Fh, 400h-7FFh xx0h-xxFh 1F0-1F7h, 3F6h-3F7h 170-177h, 376h-377h Description Memory Mapped I/O Mapped 16 Continuous Registers Primary I/O Mapped Secondary I/O Mapped 8.2 Memory Mapped Addressing When the Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2KBytes as shown in Table 37 This window accesses the Data Register FIFO. It does not allow random access to the data buffer within the Card. Register 0 is accessed with –CE1 and –CE2 Low, as a Word register on the combined Odd and Even Data Bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to address 0 with –CE1 High and –CE2 Low accesses the Error (read) or Feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even then odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the data buffer. 43/91 Software interface SMCxxxBF Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 KByte memory window to the data register is provided so that hosts can perform memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory-to-memory block move instruction. Some PCMCIA socket adapters also have an embedded auto incrementing address logic. A Word access to address at offset 8 will provide even data on the least significant Byte of the data bus, along with odd data at offset 9 on the most significant Byte of the data bus. Table 37. –REG A10 Memory Mapped Decoding A9 to A4 X X X X X X X X X X X X X X X A3 A2 A1 A0 Offset 0 0 0 0 0 0 0 0 1 1 1 1 1 X X 0 0 0 0 1 1 1 1 0 0 1 1 1 X X 0 0 1 1 0 0 1 1 0 0 0 1 1 X X 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Dh Eh Fh 8h 9h –OE=0 –WE=0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Even Data Register Error Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Status Register Dup. Even Data Register Dup. Odd Data Register Dup. Error Register Alternate Status Register Drive Address Register Even Data Register Odd Data Register Even Data Register Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Command Register Dup. Even Data Register Dup. Odd Data Register Dup. Feature Register Device Control Register Reserved Even Data Register Odd Data Register 44/91 SMCxxxBF Software interface 8.3 Contiguous I/O Mapped Addressing When the system decodes a contiguous block of I/O registers to select the Card, the registers are accessed in the block of I/O space decoded by the system as shown in Table 38 As for the Memory Mapped Addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 don’t Care) as a Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even than odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the data buffer. Table 38. –REG Contiguous I/O Decoding A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Dh Eh Fh –IORD=0 –IOWR=0 A10 to A4 X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 Even Data Register Error Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Status Register Dup. Even Data Register Even Data Register Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Command Register Dup. Even Data Register Dup. Odd Data Register Dup. Odd Data Register Dup. Error Register Alternate Status Register Drive Address Register Dup. Feature Register Device Control Register Reserved 45/91 Software interface SMCxxxBF 8.4 I/O Primary and Secondary Address Configurations When the system decodes the Primary and Secondary Address Configurations, the registers are accessed in the block of I/O space as shown in Table 39 As for the Memory Mapped Addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 don’t Care) as a Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Table 39. –REG Primary and Secondary I/O Decoding A9 to A4 A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 –IORD=0 –IOWR=0 0 0 0 0 0 0 0 0 0 0 1F(17)h 1F(17)h 1F(17)h 1F(17)h 1F(17)h 1F(17)h 1F(17)h 1F(17)h 3F(37)h 3F(37)h Even Data Register Error Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Status Register Alternate Status Register Drive Address Register Even Data Register Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Select Card/Head Register Command Register Device Control Register Reserved 46/91 SMCxxxBF Software interface 8.5 True IDE Mode Addressing When the Card is configured in the True IDE Mode, the I/O decoding is as shown in Table 40 Table 40. –CS1 True IDE Mode I/O Decoding –CS0 A2 0 X 0 0 0 1 1 1 1 1 A1 0 X 0 1 1 0 0 1 1 1 A0 0 X 1 0 1 0 1 0 1 0 -DMACK 1 0 1 1 1 1 1 1 1 1 –IORD=0 –IOWR=0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 PIO RD Data DMA RD Data Error Register Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status PIO WR Data DMA WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Alt Status 47/91 CF-ATA registers SMCxxxBF 9 CF-ATA registers The following section describes the hardware registers used by the host software to issue commands to the Card. These registers are collectively referred to as the ‘task file’. In accordance with the PCMCIA specification, each register that is located at an odd offset address can be accessed in the PC Card Memory or PC Card I/O modes. The register can be addressed in two ways: ● ● Using the normal register address. Using the corresponding even address (normal address -1) when -CE1 is High and CE2 Low, unless -IOIS16 is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data bus lines D15-D8. In True IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit only except for the Data Register, which is normally 16 bits. However, they can be configured to be accessed in 8-bit mode for non-DMA operations, by using a Set Features command (see Section 10.17). 9.1 Data Register The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h. The Data Register is a 16 bit register used to transfer data blocks between the Card data buffer and the Host. This register overlaps the Error Register. Table 41 and Table 42 describes the combinations of Data register access and explains the overlapped Data and Error/Feature Registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for Word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed. Table 41. Data Register Access (Memory and I/O mode) Data Register Word Data Register Even Data Register Odd Data Register Odd Data Register –CE2 0 1 1 0 1 0 0 –CE1 0 0 0 1 0 1 0 A0 X 0 1 X 1 X X -REG(1) Offset 0h, 8h, 9h 0h, 8h 9h 8h, 9h 1h, Dh 1h Dh Data Bus D15 to D0 D7 to D0 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D15 to D8 Error/Feature Register Error/Feature Register Error/Feature Register 1. -REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in Memory Mode. 48/91 SMCxxxBF Table 42. Data Register Access (True IDE mode) Data Register PIO Word Data Register DMA Word Data Register PIO Byte Data Register (Selected Using Set Features Command) –CS1 1 1 1 –CS0 0 1 0 A0 0 X 0 -DMACK 1 0 1 CF-ATA registers Offset 0h X 0h Data Bus D15 to D0 D15 to D0 D7 to D0 9.2 Error Register The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh. This read only register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined in Table 43 This register is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and – CE1 High. 9.2.1 Bit 7 (BBK) This bit is set when a Bad Block is detected. 9.2.2 Bit 6 (UNC) This bit is set when an Uncorrectable Error is encountered. 9.2.3 Bit 5 This bit is ‘0’. 9.2.4 Bit 4 (IDNF) This bit is set if the requested sector ID is in error or cannot be found. 9.2.5 Bit 3 This bit is ‘0’. 9.2.6 Bit 2 (Abort) This bit is set if the command has been aborted because of a Card status condition (Not Ready, Write Fault, etc.) or when an invalid command has been issued. 9.2.7 Bit 1 This bit is ‘0’. 9.2.8 Bit 0 (AMNF) This bit is set when there is a general error. 49/91 CF-ATA registers Table 43. D7 BBK SMCxxxBF Error Register D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF 9.3 Feature Register The Feature register is a write-only register, located at address 1F1h [171h], offset 1h, Dh. This write-only register provides information on features that the host can utilize. It is accessed on data bits D15 to D8 during a write operation to Offset 0 with –CE2 Low and – CE1 High. 9.4 Sector Count Register The Sector Count register is located at address 1F2h [172h], offset 2h. This register contains the number of sectors of data to be transferred on a read or write operation between the host and Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. The default value is 01h. 9.5 Sector Number (LBA 7-0) Register The Sector Number register is located at address 1F3h [173h], offset 3h. This register contains the starting sector number or bits 7 to 0 of the Logical Block Address (LBA), for any data access for the subsequent sector transfer command. 9.6 Cylinder Low (LBA 15-8) Register The Cylinder Low register is located at address 1F4h [174h], offset 4h. This register contains the least significant 8 bits of the starting cylinder address or bits 15 to 8 of the Logical Block Address. 9.7 Cylinder High (LBA 23-16) Register The Cylinder High register is located at address 1F5h [175h], offset 5h. This register contains the most significant bits of the starting cylinder address or bits 23 to 16 of the Logical Block Address. 50/91 SMCxxxBF CF-ATA registers 9.8 Drive/Head (LBA 27-24) Register The Driver/Head register is located at address 1F6h [176h], offset 6h. The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined in Table 44 9.8.1 Bit 7 This bit is set to ‘1’. 9.8.2 Bit 6 (LBA) LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to’1’, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: ● ● ● ● LBA7-LBA0: Sector Number Register D7 to D0 LBA15-LBA8: Cylinder Low Register D7 to D0 LBA23-LBA16: Cylinder High Register D7 to D0 LBA27-LBA24: Drive/Head Register bits HS3 to HS0 9.8.3 Bit 5 This bit is set to ‘1’. 9.8.4 Bit 4 (DRV) DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (Master). When DRV is ‘1’, drive/card 1 is selected (Slave). The Card is set to Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register. 9.8.5 Bit 3 (HS3) When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical Block Address mode. 9.8.6 Bit 2 (HS2) When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the Logical Block Address mode. 9.8.7 Bit 1 (HS1) When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. 9.8.8 Bit 0 (HS0) When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. 51/91 CF-ATA registers Table 44. D7 1 SMCxxxBF Drive/Head Register D6 LBA D5 1 D4 DRV D3 HS3 D2 HS2 D1 HS1 D0 HS0 9.9 Status & Alternate Status Registers The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively. Offsets are 7h and Eh. These registers return the Card status when read by the host. Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status Register does not clear a pending interrupt. The Status Register should be accessed in Byte mode; in Word mode it is recommended that Alternate Status Register is used. The status bits are described as follows 9.9.1 Bit 7 (BUSY) The busy bit is set when only the Card can access the command register and buffer, The host is denied access. No other bits in this register are valid when this bit is set to ‘1’. 9.9.2 Bit 6 (RDY) This bit indicates whether the device is capable of performing CompactFlash Memory Card operations. This bit is cleared at power up and remains cleared until the Card is ready to accept a command. 9.9.3 Bit 5 (DWF) When set this bit indicates a Write Fault has occurred. 9.9.4 Bit 4 (DSC) This bit is set when the Card is ready. 9.9.5 Bit 3 (DRQ) The Data Request is set when the Card requires information be transferred either to or from the host through the Data register. The bit is cleared by the next command. 9.9.6 Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. 9.9.7 Bit 1 (IDX) This bit is always set to ‘0’. 52/91 SMCxxxBF CF-ATA registers 9.9.8 Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. In case of read or write access commands that end with an error, the address of the first sector with an error is in the command block registers. This bit is cleared by the next command. Table 45. D7 BUSY Status & Alternate Status Register D6 RDY D5 DWF D4 DSC D3 DRQ D2 CORR D1 0 D0 ERR 9.10 Device Control Register The Device COntrol register is located at address 3F6h [376h], offset Eh. This Write-only register is used to control the CompactFlash Memory Card interrupt request and to issue an ATA soft reset to the Card. This register can be written even if the device is BUSY. The bits are defined as follows: 9.10.1 Bit 7 to 3 Don’t care. The host should reset this bit to ‘0’. 9.10.2 Bit 2 (SW Rst) This bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This clears Status Register and writes Diagnostic Code in Error register after a Write or Read Sector error. The Card remains in Reset until this bit is reset to ‘0.’ 9.10.3 Bit 1 (–IEn) When the Interrupt Enable bit is set to ‘0’, –IREQ interrupts are enabled. When the bit is set to ‘1’, interrupts from the Card are disabled. This bit also controls the Int bit in the Card Configuration and Status Register. It is set to ‘0’ at Power On. 9.10.4 Bit 0 This bit is set to ‘0’. Table 46. D7 X(0) Device Control Register D6 X(0) D5 X(0) D4 X(0) D3 X(0) D2 SW Rst D1 –IEn D0 0 53/91 CF-ATA registers SMCxxxBF 9.11 Card (Drive) Address Register The Card (Drived) Address register is located at address 3F7h [377h], offset Fh. This read-only register is provided for compatibility with the AT disk drive interface and can be used for confirming the drive status. It is recommended that this register is not mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows: 9.11.1 Bit 7 This bit is don’t care. 9.11.2 Bit 6 (–WTG) This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’. 9.11.3 Bit 5 (–HS3) This bit is the negation of bit 3 in the Drive/Head register. 9.11.4 Bit 4 (–HS2) This bit is the negation of bit 2 in the Drive/Head register. 9.11.5 Bit 3 (–HS1) This bit is the negation of bit 1 in the Drive/Head register. 9.11.6 Bit 2 (–HS0) This bit is the negation of bit 0 in the Drive/Head register. 9.11.7 Bit 1 (–nDS1) This bit is ‘0’ when drive 1 is active and selected. 9.11.8 Bit 0 (–nDS0) This bit is ‘0’ when the drive 0 is active and selected. Table 47. D7 X Card (Drive) Address Register D6 –WTG D5 –HS3 D4 –HS2 D3 –HS1 D2 –HS0 D1 –nDS1 D0 –nDS0 54/91 SMCxxxBF CF-ATA command description 10 CF-ATA command description This section defines the software requirements and the format of the commands the Host sends to the Card. Commands are issued to the Card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. There are three classes of command acceptance, all dependent on the host not issuing commands unless the Card is not busy (BSY is ‘0’). ● ● Class 1:Upon receipt of a Class 1 command, the Card sets BSY within 400ns. Class 2:Upon receipt of a Class 2 command, the Card sets BSY within 400ns, sets up the sector buffer for a write operation, sets DRQ within 700µs, and clears BSY within 400ns of setting DRQ. Class 3:Upon receipt of a Class 3 command, the Card sets BSY within 400ns, sets up the sector buffer for a write operation, sets DRQ within 20ms (assuming no reassignments), and clears BSY within 400ns of setting DRQ. ● For reasons of backward compatibility some commands are implemented as ‘no operation’ NOP. Table 48 summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each. Table 48. Class 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CF-ATA Command Set(1) Command Check Power Mode Execute Drive Diagnostic Erase Sector(s) Identify Drive Idle Idle Immediate Initialize Drive Parameters NOP Read Buffer Read DMA Read Multiple Read Sector(s) Read Verify Sector(s) Recalibrate Request Sense Seek Set Features Set Multiple Mode Set Sleep Mode Code E5h or 98h 90h C0h ECh E3h or 97h E1h or 95h 91h 00h E4h C8 C4h 20h or 21h 40h or 41h 1Xh 03h 7Xh EFh C6h E6h or 99h Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y FR SC SN CY DH D YD Y D D D Y D D Y Y Y Y D D Y D D D Y Y Y Y Y Y LBA 55/91 CF-ATA command description Table 48. Class 1 1 1 1 2 2 3 3 2 2 3 SMCxxxBF CF-ATA Command Set(1) (continued) Command Stand By Stand By Immediate Translate Sector Wear Level Write Buffer Write DMA Write Multiple Write Multiple w/o Erase Write Sector(s) Write Sector(s) w/o Erase Write Verify Code E2h or 96h E0h or 94h 87h F5h E8h CA C5h CDh 30h or 31h 38h 3Ch Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y FR SC SN CY DH D D Y Y D Y Y Y Y Y Y Y Y Y Y Y Y Y LBA 1. FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder Registers, DH = Card/Drive/Head Register, LBA = Logical Block Address Mode Supported (see command descriptions for use), Y - The register contains a valid parameter for this command. For the Drive/Head Register Y means both the Compact Flash Memory Card and head parameters are used. D - only the Compact Flash Memory Card parameter is valid and not the head parameter C - the register contains command specific data (see command descriptors for use). 10.1 Check Power Mode (98h or E5h) This command checks the power mode. Issuing the command while the Card is in Standby mode, is about to enter Standby, or is exiting Standby, the command will set BSY, set the Sector Count Register to 00h, clear BSY and generate an interrupt. Issuing the command when the Card is in Idle mode will set BSY, set the Sector Count Register to FFh, clear BSY and generate an interrupt. Table 49 defines the Byte sequence of the Check Power Mode command. Table 49. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Check Power Mode 7 6 5 4 3 2 1 0 98h or E5h Drive X X X X X X 56/91 SMCxxxBF CF-ATA command description 10.2 Execute Drive Diagnostic (90h) This command performs the internal diagnostic tests implemented by the Card. In PCMCIA configuration, this command only runs on the Card which is addressed by the Drive/Head register when the command is issued. This is because PCMCIA Card interface does not allow for direct inter-drive communication. In True IDE Mode, the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with the status for both devices. Table 50 defines the Execute Drive Diagnostic command Byte sequence. The Diagnostic codes shown in Table 51 are returned in the Error Register at the end of the command. Table 50. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X X X Execute Drive Diagnostic 7 6 5 4 90h X 3 2 1 0 Table 51. Diagnostic Codes Code 01h 02h 03h 04h 05h 8Xh Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Error in True IDE Mode 57/91 CF-ATA command description SMCxxxBF 10.3 Erase Sector(s) (C0h) This command is used to pre-erase and condition data sectors prior to a Write Sector Without Erase command or a Write Multiple Without Erase command. There is no data transfer associated with this command but a Write Fault error status can occur. Table 52 defines the Byte sequence of the Erase Sector command. Table 52. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Erase Sector(s) 7 6 5 4 C0h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 10.4 Identify Drive (ECh) The Identify Drive command enables the host to receive parameter information from the Card. This command has the same protocol as the Read Sector(s) command. Table 53 defines the Identify Drive command Byte sequence. All reserved bits or Words are zero. Table 54 shows the definition of each field in the Identify Drive Information. 10.4.1 Word 0: General Configuration This field indicates the general characteristics of the device. The default value for Word 0 is set to 848Ah. It is recommended that PCMCIA modes of operation report only the 848Ah value as they are always intended as removable devices. Alternate Configuration Values for Word 0 is 044Ah. Some operating systems require Bit 6 of Word 0 to be set to ‘1’ (Non-removable device) to use the Card as the root storage device. The Card must be the root storage device when a host completely replaces conventional disk storage with a CompactFlash Card in True IDE mode. To support this requirement and provide capability for any future removable media cards, alternate value of Word 0 is set in True IDE Mode of operation. 10.4.2 Word 1: Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 10.4.3 Word 3: Default Number of Heads This field contains the number of translated heads in the default translation mode. 58/91 SMCxxxBF CF-ATA command description 10.4.4 Word 6: Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. 10.4.5 Word 7-8: Number of Sectors per Card This field contains the number of sectors per Card. This double Word value is also the first invalid address in LBA translation mode. 10.4.6 Word 10-19: Memory Card Serial Number The contents of this field are right justified and padded with spaces (20h). 10.4.7 Word 23-26: Firmware Revision This field contains the revision of the firmware for this product. 10.4.8 Word 27-46: Model Number This field contains the model number for this product and is left justified and padded with spaces (20h). 10.4.9 Word 47: Read/Write Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands. 10.4.10 Word 49: Capabilities ● ● ● Bit 13 Standby Timer: is set to ’0’ to indicate that the Standby timer operation is defined by the manufacturer. Bit 9 LBA support: CompactFlash Memory Cards support LBA mode addressing. Bit 8 DMA Support: Read/Write DMA commands are supported. 10.4.11 Word 51: PIO Data Transfer Cycle Timing Mode This field defines the mode for PIO data transfer. For backward compatibility with BIOSs written before Word 64 was defined for advanced modes, a device reports in Word 51, the highest original PIO mode it can support (PIO mode 0, 1 or 2). Bits 15-8: are set to 02H. 10.4.12 Word 53: Translation Parameter Valid ● ● Bit 1: is set to '1' to indicate that Words 64 to 70 are valid Bit 0: is set to '1' to indicate that Words 54 to 58 are valid 10.4.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. 59/91 CF-ATA command description SMCxxxBF 10.4.14 Word 57-58: Current Capacity This field contains the product of the current cylinders, heads and sectors. 10.4.15 Word 59: Multiple Sector Setting ● ● ● Bits 15-9 are reserved and must be set to ‘0’. Bit 8 is set to ‘1’, to indicate that the Multiple Sector Setting is valid. Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’. 10.4.16 Word 60-61: Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the Card in LBA mode only. 10.4.17 Word 63: Multi-Word DMA transfer Bits 15 through 8 of Word 63 of the Identify Device parameter information identifies which Multi-Word DMA mode that has been selected by host.Each bit of Word 0 is significant. Only one of these bits can be set to ‘1’ by the CompactFlash Storage Card to indicate the MultiWord DMA mode which is currently selected: ● ● ● ● Bits 15 to 11 are reserved. Bit 10: when set to ‘1’, it indicates that Multi-Word DMA mode 1 has been selected. Bit 9: when set to ‘1’, it indicates that Multi-Word DMA mode 1 has been selected. Bit 8: when set to ‘1’, it indicates that Multi-Word DMA mode 0 has been selected. Bits 7 to 0 define the Multi-Word DMA data transfer supported field. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate which Multi-Word DMA mode is supported: ● ● ● ● Bit 7 to 3 are reserved. Bit 2: when set to ‘1’, it indicates that the CompactFlash Storage Card supports MultiWord DMA modes 2, 1 and 0. Bit 1: when set to ‘1’, it indicates that the CompactFlash Storage Card supports MultiWord DMA modes 1 and 0. Bit 0: when set to ‘1’, it indicates that the CompactFlash Storage Card supports MultiWord DMA mode 0. Note: 1 2 Selection of Multi-Word DMA modes 3 and above are specific to CompactFlash, and are reported in Word 163. Support for Multi-Word DMA modes 3 and above are specific to CompactFlash are reported in Word 163. 60/91 SMCxxxBF CF-ATA command description 10.4.18 Word 64: Advanced PIO transfer modes supported This field is bit significant. Any number of bits may be set to ‘1’ in this field by the CompactFlash Memory Card to indicate the advanced PIO modes it is capable of supporting. ● ● ● Bits 7-2 are reserved for future advanced PIO modes. Bit 1 is set to ‘1’, indicates that the CompactFlash Memory Card supports PIO mode 4. Bit 0 is set to ‘1’ to indicate that the CompactFlash Memory Card supports PIO mode 3. Note: Support for PIO modes 5 and above are specific to CompactFlash are reported in Word 163 10.4.19 Word 65: Minimum Multi-Word DMA transfer cycle time Word 65 of the parameter information of the Identify Device command is defined as the minimum Multi-Word DMA transfer cycle time. It corresponds to the minimum cycle time for which the Card ensures data integrity during transfers. It is expressed in nanoseconds. The returned value is ‘50h’ (for Cycle time values refer to Table 22). 10.4.20 Word 66: Recommended Multi-Word DMA transfer cycle time Word 66 of the parameter information of the Identify Device command is defined as the recommended Multi-Word DMA transfer cycle time. The returned value is ‘50h’ (for Cycle time values refer to Table 22). 10.4.21 Word 67: Minimum PIO transfer cycle time without flow control This field gives the minimum cycle time (in ns) that the host should use for the CompactFlash Memory Card to ensure data integrity during transfers when flow control is not used. The returned value is ‘50h’ (for Cycle time values refer to Table 22). 10.4.22 Word 68: Minimum PIO transfer cycle time with IORDY This field gives the minimum cycle time (in ns) supported by the CompactFlash Memory Card to perform data transfers using IORDY flow control. The returned value is ‘50h’ (for Cycle time values refer to Table 22). 61/91 CF-ATA command description SMCxxxBF 10.4.23 Word 163: Advanced True IDE Timing mode capabilities and settings This word describes the capabilities and current settings for CFA defined Advanced Timing modes using the True IDE interface. There are four sub-fields that describe the Advanced PIO and Advanced Multi-Word DMA Timing modes supported and selected: ● Bits 2-0: Advanced True IDE PIO Mode supported. The returned value is ‘2h’ to indicate that PIO mode 6 is the highest PIO mode supported. ● Bits 5-3: Advanced True IDE Multi-Word DMA mode supported. The returned value is ‘2h’ to indicate that Multi-Word DMA mode 4 is the highest MultiWord DMA mode supported. ● ● Bits 8-6: Advanced True IDE PIO mode selected. These bits indicate the current True IDE PIO mode selected on the Card. Bits 11-9: Advanced True IDE Multi-Word DMA mode selected. These bits indicate the current True IDE Multi-Word DMA mode selected on the Card. 10.4.24 Word 164: Advanced PCMCIA I/O and Memory Timing modes capabilities and settings This Word describes the capabilities and current settings for CFA defined Advanced Timing modes using the Memory and PCMCIA I/O interface: ● Bits 2-0: maximum Advanced PCMCIA I/O mode supported. The returned value is ‘3h’ to indicate that 80ns is the maximum I/O timing mode supported by the Card. ● Bits 5-3: maximum PCMCIA Memory timing mode supported. The returned value is ‘3h’ to indicate that 80ns is the maximum PCMCIA Memory timing mode supported by the Card. Table 53. Bit Identify Drive 7 6 5 4 ECh X Drive X X X X X X 3 2 1 0 Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 62/91 SMCxxxBF Table 54. Word Address CF-ATA command description Identify Drive Information Default Value 848Ah 0 044Ah 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62 XXXXh 0000h 00XXh 0000h 0000h XXXXh XXXXh 0000h aaaa 0000h 0000h 0004h aaaa aaaa 0001h 0000h 0200h 0000h 0200h 0000h 0003h XXXXh XXXXh XXXXh XXXXh 0100h XXXXh 0000h 2 2 2 2 2 2 2 4 2 20 2 2 2 8 40 2 2 2 2 2 2 2 2 2 2 4 2 4 2 Total Bytes 2 Data Field Type Information General Configuration (signature of the CompactFlash Memory Card) Alternate Configuration. Default number of cylinders Reserved Default number of heads Obsolete Obsolete Default number of sectors per track Number of sectors per Card (Word 7 = MSW, Word 8 = LSW) Obsolete Serial number in ASCII (right justified) Obsolete Obsolete Reserved Firmware revision in ASCII. Big Endian Byte Order in Word Model number in ASCII (right justified) Big Endian Byte Order in Word Maximum number of sectors on Read/Write Multiple command Reserved Capabilities Reserved PIO data transfer cycle timing mode Obsolete Field validity Current numbers of cylinders Current numbers of heads Current sectors per track Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved. 63/91 CF-ATA command description Table 54. Word Address 63 64 65 66 67 68 69-128 129-159 160-162 163 164 165-255 SMCxxxBF Identify Drive Information (continued) Default Value 0407h 0003h 0050h 0050h 0050h 0050h 0000h 0000h 0000h 0492h 001Bh 0000h Total Bytes 2 2 2 2 2 2 120 62 4 2 2 190 Data Field Type Information Multi-Word DMA transfer. In PCMCIA mode, this value is ‘0h’. Advanced PIO modes supported Minimum Multi-Word DMA transfer cycle time per Word. In PCMCIA mode this value is ‘0h’. Recommended Multi-Word DMA transfer cycle time. In PCMCIA mode this value is ‘0h’. Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved manufacturer unique Bytes Reserved CF Advanced True IDE Timing Mode Capability and Setting CF Advanced PCMCIA I/O and Memory Timing Mode Capability Reserved 10.5 Idle (97h or E3h) This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count (each count is 5ms) and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5ms) is different from the ATA specification. Table 55 defines the Byte sequence of the Idle command. Table 55. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Idle 7 6 5 4 3 2 1 0 97h or E3h Drive X X X Timer Count (5ms increments) X X 64/91 SMCxxxBF CF-ATA command description 10.6 Idle Immediate (95h or E1h) This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. Table 56 defines the Idle Immediate command Byte sequence. Table 56. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Idle Immediate 7 6 5 4 3 2 1 0 95h or E1h Drive X X X X X X 10.7 Initialize Drive Parameters (91h) This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command. Table 57 defines the Initialize Drive Parameters command Byte sequence. Table 57. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X Initialize Drive Parameters 7 6 5 4 91h Max Head (no. of heads 1) 3 2 1 0 65/91 CF-ATA command description SMCxxxBF 10.8 NOP (00h) This command always fails with the CompactFlash Memory Card returning command aborted. Table 58 defines the Byte sequence of the NOP command. Table 58. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X X X NOP 7 6 5 4 00h X 3 2 1 0 10.9 Read Buffer (E4h) The Read Buffer command enables the host to read the current contents of the Card’s sector buffer. This command has the same protocol as the Read Sector(s) command. Table 59 defines the Read Buffer command Byte sequence. Table 59. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X X X Read Buffer 7 6 5 4 E4h X 3 2 1 0 66/91 SMCxxxBF CF-ATA command description 10.10 Read DMA (C8h) This command uses Multi-Word DMA mode to read from 1 to 256 sectors as specified in the Sector Count register. If the sector count is set to ‘0’, 256 sectors will be read by issuing a Read DMA command. Data transfer begins at the sector specified in the Sector Number Register. When the Read DMA command is issued, the CompactFlash Card asserts BSY, and transfers all or part of the sector data in the buffer. The Card can then set DRQ and clear BSY, although it is not required. The Card asserts DMARQ when data are available to be transferred. The host then reads the 512*sector-count Bytes of data from the Card using DMA protocol. When DMARQ is asserted, the host asserts -DMACK to notify it is ready to transfer data, and asserts -IORD once for each 16 bit Word to be transferred. Interrupts are not generated for each sector transfer, but when all sectors have been transferred or when an error occurred during the operation. An Abort error is returned by the Card when a Read DMA command is sent by the host and the 8-bit transfer mode has been enabled by the Set Features command. Table 60 defines the Read DMA command Byte sequence. Table 60. Read DMA Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) LBA Drive 7 6 5 4 C8h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 67/91 CF-ATA command description SMCxxxBF 10.11 Read Multiple (C4h) The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = (sector count) module (block count). If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. Table 61 defines the Read Multiple command Byte sequence. Table 61. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Read Multiple 7 6 5 4 C4h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 68/91 SMCxxxBF CF-ATA command description 10.12 Read Sector(s) (20h or 21h) This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and after each sector of data (except the last one) has been read by the host, the Card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 Bytes of data from the buffer. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer. Table 62 defines the Read Sector command Byte sequence. Table 62. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Read Sector(s) 7 6 5 4 3 2 20h or 21h Head (LBA 27-24) Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 1 0 10.13 Read Verify Sector(s) (40h or 41h) This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the Card sets BSY. When the requested sectors have been verified, the Card clears BSY and generates an interrupt. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified. Table 63 defines the Read Verify Sector command Byte sequence. 69/91 CF-ATA command description Table 63. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 SMCxxxBF Read Verify Sector(s) 7 6 5 4 3 40h or 41h Drive Head (LBA 27-24) 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 10.14 Recalibrate (1Xh) This command is effectively a NOP command to the Card and is provided for compatibility purposes. Table 64 defines the Recalibrate command Byte sequence. Table 64. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive X X X X X Recalibrate 7 6 5 4 1Xh X 3 2 1 0 70/91 SMCxxxBF CF-ATA command description 10.15 Request Sense (03h) This command requests extended error information for the previous command. Table 65 defines the Request Sense command Byte sequence. Table 66 defines the valid extended error codes. The extended error code is returned to the host in the Error Register. Table 65. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 X 1 Drive X X X X X Request Sense 7 6 5 4 03h X 3 2 1 0 Table 66. Extended Error Codes Description No Error Detected Self Test OK (No Error) Miscellaneous Error Invalid Address (Requested Head or Sector Invalid) Address Overflow (Address Too Large) Supply or generated Voltage Out of Tolerance Uncorrectable ECC Error Corrected ECC Error Self Test or Diagnostic Failed ID Not Found Spare Sectors Exhausted Data Transfer Error / Aborted Command Corrupted Media Format Write / Erase Failed Extended Error Code 00h 01h 09h 21h 2Fh 35h, 36h 11h 18h 05h, 30-34h, 37h, 3Eh 10h, 14h 3Ah 1Fh 0Ch, 38h, 3Bh, 3Ch, 3Fh 03h 71/91 CF-ATA command description SMCxxxBF 10.16 Seek (7Xh) This command is effectively a NOP command to the Card although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. Table 67 shows the Seek command Byte sequence. Table 67. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Seek 7 6 5 4 7Xh Drive Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) X X 10.17 Set Features (EFh) This command is used by the host to establish or select certain features. Table 68 shows the Set Features command Byte sequence. Table 69 defines all features that are supported. ● Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature command is issued all data transfers will occur on the D7D0 data lines and the –IOIS16 signal will not be asserted for data register accesses. The host must not enable this feature for DMA transfers. Feature 03h allows the host to select the PIO or the Multi-Word DMA transfer mode. The number of sectors to be transferred must be specified in the Sector Count register (see Table 70 for values). The upper 5 bits define the type of transfer and the lower 3 bits encode the transfer mode. Only one PIO mode and one Multi-Word mode can be selected at a time. The host can change the selected mode by issuing the Set Features command. Feature code 9Ah allows the host to configure the Card to best meet the host system power requirements. The host programs the Sector Count register to a value that is equal to one-fourth of the desired maximum average current (in mA) that the Card should consume. For example, if the Sector Count register is set to ‘6’, the Card must be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the Card replies to the host with the range of values that it supports. The minimum value is set in the Cylinder Low Register, and the maximum value is set in the Cylinder Hi register. After power-up, the Card defaults to operate at the highest performance and therefore in the highest current mode. Values outside this programmable range are accepted by the card. However, the Card will operate either at the lowest power or highest performance as appropriate. ● ● 72/91 SMCxxxBF Table 68. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X Config Feature M CF-ATA command description Set Features 7 6 5 4 EFh X 3 2 1 0 Table 69. Feature 01h 03h 55h 69h 81h 96h 97h 9Ah Features Supported Operation Enable 8-bit data transfers. Set transfer mode based on value in Sector Count register. Disable Read Look Ahead. NOP Accepted for backward compatibility. Disable 8 bit data transfer. NOP Accepted for backward compatibility. Accepted for backward compatibility. Use of this Feature is not recommended. Set the host current source capability. Allows trade-off between current drawn and read/write speed. Table 70. Transfer Mode Values Mode Bits (7:3) 00000b 00000b 00001b 00010b 00100b Bits (2:0) 000b 001b Mode(1) N/A Mode PIO default mode PIO default mode, disable IORDY PIO flow control transfer mode Reserved Multi-Word DMA mode 1. Mode = transfer mode number 73/91 CF-ATA command description SMCxxxBF 10.18 Set Multiple Mode (C6h) This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. Upon receipt of the command, the Card sets BSY and checks the Sector Count Register. If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for all subsequent Read Multiple and Write Multiple commands and execution is enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the Sector Count Register contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled. At power on the default mode is Read and Write Multiple disabled, unless it is disabled by a Set Feature command. Table 71 defines the Set Multiple Mode command Byte sequence. Table 71. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X Sector Count X Set Multiple Mode 7 6 5 4 C6h X 3 2 1 0 10.19 Set Sleep Mode (99h or E6h) This command causes the CompactFlash Memory Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command. Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 5 milliseconds. Note that this time base (5ms) is different from the ATA Specification. Table 72 defines the Set Sleep Mode command Byte sequence. 74/91 SMCxxxBF Table 72. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X CF-ATA command description Set Sleep Mode 7 6 5 4 3 99h or E6h Drive X X X X X X 2 1 0 10.20 Standby (96h or E2) This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA ‘Standby’ Mode), clear BSY and return the interrupt immediately. Recovery from Sleep mode is accomplished by issuing another command. Table 73 defines the Standby command Byte sequence. Table 73. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Standby 7 6 5 4 3 96h or E2h Drive X X X X X X 2 1 0 10.21 Standby Immediate (94h or E0h) This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA Standby Mode), clear BSY and return the interrupt immediately. Recovery from Sleep mode is accomplished by issuing another command. Table 74 defines the Standby Immediate Byte sequence. 75/91 CF-ATA command description Table 74. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X SMCxxxBF Standby Immediate 7 6 5 4 3 94h or E0h Drive X X X X X X 2 1 0 10.22 Translate Sector (87h) This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512 Byte buffer of information containing the desired cylinder, head and sector, including its Logical Address, and the Hot Count, if available, for that sector. Table 75 defines the Translate Sector command Byte sequence. Table 76 represents the information in the buffer. Table 75. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Translate Sector 7 6 5 4 87h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X Table 76. Address 00h-01h 02h 03h 04-06h 07-12h 13h 14h-17h 18h-1Ah 1Bh-1FFh Translate Sector Information Information Cylinder MSB (00), Cylinder LSB (01) Head Sector LBA MSB (04) - LSB (06) Reserved Erased Flag (FFh) = Erased; 00h = Not Erased Reserved Hot Count MSB (18) - LSB (1A); 0 = Hot Count not supported Reserved 76/91 SMCxxxBF CF-ATA command description 10.23 Wear Level (F5h) This command is effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with a ‘00h’ indicating Wear Level is not needed. Table 77 defines the Wear Level command Byte sequence. Table 77. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X Completion Status X Wear level 7 6 5 4 F5h Flag 3 2 1 0 10.24 Write Buffer (E8h) The Write Buffer command enables the host to overwrite contents of the Card’s sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 Bytes. Table 78 defines the Write Buffer command Byte sequence. Table 78. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X Drive X X X X X Write Buffer 7 6 5 4 E8h X 3 2 1 0 77/91 CF-ATA command description SMCxxxBF 10.25 Write DMA (CAh) This command uses DMA mode to write from 1 to 256 sectors as specified in the Sector Count register. If the sector count is set to ‘0’, 256 sectors will be read by issuing a Read DMA command. The transfer begins at the sector specified in the Sector Number Register. When the Write DAM command is issued, the CompactFlash Storage Card asserts BSY and transfers all or part of the sector data in the buffer. The Card can then set DRQ and clear BSY, although it is not required. The Card asserts DMARQ when data are available to be transferred. The host then writes the 512*sector-count Bytes of data to the Card using the DMA protocol. When DMARQ is asserted by the Card, the host asserts -DMACK to notify that it is ready to transfer data, and asserts -IOWR once for each 16 bit Word to be transferred. Interrupts are not generated for each sector transfer, but when all sectors have been transferred or when an error occurred during the operation. An Abort error is returned by the Card when a Write DMA command is sent by the host and the 8-bit transfer mode has been enabled by the Set Features command. Table 79 defines the Write DMA command Byte sequence. Table 79. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) LBA Drive Write DMA 7 6 5 4 CAh Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 78/91 SMCxxxBF CF-ATA command description 10.26 Write Multiple Command (C5h) This command is similar to the Write Sectors command. The Card sets BSY within 400ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = (sector count) module (block count). If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error. Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of the command. For example, each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the address is that of the third sector. Note: The current revision of the CompactFlash Memory Card only supports a block count of 1 as indicated in the Identify Drive Command information. The Write Multiple command is provided for compatibility with future products which may support a larger block count. Table 80 defines the Write Multiple command Byte sequence. Table 80. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High Cylinder Low Sector Number Sector Count X Write Multiple 7 6 5 4 C5h Head 3 2 1 0 79/91 CF-ATA command description SMCxxxBF 10.27 Write Multiple without Erase (CDh) This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. Table 81 defines the Write Multiple without Erase command Byte sequence. Table 81. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) X LBA 1 Write Multiple without Erase 7 6 5 4 CDh Driv e Cylinder High Cylinder Low Sector Number Sector Count X Head 3 2 1 0 10.28 Write Sector(s) (30h or 31h) This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the Card sets BSY, sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. Table 82 defines the Write Sector(s) command Byte sequence. 80/91 SMCxxxBF Table 82. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 CF-ATA command description Write Sector(s) 7 6 5 4 3 30h or 31h Drive Head (LBA 27-24) 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 10.29 Write Sector(s) without Erase (38h) This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. This command has the same protocol as the Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. If the sector is not pre-erased a normal write sector operation will occur. Table 83 defines the Write Sector(s) without Erase command Byte sequence. Table 83. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LB A 1 Drive Write Sector(s) without Erase 7 6 5 4 3 38h Head (LBA 27-24) 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 81/91 CF-ATA command description SMCxxxBF 10.30 Write Verify (3Ch) This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write Sector(s) command. Table 84 defines the Write Verify command Byte sequence. Table 84. Bit Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sect Num (3) Sect Cnt (2) Feature (1) 1 LBA 1 Drive Write Verify 7 6 5 4 3Ch Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 82/91 SMCxxxBF CIS information (typical) 11 CIS information (typical) -------0000: Code 01, link 04 DF 79 01 FF -------– – – – – – -------000C: Code 1C, link 05 02 DF 79 01 FF -------– – – – – – – -------001A: Code 18, link 02 DF 01 -------– – -------0022: Code 20, link 04 0A 00 00 00 -------– – -------002E: Code 15, link 12 04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00 00 FF Tuple CISTPL_MANFID (20), length 4 (04) Manufacturer # 0x000A hardware rev 0.00 Tuple CISTPL_JEDEC_C (18), length 2 (02) Device 0 JEDEC id: Manufacturer DF, ID 01 Tuple CISTPL_DEVICE_OC (1C), length 5 (05) Device conditions: VCC = 3.3V Device type is FUNCSPEC Extended speed byte used Device speed is 80ns Write protect switch is not in control Device size is 2K bytes Tuple CISTPL_DEVICE (01), length 4 (04) Device type is FUNCSPEC Extended speed byte used Device speed is 80ns Write protect switch is not in control Device size is 2K bytes 83/91 CIS information (typical) -------– – – – -------0056: Code 21, link 02 04 01 -------– – Tuple CISTPL_FUNCID (21), length 2 (02) Function code 04 (Fixed Disk), system init 01 Tuple CISTPL_VERS_1 (15), length 18 (12) Major version 4, minor version 1 Product Information: Manufacturer: "Numonyx", Product name: "Numonyx-xxxxB" SMCxxxBF -------005E: Code 22, link 02 01 01 -------– – -------0066: Code 22, link 03 02 0C 0F -------– – – – – – – – – -------0070: Code 1A, link 05 01 03 00 02 0F -------– – – – – – – Tuple CISTPL_CONFIG (1A), length 5 (05) Last valid configuration index is 3 Configuration Register Base Address is 200 Configuration Registers Present: Configuration Option Register at 200 Card Configuration and Status Register at 202 Pin Replacement Register at 204 Socket and Copy Register at 206 Tuple CISTPL_FUNCE (22), length 3 (03) VPP is not required This is a silicon device Identify Drive Model/Serial Number is guaranteed unique Low-Power Modes supported: Sleep Standby Idle Drive automatically minimizes power All modes include 3F7 or 377 Index bit is not supported -IOIS16 is unspecified in Twin configurations Tuple CISTPL_FUNCE (22), length 2 (02) This is a PC Card ATA Disk 84/91 SMCxxxBF -------007E: Code 1B, link 08 C0 C0 A1 01 55 08 00 20 -------– – – – – – – – -------0092: Code 1B, link 06 00 01 21 B5 1E 4D -------– – – -------00A2: Code 1B, link 0A C1 41 99 01 55 64 F0 FF FF 20 -------– – – – – – – – – – -------00BA: Code 1B, link 06 01 01 21 B5 1E 4D -------Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 01 VCC Power Description: Nom V = 3.30 V, Tuple CISTPL_CFTABLE_ENTRY (1B), length 10 (0A) Configuration Table Index is 01 (default) Interface type is I/O BVDs not active, WP not active, RdyBsy active Wait signal support not required VCC Power Description: Nom V = 5.0 V Decode 4 I/O lines, bus size 8 or 16 Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 00 Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08) Configuration Table Index is 00 (default) Interface type is Memory BVDs not active, WP not active, RdyBsy active Wait signal support required VCC Power Description: Nom V = 5.0 V map 2048 bytes of memory to Card address 0 CIS information (typical) Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown VCC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA IRQ may be shared, pulse and level mode interrupts are supported Interrupts in mask FFFF are supported Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 85/91 CIS information (typical) Peak I = 45.0 mA -------00CA: Code 1B, link 0F C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20 -------– – – – – – – – – – – – – -------00EC: Code 1B, link 06 02 01 21 B5 1E 4D -------– – – -------00FC: Code 1B, link 0F C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20 -------– – – – – – – – – – – – Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) Configuration Table Index is 03 (default) Interface type is I/O BVDs not active, WP not active, RdyBsy active Wait signal support not required VCC Power Description: Nom V = 5.0 V Decode 10 I/O lines, bus size 8 or 16 I/O block at 0170, length 8 I/O block at 0376, length 2 IRQ may be shared, pulse and level mode interrupts are supported Only IRQ14 is supported Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 02 VCC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) Configuration Table Index is 02 (default) Interface type is I/O BVDs not active, WP not active, RdyBsy active Wait signal support not required VCC Power Description: Nom V = 5.0 V Decode 10 I/O lines, bus size 8 or 16 I/O block at 01F0, length 8 I/O block at 03F6, length 2 IRQ may be shared, pulse and level mode interrupts are supported Only IRQ14 is supported SMCxxxBF Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 86/91 SMCxxxBF -------011E: Code 1B, link 06 03 01 21 B5 1E 4D -------– – – -------012E: Code 14, link 00 -------– -------0134: Code FF -------– Tuple CISTPL_END (FF) Tuple CISTPL_NO_LINK (14), length 0 (00) Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) Configuration Table Index is 03 CIS information (typical) VCC Power Description: Nom V = 3.30 V, Peak I = 45.0 mA 87/91 Package mechanical SMCxxxBF 12 Package mechanical Figure 10. Type I CompactFlash Memory Card Dimensions 1.60mm ± 0.5 (0.063in ± 0.002) 26 50 0.99mm± 0.05 (0.039in ± 0.002) 3.30mm ± 0.10 (0.130in ± 0.004) 1 1.01mm ± 0.07 (0.039in ± 0.003) 25 1.01mm ± 0.07 (0.039in ± 0.003) 2.44mm ± 0.07 (0.096in ± 0.003) 2X 25.78mm ± 0.07 (2X 1.015in ± 0.003) Optional Configuration (see note) 2X 12.00mm ± 0.1 (2X 0.472in ± 0.004) 36.40mm ± 0.15 (1.433in ± 0.006) 2.15mm ± 0.07 (0.085in ± 0.003) 2X 3.00mm ± 0.07 (2X 0.118in ± 0.003) 0.76mm ± 0.07 (0.030in ± 0.003) 0.63mm ± 0.07 (0.025in ± 0.003) 1.65mm (0.130in) 4X R 0.5mm ± 0.1 (4X R 0.020in ± 0.004) 41.66mm ± 0.13 (1.640in ± 0.005) 42.80mm ± 0.10 (1.685in ± 0.004) TO P AI04301b 88/91 SMCxxxBF Part numbering 13 Part numbering Table 85. Example: Ordering Information Scheme SMC 01G B F Y 6 E Memory Card Standard SMC = Storage Medium, CompactFlash Density 032 = 32 MBytes 064 = 64 MBytes 128 = 128 MBytes 256 = 256 MBytes 512 = 512 MBytes 01G = 1 GBytes 02G = 2 GBytes 04G = 4 GBytes Options of the Standard B = CF Type SM222 Memory Type F = Flash Memory Card Version Y= Version depending on device technology Temperature Range 6 = -40 to 85°C Packing Blank = Standard Packing (tray) E = Lead-Free Package, Standard Packing (tray) Note: Other digits may be added to the ordering code for pre-programmed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’.For further information on any aspect of the device, please contact your nearest Numonyx Sales Office. 89/91 Revision history SMCxxxBF 14 Revision history Table 86. Date 22-Sep-2006 Document Revision History Version 1 Initial release. Sustained write and read performances changed to 12.5MB/s and 19MB/s, respectively. Table 2: System Performance and Table 3: Current Consumption updated. Sectors_card and total addressable capacity updated for SMC04GBF in Table 6: CF capacity specification. Table 11: Input Power updated. Note 1 updated below Figure 7: I/O Write waveforms. Read Byte Access Configuration CF+ (8 bits) mode removed from Table 32: Attribute Memory Function. Applied Numonyx branding. Revision Details 27-Oct-2006 2 10-Dec-2007 3 90/91 SMCxxxBF Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 91/91