SMS128FF

SMSxxxAF SMSxxxFF, SMSxxxBF 64 MByte, 128 MByte, 256 MByte 512 MByte and 1 GByte, 3.3V Supply Secure Digital™ Card Features ■ ■ ■ SD Memory Card Specification Version 1.01compliant Up to 1 Gbyte of Formatted Data Storage Bus Mode – SD Protocol (1 to 4 Data Lines) – SPI Protocol Operating Voltage Range: – Basic Communication (CMD0, CMD15, CMD55 and ACMD41): 2.0V to 3.6V – Other Commands and Memory Access: 2.7V to 3.6V Variable Clock Rate: 0 to 25 MHz Read Access (using 4 Data Lines) – Sustained Multiple Block: 6.3 Mb/s Write Access (using 4 Data Lines) – Sustained Multiple Block: 3.0 Mb/s Maximum Data Rate with up to 10 Cards Aimed at Portable and Stationary Applications Communication Channel Protocol Attributes: – Six-wire communication channel (clock, command, 4 data lines) – Error-proof data transfer – Single or Multiple block oriented data transfer Device summary Part Number SMS128AF SMS256AF SMS512AF SMS01GAF SMS064BF SMS128BF SMS064FF SMS128FF SMS256FF SMS512FF Package Form Factor Operating Voltage Range ■ ■ ■ ■ ■ MiniSD MicroSD SD SD Secure Digital ■ ■ ■ ■ ■ ■ ■ miniSD Memory Field Error Correction Safe Card Removal during Read Write Protect Feature using Mechanical Switch Built-in Write Protection Features (Permanent and Temporary) SD, MiniSD and MicroSD Packages – ECOPACK® compliant – Halogen free – Antimony free Table 1. SD (full size) MiniSD 2.7V to 3.6V MicroSD December 2007 Rev 3 1/61 www.numonyx.com 1 Contents SMSxxxAF, SMSxxxFF, SMSxxxBF Contents 1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Secure digital memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 3.3 3.4 Secure digital memory card bus topology . . . . . . . . . . . . . . . . . . . . . . . . 15 SD bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SD Memory Card Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 3.4.2 Card Identification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 3.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 SD memory card hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 4.2 4.3 4.4 4.5 SD memory card bus circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Hot Insertion/Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Card registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 5.2 5.3 5.4 5.5 5.6 OCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CSD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RCA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DSR Register (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Command and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.1 6.1.2 Card Identification and Operating Conditions Timings . . . . . . . . . . . . . 35 Card Relative Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/61 SMSxxxAF, SMSxxxFF, SMSxxxBF 6.1.3 6.1.4 6.1.5 Contents Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Last Card Response, Next Host Command Timings . . . . . . . . . . . . . . . 36 Last Host Command, Next Host Command Timings . . . . . . . . . . . . . . . 37 6.2 Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 6.2.2 Single Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Multiple Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.1 6.3.2 Single Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Multiple Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4 STOP_TRANSMISSION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4.1 6.4.2 Erase, Set and Clear Write Protect Timings . . . . . . . . . . . . . . . . . . . . . 41 Re-selecting a busy card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5 Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 Serial peripheral interface (SPI) mode . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 7.2 SPI bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SPI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Bus Transfer Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Erase & Write Protect Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Read CID/CSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory Array Partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Card Lock/Unlock Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Application Specific Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 7.4 SPI Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.4.1 7.4.2 7.4.3 7.4.4 R1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 R1b Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 R2 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 R3 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5 7.6 Clearing Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SPI Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 Data Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3/461 Contents 7.6.2 SMSxxxAF, SMSxxxFF, SMSxxxBF Data Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Appendix A Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4/61 SMSxxxAF, SMSxxxFF, SMSxxxBF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 System reliability and maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory array structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Full-size SD Memory Card pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MicroSD Contact Pad Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Card States vs. Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SD Card Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Response R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Response R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Response R3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Response R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Bus Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Signal Condition - I/O Signal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SD Memory Card Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OCR Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CID Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11 . . . . . . . . 33 SCR Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Timing Diagram Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Command Classes in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SPI Timing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SPI Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Full-Size Secure Digital Memory Card Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MiniSD package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MicroSD package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5/61 List of figures SMSxxxAF, SMSxxxFF, SMSxxxBF List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Write Protection hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Full size Secure Digital Memory Card form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MicroSD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Secure Digital Memory Card system bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 "No Response" and "No Data" operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 (Multiple) Block Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 (Multiple) Block Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Command Token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 response token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SD Memory Card State Diagram (Card Identification Mode) . . . . . . . . . . . . . . . . . . . . . . . 21 SD Memory Card State Diagram (Data Transfer Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Full Size SD Memory Card Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-Up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bus Signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Input/Output Timings Referenced to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Identification Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SEND_RELATIVE_ADDRESS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Response (Data Transfer Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Response End To Next CMD Start (Data Transfer Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 36 Command Sequence (All Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Single Block Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Multiple Block Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STOP_TRANSMISSION Command (CMD12, Data Transfer Mode) . . . . . . . . . . . . . . . . . 38 Block Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multiple Block Write Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STOP_TRANSMISSION During Data Transfer From The Host . . . . . . . . . . . . . . . . . . . . . 40 STOP_TRANSMISSION During CRC Status Transfer From Card. . . . . . . . . . . . . . . . . . . 40 STOP_TRANSMISSION Received After Last Data Block with Card Busy . Programming40 STOP_TRANSMISSION Received After Last Data Block with Card Idle . . . . . . . . . . . . . . 41 SD Memory Card System SPI Mode Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Read Operation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Multiple Block Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Read Data Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Erase & Write Protect Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Host Command to Card Response - Card is Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Host Command to Card Response - Card is Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Card Response to Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Single Block Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STOP_TRANSMISSION between Blocks During Multiple Block Read . . . . . . . . . . . . . . . 50 STOP_TRANSMISSION within a Block During Multiple Block Read . . . . . . . . . . . . . . . . 51 CSD Register Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Single Block Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Multiple Block Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Full-Size Secure Digital Memory Card Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 mini Secure Digital Card Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MicroSD card mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6/761 SMSxxxAF, SMSxxxFF, SMSxxxBF Figure 49. List of figures Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7/761 Description SMSxxxAF, SMSxxxFF, SMSxxxBF 1 Description The Secure Digital Memory Card (SD Memory Card) is a Flash-Based Memory Card. It is specifically designed to meet the security, capacity, performance and environmental requirements of the latest-generation audio and video consumer electronic devices, that is mobile phones, digital cameras, digital recorders, PDAs, organizers, electronic toys, etc. The Secure Digital Memory Card is a high-mobility, high-performance, low-cost and lowpower consumption device that features high data throughput at the memory card interface. It includes a copyright protection mechanism that complies with the security of the SDMI (Secure Digital Music Initiative) standard. The Secure Digital Memory Card security system uses mutual authentication and a “cipher algorithm” that protects the card from illegal use. Unsecured access to the user's personal content is also available. The Secure Digital Memory Cards have an advanced communication interface designed to operate in a low voltage range. The full-size Secure Digital Memory Card has a 9-pin interface whereas the Mini Secure Digital Memory Card has a 11-pin interface but can be fitted with a 9-pin adapter. Only the 9-pin interface is described in this document. The MicroSD Memory Card has an 8-pin interface, and can also be fitted with a 9-pin adapter. Table 2, Table 3, Table 4, Table 5, and Table 6 give an overview of the Secure Digital Memory Card features. In order to meet environmental requirements, the devices are offered in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The SD, MiniSD and MicroSD packages are also Halogen free and Antimony free. Related documentation ● ● ● Secure Digital Memory Card Specifications: Part 1 Physical Layer Specification, Version 1.01 MiniSd Memory Card Specifications: Addendum to SD Memory Card Specifications Part 1 Physical layer Specification, Version 1.02 MicroSD Memory Card Specifications: Addendum to SD Memory Card Specifications Part 1, Physical Layer Specification, Version 1.00 System performance System performance Max. 30 (1) Table 2. Typ. Unit µs Sleep to Ready Sustained Multiple Block Read Burst Single Block Read (1) 6.3 (43X) 1.8 (12X) 3.0 (20X) 0.8 (5X) 150 MBytes/s MBytes/s MBytes/s MBytes/s ms Sustained Multiple Block Write(1) Burst Single Block Write(1) Power-up to Ready 1. 43X, 20X, 12X and 5X Speed grade markings where 1X = 150 KBytes/s. 8/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 3. Power consumption(1) Mode Standby Read Write 1. TA= 25°C, VDD= 3.6V. Description Max. Current Consumption 200 µA 30 mA 30 mA Table 4. Environmental specifications(1) Operating −25°C to 85°C NA NA Non-Operating − 40°C to 85°C 85°C - 85%RH ±4kV, Human body model according to ANSI EOS/ESD-S5.1-1998 ±8kV (coupling plane discharge) Environmental specifications Temperature Humidity (non- condensing) Contact Pads ESD Protection Other ±15kV (air discharge) Human body model per IEC61000-4-2 NA NA NA TA = 35 °C 3% NaCl (MIL Std Method 1009) 15 Gmax 1,000G 2000G 20N (middle of the card) NA 20N (border of the card) 254nm, 15Ws/cm2 Salt Water Spray Vibration (peak-to-peak) Shock Drop Bending UV light exposure 1. NA = Not Applicable; RH = Relative Humidity; ESD = ElectroStatic Discharge Table 5. Physical dimensions SD 24 32 MiniSD 20 21.5 MicroSD 11 15 Inter Connect Area 0.7±0.1 Unit mm mm Parameter Width Height Thickness 2.1 1.4 Max. Card Thickness 0.95 Max. Pull Area 1.0±0.1 mm Weight Number of Pins Approx. 2 9 Approx. 1 11 1,000,000hrs None 1 non-recoverable bit in 1014 bit read >2,000,000 Program/Erase Cycles 10/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Memory array partitioning 2 Memory array partitioning The basic unit of data transfer to/from the SD Memory Card is the Byte. The memory array is divided into several structures as described below and summarized in Table 17. Block The Block is the unit structure related to block-oriented read and write commands. Its size is the number of Bytes that are transferred when a block-oriented read or write command is sent by the host. The SD Memory Card Block size is either programmable or fixed. The information about allowed block sizes and programmability is stored in the CSD Register. The details of the Memory Array Structure and the number of addressable Blocks are shown in Table 17. Sector The sector is the unit structure related to the erase commands. Its size is the number of blocks that are erased at any one time. The sector size is fixed for each device. The information about the sector size (in blocks) is stored in the CSD register. Write Protect Group (WP-Group) The WP-Group is the smallest structure that may be individually protected. Its size is the number of Sectors that are Write Protected with one bit. The information about the Write Protect Group size is stored in the CSD Register. Table 7. Type of Structure Blocks Sector WP-Groups Memory array structures Number of structures in device Unit 512 Bytes Block Sector 32 MByte Devices 59776 128 1 64 MByte 128 MByte 256 MByte 512 MByte Devices Devices Devices Devices 122624 128 2 248320 128 4 499712 128 8 1002496 128 16 1 GByte Devices 1999872 128 32 11/61 Memory array partitioning Figure 1. Write Protection hierarchy Memory Card Write Protect Group 0 Sector 1 Block 1 SMSxxxAF, SMSxxxFF, SMSxxxBF Block 2 Sector 2 Sector 3 Write Protect Group 1 Write Protect Group 2 ai10041 12/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface 3 Secure digital memory card interface This section applies to the full-size SD Memory Card only, or to the MiniSD and MicroSD card when used with an adapter. Details on the 11-pin communication interface of the MiniSD card used without an adapter are still to be announced. Figure 3: MicroSD pin assignment shows the MicroSD pinout. The Secure Digital Memory Card has an advanced 9-pin communication interface (Clock, Command, 4 Data pins and 3 Power Supply pins) designed to operate in a low voltage range. The Secure Digital Card has its nine pins exposed on one side (see Figure 2). The signal/pin assignments are listed in Table 8 The pin types are Power Supply, Input, Output and Push-Pull. The signals include six communication lines CMD, DAT0, DAT1, DAT2, DAT3, CLK and three supply lines VDD, VSS1 and VSS2. Figure 2. Full size Secure Digital Memory Card form factor Write Enable (Up) 1 2 3 4 5 6 78 9 SD Memory Card Write Protect (Down) ai10029 Table 8. Pin # Full-size SD Memory Card pin assignment SD mode Name Type(1) I/O/PP(3) PP S S I S I/O/PP I/O/PP I/O/PP Description Card Detect / Data Line [Bit 3] Command/Response Supply voltage ground Supply voltage Clock Supply voltage ground Data Line [Bit 0] Data Line [Bit 1] Data Line [Bit 2] Name CS DI VSS VDD SCLK VSS2 DO Type I I S S I S SPI mode Description Chip Select (active Low) Data In Supply voltage ground Supply voltage Clock Supply voltage ground 1 2 3 4 5 6 7 8 9 CD/DAT3(2) CMD VSS1 VDD CLK VSS2 DAT0 DAT1 (2) O/PP Data Out Reserved Reserved DAT2(2) 1. S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers. 2. The extended DAT lines (DAT1-DAT3) are input on power-up. They start to operate as DAT lines after SET_BUS_WIDTH command. 3. After power-up this line is input with 50kW pull-up (can be used for card detection or SPI mode selection). The pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command. 13/61 Secure digital memory card interface Figure 3. MicroSD pin assignment SMSxxxAF, SMSxxxFF, SMSxxxBF Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Ai11728 Table 9. Pin MicroSD Contact Pad Assignment SD Mode Name Type(1) Description Name RSV CS DI VDD SCLK VSS DO RSV I I S I S O/PP Type SPI Mode Description Reserved Chip Select (neg true) Data In Supply voltage Clock Supply voltage ground Data Out Reserved 1 2 3 4 5 6 7 8 DAT2 CD/DA T3(2) CMD VDD CLK VSS DAT0 DAT1 I/O/PP Data Line [Bit 2] I/O/PP Card Detect / Data Line (3) [Bit 3] PP S I S Command/Response Supply voltage Clock Supply voltage ground I/O/PP Data Line [Bit 0] 1. S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers. 2. The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used. It is defined so, in order to keep compatibility to MultiMediaCards. 3. After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode selection). The pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command. 14/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface 3.1 Secure digital memory card bus topology The Secure Digital Memory Card system defines two alternative communications protocols: SD and SPI that correspond to two operating modes. Either mode can be selected in the application, mode selection is transparent to the host. The host automatically detects the operating mode of the card by issuing the Reset command (refer to Section 7.2.1: Mode Selection) and will expect all further communications to use the same mode. Therefore, applications that use only one communication mode do not have to be aware of the other. The SD bus includes the following signals: ● ● ● ● CLK: Host to card clock signal CMD: Bi-directional Command/Response signal DAT0 - DAT3: 4 Bi-directional data signals. VDD, VSS1, VSS2: Power and ground signals. The SD Memory Card bus has a synchronous star topology (refer to Figure 4: Secure Digital Memory Card system bus topology) with a single master (the application) and multiple slaves (the cards). The Clock, power and ground signals are common to all cards. The command (CMD) and data (DAT0 - DAT3) signals are dedicated to the cards, they provide continuous point-to-point connection to all the cards. During the initialization process, commands are sent to each card individually, allowing the application to detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to (from) each card individually. However, in order to simplify the handling of the card stack, after the initialization process, all commands may be sent concurrently to all cards. Addressing information is provided in the command packet. The SD bus allows dynamic configuration of the number of data lines. After power-up the SD Memory Card defaults to using only DAT0 for data transfer. After initialization the host can change the bus width (number of active data lines). This feature is an easy trade off between hardware cost and system performance. 15/61 Secure digital memory card interface Figure 4. SMSxxxAF, SMSxxxFF, SMSxxxBF Secure Digital Memory Card system bus topology HOST CLK VDD VSS DAT0-DAT3(A) CMD(A) CLK VDD VSS SD Memory Card (A) DAT0-DAT3 CMD CLK VDD VSS DAT0-DAT3(B) CMD(B) SD Memory Card (B) DAT0-DAT3 CMD CLK VDD MultiMediaCard VSS (C) DAT0, CS, CMD(1) DAT0-DAT3(C) CMD(C) ai10029 1. DAT1 and DAT2 not connected. 3.2 SD bus protocol Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit. ● Command: a command is a token which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). Commands are transferred serially on the CMD line. See Figure 5: "No Response" and "No Data" operations. The Command token format is shown in Figure 8 Response: a response is a token which is sent from an addressed card, or (simultaneously) from all connected cards, to the host, as an answer to a previously received command. Responses are transferred serially on the CMD line. A response is illustrated in Figure 5: "No Response" and "No Data" operations. The Response token format is shown in Figure 9 Data: data can be transferred from the card to the host or from the host to the card. Data is transferred via the data lines. See Figure 6: (Multiple) Block Read operation for an illustration. The Data Packet format is shown in Figure 10 ● ● Card addressing is implemented using a session address assigned to the card during the initialization phase (See SD Memory Card Specification, Chapter 4). The basic transaction on the SD bus is the command/response transaction. In this type of bus transactions, the information is directly transferred within the command or response structure. In addition, some operations have a data token. Data transfers to/from the SD Memory Card are done in blocks. Data blocks are always followed by CRC bits. Single and Multiple Block operations are supported. Note that the Multiple Block operation mode improves the speed of write operations. A Multiple Block transmission is terminated by issuing a STOP_TRANSMISSION command on the CMD line (See Figure 6 and Figure 7). 16/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface Data transfer can be configured by the host to use single or multiple data lines (provided that the card supports this feature). A busy signal on DAT0 is used to indicate that a Block Write operation is ongoing (see Figure 7). The same busy signaling is used regardless of the number of data lines used to transfer the data. Response tokens (see Figure 9) have four coding schemes depending on their content. The token length is either 48 or 136 bits (See SD Memory Card Specification, Chapter 4.5 for detailed definitions of the commands and responses). The CRC protection algorithm for data block is a 16-bit CCITT polynomial (see SD Memory Card Specification, chapter 4.5). On the CMD line, the MSB bit is transmitted first and the LSB bit last. When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 10). Start bits, End bits and CRC bits, are transmitted on all the DAT lines used. CRC bits are calculated and checked for every DAT line individually. The CRC status response and Busy indication are sent by the card to the host on DAT0 only (DAT1-DAT3 are Don’t Care). Figure 5. "No Response" and "No Data" operations from Host to Card CMD Command from Host to Card Command from Card to Host Response DAT Operation (no response) Operation (no data) ai10031 Figure 6. (Multiple) Block Read operation from Card to Host Command Response Data from Card to Host STOP_TRANSMISSION command stops data transfer Command Response from Host to Card CMD DAT Data Block CRC Block Read operation Data Block CRC Data Block CRC Data Stop operation Multiple Block Read operation ai10032 17/61 Secure digital memory card interface Figure 7. (Multiple) Block Write operation from Card to Host Command Response Data from Host to Card SMSxxxAF, SMSxxxFF, SMSxxxBF from Host to Card CMD CRC all right response STOP_TRANSMISSION command and busy stops data transfer from Card Response Command DAT Data Block CRC Block Write operation busy Data Block CRC busy Data Stop operation Multiple Block Write operation ai10033 Figure 8. Command Token format Transmitter Bit '1' = command from Host Start Bit always '0' Command content: command and address information or parameter, protected by 7 bit CRC checksum End bit always '1' 01 CONTENT Total Length = 48 bits CRC 1 ai10034 Figure 9. response token format Response content: mirrored command and status information (R1 response), OCR Register (R3 response) or RCA (R6 response)protected by 7 bit CRC checksum End bit always '1' Transmitter Bit '0' = Card response Start Bit always '0' R1, R3, R6 00 CONTENT Total Length = 48 bits CRC 1 End bit always '1' R2 00 CONTENT = CID or CSD Total Length = 136 bits CRC 1 ai10035b 18/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Figure 10. Data Packet format MSB (bit 4095) Start Bit always '0' Secure digital memory card interface LSB (bit 0) End bit always '1' Standard bus (only DAT0 used) 0 CONTENT Block Length MSB Number CRC 1 LSB Number End bit always '1' Start Bit always '0' DAT3 0 4095 CONTENT 3 CRC 1 DAT2 Wide bus (all four data lines used) DAT1 0 4094 CONTENT 2 CRC 1 0 4093 CONTENT 1 CRC 1 DAT0 0 4092 CONTENT Block Length / 4 0 CRC 1 ai10036b 3.3 SD Memory Card Functional Description All communications between the host and the cards are controlled by the host (master). The host sends commands of two types: ● ● Broadcast commands which are intended for all cards. Some of these commands require a response. Addressed (point-to-point) commands that are sent to the addressed card and are followed by a response from the card. 3.4 Operation Modes Figure 11 and Figure 12 show an overview of the command flow for the Card Identification mode and the Data Transfer mode, respectively. Table 10 shows the relationship between operation modes and card states. Each state in the SD Memory Card state diagram (see Figure 16 and Figure 17) is associated with one operation mode. Table 10. Card States vs. Operation Modes Card state Inactive State Idle State Ready State Identification State Card Identification Mode Inactive Operation mode 19/61 Secure digital memory card interface Table 10. SMSxxxAF, SMSxxxFF, SMSxxxBF Card States vs. Operation Modes (continued) Card state Operation mode Stand-by State Transfer State Sending-data State Data Transfer Mode Receive-data State Programming State Disconnect State 3.4.1 Card Identification Mode The host enters the Card Identification mode after reset and remains in this mode until it has finished searching for new cards on the bus. Cards enter the Card Identification mode after reset and remain in this mode until they receive the SEND_RCA command (CMD3) (or the SET_RCA command for MultiMediaCards). While in Card Identification mode the host resets all the cards that are in Card Identification mode, validates the operation voltage range, identifies every card and asks them to publish their Relative Card Addresses (RCA). This operation is done separately for each card on its own CMD line. In this mode, all data communications use the command line (CMD) only. The host starts the card identification process at the identification clock rate fOD. The SD Memory Card has push-pull CMD line output drives. Once the bus has been activated the host asks each card to send their valid operation conditions (ACMD41 preceded by APP_CMD - CMD55 with RCA=0000h). The response to ACMD41 is the Operation Condition Register of the card. The same command is sent to all the new cards in the system. Incompatible cards are switched to Inactive State. The host then issues the ALL_SEND_CID command (CMD2), to every card to get their unique card identification (CID) numbers. All unidentified cards (which are in Ready State) answer by sending their CID numbers (on the CMD line) and switch to the Identification State. Then the host issues a CMD3 (SEND_RELATIVE_ADDR) command to ask the cards to publish a relative card address (RCA). The RCA is shorter than the CID, and will be used to address the card (typically at a clock rate higher than fOD) once this is in Data Transfer mode. Once the RCA is received the card state changes to Standby. At this point, the host may ask the card to publish another RCA number by sending another SEND_RELATIVE_ADDR command to the card. The last published RCA is the actual RCA of the card. The host repeats the identification process, that is the cycles with CMD2 and CMD3, for each card in the system. Once all the SD Memory Cards have been initialized, the host initializes the MultiMediaCards that are in the system (if any) by issuing CMD2 and CMD3 as explained in the MultiMediaCard specification. Note that in the SD system all the cards are connected separately so each MultiMediaCard has to be initialized individually. 20/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface Figure 11. SD Memory Card State Diagram (Card Identification Mode) Power-on SPI Operation Mode CMD0 + CS asserted Card is busy or host omitted voltage range Idle State (Idle) CMD0 from all states except for (ina) ACMD41 No response (invalid command), must be a MultiMediaCard Start MultiMediaCard initialization process starting at CFM1 Ready State (ready) Card with incompatible voltage range Inactive State (ina) CMD15 CMD2 Identification State (ident) Card responds with new RCA Card Identification mode CMD3 Data Transfer mode Stand-by State (stby) CMD0 Card Responds with new RCA from all states in Data Transfer mode ai10037 3.4.2 Data Transfer Mode Cards enter the Data Transfer mode once their Relative Card Addresses (RCA) have been published. The host enters the Data Transfer mode after identifying all the cards on the bus. The host issues SEND_CSD (CMD9) to obtain the contents of the Card Specific Data (CSD) Register for each card. The CSD Register contains information like the block length and the card storage. Until the host knows the contents of all the CSD Registers, the fPP clock rate must remain at fOD because some cards may have operating frequency limitations. The broadcast command SET_DSR (CMD4) configures the driver stages of all identified cards. It programs their Driver Stage Registers (DSR) according to the application bus layout (length), the number of cards on the bus and the data transfer frequency. The clock rate is changed from fOD to fPP at that point. The SET_DSR command is an option for the card and the host. CMD7 is used to select one card and switch it to the Transfer State. Only one card can be in Transfer State at a given time. If a previously selected card is still in Transfer State when the host uses CMD7 to switch another card to the Transfer state, then the connection between the previously selected card and the host is released and the card reverts to the Standby State. 21/61 Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF When CMD7 is issued with the reserved relative card address "0000h", all cards revert to the Standby State. This function may be used before identifying new cards, to avoid resetting already registered cards. When in Standby state the cards that already have an RCA do not respond to identification commands (CMD41, CMD2, CMD3). Note that a card is deselected when it receives a CMD7 with an RCA that does not match. Card deselection is automatic if another card in a system is selected and the cards share the same CMD lines. So, in an SD Memory Card system, the host may either have a common CMD line for all SD Memory Cards (in which case card deselection is automatic just like in a MultiMediaCard system) or the host may have separate CMD lines, in which case it must be aware of the necessity of deselecting cards. All data communications in the Data Transfer Mode are point-to point between the host and the selected card (using addressed commands). All addressed commands are acknowledged by a response on the CMD line. The relationships between the various states in the Data Transfer mode are summarized below (see Figure 12): ● All Data Read commands (CMD17, CMD18, CMD30, CMD56, ACMD51) can be aborted at any time using the Stop command (CMD12). The data transfer will terminate and the card will return to the Transfer State. All Data Write commands (CMD24,CMD25, CMD26, CMD27, CMD42, CMD56) can be aborted at any time using the Stop command (CMD12). The write commands must be stopped prior to deselecting the card using CMD7. As soon as the data transfer has completed, the card switches from the Data Write state to either the Programming state (if the transfer was successful) or the Transfer state (if the transfer failed). If a Block Write operation is stopped and the block length and CRC of the last block are valid, the data will be programmed. The card can provide buffering during Block Write. This means that the data to be programmed to the next block can be sent to the card while the previous block is being programmed. ● ● ● ● If all write buffers are full, the DAT0 line will remain Low (BUSY) as long as the card is in the Programming state (see Figure 12). ● There is no buffering option for Write CSD, Write CID, Write Protection and erase. This means that while the card is busy with any one of these commands, no other Data Transfer command will be accepted. The DAT0 line will remain Low as long as the card is busy and in the Programming state. Parameter Set commands (CMD16, CMD32, CMD33) are not allowed while the card is programming. Read commands are not allowed while the card is programming. Switching another card from the Standby to the Transfer state (using CMD7) will not terminate erase and programming operations. The card will switch to the Disconnect state and release the DAT line. A card in the Disconnect state can be reselected using CMD7. The card will then revert to the Programming state and reactivate the busy signaling. Resetting a card (using CMD0 or CMD15) will terminate any pending or ongoing programming operation. This may result in the loss of card contents. It is up to the host to prevent possible data loss. ● ● ● ● ● 22/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface Figure 12. SD Memory Card State Diagram (Data Transfer Mode) CMD3 Card Identification mode Data Transfer mode CMD15 CMD0 from all states in Data Transfer mode CMD13, CMD55 no state transition in Data Transfer mode Sending Data State (data) CMD12, "Operation Complete" Transfer State (tran) CMD17,CMD18 CMD30,CMD56(r) ACMD51 CMD7 Standby State (stby) CMD7 CMD4, CMD9 CMD10 "Operation Complete" CMD7 Disconnect State (dis) CMD7 CMD28, CMD29 CMD38 "Operation Complete" CMD24,CMD25 CMD26,CMD27 CMD42,CMD56(w) Receive Data State (rcv) Programming State (prg) CMD12 or Transfer End ai10038 3.5 Commands Four types of commands are used to control the SD Memory Card: 1. Broadcast commands (bc), no response: The broadcast feature is available only if all the CMD lines are interconnected at the level of the host. If they are not interconnected then each individual card will accept the command in turn. Broadcast commands with response (bcr): Since there is no Open Drain mode in SD Memory Cards, this type of command is used only if the host does not use a common CMD line. The command is accepted by every individual Card and the responses from all cards are sent simultaneously. addressed (point-to-point) commands (ac): There is no data transfer on DAT. addressed (point-to-point) data transfer commands (adtc): There is a data transfer on DAT. 2. 3. 4. All commands have a fixed code length of 48 bits for a transmission time of 2.4µs at 20MHz. All commands and responses are sent over the CMD line of the SD Memory Card. Command transmission always starts with the most significant bit (MSB) of the command codeword. All commands are protected by a CRC. All Command codewords are terminated by the end bit (always '1'). Table 11 shows the command format. All commands and their arguments are specified in the SD Memory Card Specification. 23/61 Secure digital memory card interface Table 11. Bit position Width Value Description SMSxxxAF, SMSxxxFF, SMSxxxBF SD Card Command Format 47 1 '0 Start bit 46 1 ''1 Transmission bit 45:40 6 'x Command index 39:8 32 x Argument 7:1 7 x CRC7 0 1 '1' End bit 3.6 Responses All responses are sent via the command line CMD. Response transmission always starts with the leftmost bit of the response codeword. The code length depends on the response type. A response always starts with a start bit (always '0'), followed by the bit indicating the direction of transmission (from card = '0'). A value denoted by 'X' in Table 12, Table 13, Table 14 and Table 15 indicates a variable entry. All responses (except for R3 Responses) are protected by a CRC. All response codewords are terminated by the end bit (always '1'). There are five types of responses. Their formats are defined as follows: 1. R1 (normal response command): the code length is 48 bits. Bits 45 to 40 indicate the index of the command to respond to. The index is a binary coded number (between 0 and 63). The status of the card is coded in 32 bits (see Table 12). Note that if data transfer to the card takes place, then a busy signal may appear on the data line after the transmission of each block of data. The host has to check for busy after data block transmission. 2. R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands, depending on the state it was in prior to receiving the command. The Host has to check for busy in the response. R2 (CID, CSD Register): the code length is 136 bits. The contents of the CID Register are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD Register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD Registers are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response (see Table 13). R3 (OCR register): the code length is 48 bits. The contents of the OCR register are sent as a response to ACMD41 (see Section Table 14. on page 25). R6 (Published RCA response): the code length is 48 bits. Bits 45 to 40 indicate the index of the command to respond to. In this case it is '000011' (together with bit 5 in the status bits it means = CMD3) as shown in Table 15 The 16 MSB bits of the argument field are used for the Published RCA number. 3. 4. 5. For more details about Response formats, please refer to the SD Memory Card Specification. 24/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 12. Bit Position Width (bits) Value Description Secure digital memory card interface Response R1 47 1 ‘0’ Start Bit 46 1 ‘0’ Transmission Bit [45:40] 6 X Command Index [39:8] 32 X Card Status [7:1] 7 X CRC7 0 1 ‘1’ End Bit Table 13. Bit Position Width (bits) Value Description Response R2 135 1 ‘0’ Start Bit 134 1 ‘0’ Transmission Bit [133:128] 6 ‘111111’ Reserved [127:1] 127 X CID or CSD register incl. internal CRC7 0 1 ‘1’ End Bit Table 14. Bit Position Width (bits) Value Description Response R3 47 1 ‘0’ Start Bit 46 1 ‘0’ Transmission Bit [45:40] 6 ‘111111’ Reserved [39:8] 32 X OCR Register [7:1] 7 ‘111111’ Reserved 0 1 ‘1’ End Bit Table 15. Bit Position Width (bits) Value Description Response R6 47 1 ‘0’ Start Bit 46 1 ‘0’ Transmissio n Bit [45:40] 6 X Command Index (‘000011’) [39:8] Argument Field 16 X New published RCA [31:16] of the card 16 X [15:0] Card Status Bits: 23, 22, 19 and 12 to 0 [7:1] 7 X CRC7 0 1 ‘1’ end bit 25/61 SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF 4 4.1 SD memory card hardware interface SD memory card bus circuitry Figure 13 shows the internal bus circuitry required for the Full Size SD Memory Card. The SD Memory Card may also feature two additional contacts, that are not part of the internal circuitry. When present in the device, these contacts are located at the level of the Write Protect/Card Detect switch in the socket, and should be connected as illustrated in Figure 13. When DAT3 is used for card detection, the RDAT resistor connected to DAT3 should be disconnected and another resistor should be connected to Ground. RDAT and RCMD are pull-up resistors used to protect the DAT and CMD lines, respectively, against bus floating when no card is inserted or when all card drivers are high impedance. RWP is used to protect the Write Protect/Card Detection switch. Figure 13. Full Size SD Memory Card Circuitry VDD RDAT VDD RCMD VDD RWP Write Protect CMD DAT0-DAT3 SD Memory Card Host C1 C2 C3 9 12345678 SD Memory Card CLK VSS ai10042 26/61 SMSxxxAF, SMSxxxFF, SMSxxxBF SD memory card hardware interface 4.2 Power-Up The power-up of the SD Memory Card bus is handled locally in each SD Memory Card and in the bus master. After power-up (or after hot insertion) the SD Memory Card enters the Idle state. When in this state, the SD Memory Card ignores all bus transactions until ACMD41 is received (ACMD command type should always be preceded by CMD55). ACMD41 is a special synchronization command used to negotiate the operating voltage range and to poll the cards until they are out of their power-up sequence. In addition to the operating voltage profile of the cards, the response to ACMD41 contains a busy flag that indicates that the power-up sequence has not completed and the card is not ready for identification. The host has to wait (and continue polling the cards in turn) until the bit is cleared (‘0’). The power-up sequence of an individual card should not exceed 1 second. After power-up the host starts the clock and sends the initializing sequence on the CMD line. This sequence is a contiguous stream of logical 1's. It does not exceed 1ms, 74 clocks or the supply-ramp-up-time. Note that the maximum duration is fixed to 74 clocks which is ten clock cycles more than the 64 clocks after which the card is normally ready for communication to eliminate all power-up synchronization problems. Figure 14. Power-Up Diagram Supply voltage VDDmax Bus master supply voltage Valid voltage range for CMD0, CMD15, CMD55 and ACMD41 commands Valid voltage range for all other commands and memory access VDDmin Power up Supply ramp up time time Initialization sequence Initialization delay(1) Time out value for initialization process(2) ACMD NCC ACMD NCC ACMD NCC CMD2 41 41 41 Optional repetitions of ACMD41, until no card responds with the busy bit set. time ai10043 1. Initialization delay = 1ms (max) + 74 clock cycles + supply ramp-up time. 2. Timeout value for initialization process is 1s. 27/61 SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF 4.3 Hot Insertion/Removal To guarantee a reliable initialization during hot insertion, some measures must be taken on by the host. For example, a special hot-insertion capable card connector may be used to guarantee the sequence of the card pin connection. The card contacts are connected in three steps: 1. 2. 3. Ground VSS (pin 3) and supply voltage VDD (pin 4). CLK, CMD, DAT0, DAT1, DAT2 and VSS (pin 6). CD / DAT3 (pin 1). Pins 3 and 4 should be connected first on insertion, and be disconnected last on extraction. Another method is a switch which could ensure that the power is switched on only after all card pads are connected. Inserting a Card in or removing it from the SD Memory Card bus with the power on will not damage the card. Data transfer operations are protected by CRC codes, therefore any bit changes induced by card insertion and removal can be detected by the SD Memory Card bus master. ● ● ● The inserted card must be properly reset even when the clock frequency is fPP. Each card should be fitted with a protection from the power supply to prevent damage to the card (and host). Data transfer failures induced by removal/insertion are detected by the bus master. They must be corrected by the application, which may repeat the issued command. 4.4 Power Protection Cards have to be inserted in or removed from the bus without being damaged. If one of the supply pins (VDD or VSS) is not connected properly, then the current is drawn through a data line. All the card outputs should also be able to withstand shortcuts to either supply. If the hot insertion feature is implemented in the host, then the host has to be able to withstand an instant shortcut between VDD and VSS without being damaged. 4.5 Electrical Specifications Table 16 defines the Bus Operating Conditions for the SD Memory Card. The total capacitance CL of the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS and the capacitances CCARD of all the cards connected to this line. CL = CHOST + CBUS + N × CCARD, where: ● N is the number of cards connected to the line. ● ● CHOST + CBUS must be lower than 30pF for up to 10 cards and lower than 40pF for up to 30 cards. The values in Table 16 should not be exceeded. As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. See Figure 15: Bus Signal levels and Table 17: Bus Signal Condition - I/O Signal Voltages. 28/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 16. Symbol SD memory card hardware interface Bus Operating Conditions Parameter Peak voltage on all lines Input Leakage Current Output Leakage Current Min − 0.3 − 10 − 10 2.0 Max. VDD+0.3 10 10 3.6 Unit V A A V Remark VDD Supply voltage Supply voltage specified in OCR register VSS1, VSS2 Supply voltage differentials power-up time RCMD, RDAT Pull-up resistance − 0.3 0.3 250 V ms KΩ pF pF pF nH KΩ fPP < 20MHz fPP < 5MHz 21 Cards fPP < 20MHz 21 Cards 10 100 250 CL Bus signal line capacitance 100 CCARD Single Card capacitance Maximum signal line Inductance 10 16 10 90 RDAT3 Pull-up resistance inside card (pin1) Figure 15. Bus Signal levels V VDD High Input Level VOH VIH Undefined VIL Low Input Level VOL VSS Low Output Level t ai10044 High Output Level Table 17. Symbol VOH VOL VIH VIL Bus Signal Condition - I/O Signal Voltages Parameter HIGH Output voltage LOW Output voltage HIGH Input voltage LOW Input voltage Conditions IOH = − 100µA at VDD min IOL = 100µA at VDD min 0.625VDD VSS −0.3 Min 0.75VDD 0.125VDD VDD + 0.3 0.25VDD Max. Unit V V V V 29/61 SD memory card hardware interface Figure 16. Data Input/Output Timings Referenced to Clock tKLKL tKLKH SMSxxxAF, SMSxxxFF, SMSxxxBF tKHKL tf tQVKH tr tKHQX VALID Input tKLDV tKLDX VALID ai10045 Output Table 18. Symbol tKLKL fOD Bus Timings (1) Alt fPP Parameter Clock frequency Data Transfer Mode Clock Frequency Identification Mode (the low frequency is required for MultiMediaCard compatibility). tWL Clock low time Condition CL = 100pF (7 cards) CL = 250pF (21 cards) CL = 100pF (7 cards) CL = 250pF (21 cards) Clock high time CL = 100pF (7 cards) CL = 250pF (21 cards) Clock rise time CL = 100pF (7 cards) CL = 250pF (21 cards) Clock fall time CL = 100pF (7 cards) CL = 250pF (21 cards) Min 0 0 10 50 10 50 10 50 10 50 Max. 25 400 Unit MHz kHz ns ns ns ns ns ns ns ns tKLKH tKHKL tWH tr tTLH tf tTHL Inputs CMD, DAT (referenced to CLK) tQVKH tKHQX tISU tIH Input set-up time Input hold time CL = 25pF (1 card) CL =25pF (1 card) 5 5 ns ns Outputs CMD, DAT (referenced to CLK) tKLDX tKLDV tODLY Output Delay time CL =25pF (1 card) 14 ns 1. Clock CLK: All values are referred to min (VIL) and max (VIH). 30/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Card registers 5 Card registers Six registers are defined in the card interface: OCR, CID, CSD, RCA, DSR and SCR. See Table 19 for a description. The registers are accessed by using the corresponding commands. The OCR, CID, CSD and SCR registers contain the card/content specific information, whereas the RCA and DSR registers are configuration registers that store the actual configuration parameters. For more details about the register structure, please refer to the SD Memory Card Specification v.1.01. Table 19. Name CID SD Memory Card Registers Width 128 Description Card IDentification number register. It contains the card’s individual identification number. It is mandatory. Relative Card Address register. It contains the local system address of the card, that is dynamically suggested by the card and approved by the host during initialization. It is mandatory. Driver Stage Register. It is used to configure the card's output drivers. It is optional. Card Specific Data register. It contains the information about the card’s operation conditions. It is mandatory. SD Configuration Register. It contains the information about the SD Memory Card's Special Feature capabilities. It is mandatory Operation Condition Register. It is mandatory. RCA(1) 16 DSR CSD SCR OCR 16 128 64 32 1. The RCA Register is not used (available) in SPI mode. 5.1 OCR Register The 32-bit Operation Conditions Register contains the VDD voltage profile of the card. It also includes a status information bit that goes High (set to ‘1’) once the card power-up sequence has completed. The OCR register is used by the cards that do not support the full operating voltage range of the SD Memory Card bus, or by cards whose power-up sequence does not match the definition given in Figure 14: Power-Up Diagram. Table 20. OCR Register Definition VDD Voltage Range reserved 1.6V to 1.7V 1.7V to 1.8V 1.8V to 1.9V 1.9V to 2.0V 2.0V to 2.1V OCR Bit Position 0-3 4 5 6 7 8 31/61 Card registers Table 20. OCR Register Definition (continued) SMSxxxAF, SMSxxxFF, SMSxxxBF OCR Bit Position 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24-30 31 2.1V to 2.2V 2.2V to 2.3V 2.3V to 2.4V 2.4V to 2.5V 2.5V to 2.6V 2.6V to 2.7V 2.7V to 2.8V 2.8V to 2.9V 2.9V to 3.0V 3.0V to 3.1V 3.1V to 3.2V 3.2V to 3.3V 3.3V to 3.4V 3.4V to 3.5V 3.5V to 3.6V reserved VDD Voltage Range Card Power-up Status bit (busy). This bit is Low during the card power-up routine. It goes High on completion 5.2 CID Register The Card IDentification (CID) Register contains the card identification information used during the card identification phase. Each Flash memory card should have a unique identification number. The structure of the CID register is defined in Figure 16. Table 21. CID Fields Name Manufacturer ID OEM/Application ID Product name Product revision Product serial number Reserved Manufacturing date CRC7 checksum not used, always '1’ Field MID OID PNM PRV PSN -MDT CRC -Width 8 16 40 8 32 4 12 7 1 CID-slice [127:120] [119:104] [103:64] [63:56] [55:24] [23:20] [19:8] [7:1] [0:0] 32/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Card registers 5.3 CSD Register The Card Specific Data Register provides information on how to access the card contents. The CSD Register defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable register parameters (entries with cell type W or R, listed in Table 22) can be changed using CMD27. Table 22. CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11 Name Field CSD_STRUCTURE TAAC NSAC TRAN_SPEED CCC READ_BL_LEN READ_BL_PARTIAL WRITE_BLK_MISALIGN READ_BLK_MISALIGN DSR_IMP C_SIZE VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT ERASE_BLK_EN SECTOR_SIZE WP_GRP_SIZE WP_GRP_ENABLE R2W_FACTOR WRITE_BL_LEN WRITE_BL_PARTIAL FILE_FORMAT_GRP COPY PERM_WRITE_PROTECT Width 2 6 8 8 8 12 4 1 1 1 1 2 12 3 3 3 3 3 1 7 7 1 2 3 4 1 5 1 1 1 Cell Type(1) R R R R R R R R R R R R R R R R R R R R R R R R R R R R/W(1) R/W(1) R/W(1) CSD-slice [127:126] [125:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79:79] [78:78] [77:77] [76:76] [75:74] [73:62] [61:59] [58:56] [55:53] [52:50] [49:47] [46:46] [45:39] [38:32] [31:31] [30:29] [28:26] [25:22] [21:21] [20:16] [15:15] [14:14] [13:13] CSD structure reserved data read access-time-1 data read access-time-2 in CLK cycles (NSAC*100) Max. data transfer rate card command classes Max. read data block length partial blocks for read allowed write block misalignment read block misalignment DSR implemented reserved device size Max. read current @VDD min Max. read current @VDD max Max. write current @VDD min Max. write current @VDD max device size multiplier erase single block enable sector size write protect group size write protect group enable reserved for MultiMediaCard compatibility write speed factor Max. write data block length partial blocks for write allowed reserved File format group copy flag (OTP) permanent write protection 33/61 Card registers Table 22. SMSxxxAF, SMSxxxFF, SMSxxxBF CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11 Name Field TMP_WRITE_PROTECT FILE_FORMAT CRC Width 1 2 2 7 1 Cell Type(1) R/W R/W(1) R/W R/W CSD-slice [12:12] [11:10] [9:8] [7:1] [0:0] temporary write protection File format reserved CRC not used, always'1 1. R = readable, W(1) = can be written once, W = can be written several times. 5.4 RCA Register The writable 16-bit Relative Card Address Register contains the card address published by the card during the identification phase. This address is used for addressed host-card communications after the card identification phase. The default value of the RCA register is 0000h. This value is reserved, the CMD7 command uses it to set all the cards to the Standby state. 5.5 DSR Register (Optional) The 16-bit Driver Stage Register is not used in Numonyx Cards. 5.6 SCR Register The SD Card Configuration Register (SCR) is a configuration register. The SCR provides information on the special features that are configured in the SD Memory Card. The size of SCR Register is 64 bit. This register is programmed in the factory by the SD Memory Card manufacturer. Table 23 describes the SCR contents. Table 23. SCR Fields Description Field SCR_STRUCTURE SD_SPEC DATA_STAT_AFTER_ERASE SD_SECURITY SD_BUS_WIDTHS Width 4 4 1 3 4 16 32 Cell Type(1) R R R R R R R SCR Slice [63:60] [59:56] [55:55] [54:52] [51:48] [47:32] [31:0] SCR Structure SD Memory Card - Specification. Version data_status_after erases SD Security Support DAT Bus width supported reserved reserved for manufacturer usage 1. R = readable. 34/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Timings 6 Timings The symbols listed in Table 24 are used in all timing diagrams. The difference between P-bits and Z-bits is that P-bits are actively driven to High by the card or the host output driver whereas Z-bits are driven to High and kept High by the pull-up resistors RCMD and RDAT. P-bits, which are actively driven High, are less sensitive to noise. All timing values are defined in Table 25 Table 24. Symbol S T P E Z D X * CRC Start bit (= ‘0’) Transmitter bit (Host = '1', Card = '0') One-cycle pull-up (= '1') End bit (=1) High impedance state (-> = '1') Data bits Don't Care data bits (from card) Repetition Cyclic redundancy check bits (7 bits) Timing Diagram Symbols Description Card active Host active 6.1 Command and Response The host command and the card response are both clocked out on the rising edge of the host clock. 6.1.1 Card Identification and Operating Conditions Timings The timings for CMD2 (ALL_SEND_CID) and ACMD41 are shown in Figure 17 The command is followed by two Z-bits (to leave time for the bus to switch direction) and then by P-bits pushed up by the responding card. The card response to the host command starts after NID clock cycles. 35/61 Timings Figure 17. Identification Sequence Host Command CMD S T CONTENT CRC E Z NID Cycles Z P *** P S T SMSxxxAF, SMSxxxFF, SMSxxxBF CID or OCR CONTENT Z Z Z ai10046 6.1.2 Card Relative Address Timings The SD Memory Card timings for CMD3 (SEND_RELATIVE_ADDR) are given in Figure 18. The minimum delay between the host command and the card response is NCR clock cycles. Figure 18. SEND_RELATIVE_ADDRESS Command Host Command CMD S T CONTENT CRC E Z NCR Cycles Z P *** P S T Response CONTENT CRC E Z Z Z ai10047 6.1.3 Data Transfer Mode After publishing its RCA the card switches to the Data Transfer mode. The command is followed by two Z-bits (to leave time for the bus to switch direction) and then by P-bits pushed by the responding card as shown in Figure 19. The timing diagram presented in Figure 19 applies to all host commands followed by card responses, and to ACMD41 and CMD2 commands. Figure 19. Response (Data Transfer Mode) Host Command CMD S T CONTENT CRC E Z NCR Cycles Z P *** P S T Response CONTENT CRC E Z Z Z ai10047 6.1.4 Last Card Response, Next Host Command Timings After receiving the last card response, the host can start the next command transmission after NRC clock cycles as shown in Figure 20. The timing diagram presented in Figure 20 applies to any host command. Figure 20. Response End To Next CMD Start (Data Transfer Mode) Response CMD S T CONTENT CRC E Z NRC Cycles ****** Z S T Host Command CONTENT CRC E ai10048 36/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Timings 6.1.5 Last Host Command, Next Host Command Timings The host can send a new command NCC clock cycles after sending the previous one as shown in Figure 21. Figure 21. Command Sequence (All Modes) Host Command CMD S T CONTENT CRC E Z NCC Cycles ****** Z S T Host Command CONTENT CRC E ai10049 6.2 6.2.1 Data Read Single Block Read The host selects one card for the data read operation by issuing CMD7, and sets the valid block length for oriented data transfer by issuing CMD16. Figure 22 shows the timings for a basing bus read operation. The sequence starts with a Single Block Read command (CMD17) which specifies the start address in the argument field. The response is sent on the CMD line. Data transmission from the card starts NAC after the end bit of the read command, where NAC is the access time. CRC check bits are appended to the data bits to allow the host to check for transmission errors. Figure 22. Single Block Read Command Host Command CMD S T CONTENT CRC E Z NCR Cycles Z P *** P S T Response CONTENT CRC E NAC Cycles DAT Z Z Z **** Z Z Z Z Z Z P ********** P S Read Data DDD *** ai10050 6.2.2 Multiple Block Read In Multiple Block Read mode, the card responds to the read command from the host by sending a continuous flow of data blocks. The data flow is terminated by a STOP_TRANSMISSION command (CMD12). Figure 23 describes the Multiple Block Read command followed by the data blocks and Figure 24, the response to a STOP_TRANSMISSION command. The data transmission stops two clock cycles after the end bit of the STOP_TRANSMISSION command. 37/61 Timings Figure 23. Multiple Block Read Command Host Command CMD ST CONTENT NCR Cycles Response CONTENT SMSxxxAF, SMSxxxFF, SMSxxxBF CRC E Z Z P * P S T NAC Cycles CRC E Z Z P P P P P P P P P P P P P NAC Cycles CRC E P ******* Read Data PS DDD DD ai10051 Read Data PS CONTENT DAT ZZZ **** Z Z ZZZ ZP ******* Figure 24. STOP_TRANSMISSION Command (CMD12, Data Transfer Mode) Host Command CMD S T CONTENT CRC E Z NCR Cycles Z P *** P S T Response CONTENT CRC E DAT DDD ******** D D D E Z Z ******************** ai10052 6.3 6.3.1 Data Write Single Block Write The host selects one card for the data write operation by issuing CMD7. The host sets the valid block length for block oriented data transfer by issuing CMD16. Figure 25 shows the timings of a basic bus write operation. The sequence starts with a Single Block Write command (CMD24) which determines (in the argument field) the start address. The card responds on the CMD line. Data transfer from the host starts NWR clock cycles after the card response is received. CRC check bits are appended to the data sent by the host to allow the card to check for transmission errors. The card returns the CRC check result as a CRC status token on the DAT0 line. If a transmission error occurred, the card returns a negative CRC status ('101'). If the transmission completed successfully, the card returns a positive CRC status ('010') and starts programming the data. If an error occurred while programming the Flash memory, the card ignores all further data blocks. In this case the card will not send any CRC response and so, there will be no CRC start bit on the bus and the three CRC status bits will read ('111'). Note that the CRC response is always output two clock cycles after the data. If the card does not have any Data Receive buffer available, it indicates this condition by pulling the DAT0 data line to Low. It will stop pulling DAT0 to Low as soon as at least one Data Receive buffer for the defined data transfer block length becomes available. The level of DAT0 does not give any information about the data write status. The host can obtain this information by issuing a CMD13 (SEND_STATUS) to the card. 38/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Figure 25. Block Write Command Host Command CMD NCR Card Response ****************** Write Data Timings E Z Z P * P S T CONTENT CRC E Z Z P NWR PPPPPPPP CRC Status Busy DAT0 DAT1-DAT3 Z Z ******* Z Z Z Z Z ******* Z Z Z *** *** Z Z Z Z P*P S Z Z Z Z P*P S CONTENT CRC E Z Z S Status E S L * L E Z CONTENT CRC E Z Z X X X X X X X X X Z ai10053 6.3.2 Multiple Block Write In Multiple Block Write mode, the write command from the host is followed by a continuous flow of data blocks from the host. The data flow is terminated by a STOP_TRANSMISSION command (CMD12). As in the case of a Single Block Write operation, CRC check bits are appended to the data sent to allow the card to check for transmission errors. The card returns the CRC check result as a CRC status token on the DAT0 line. If a transmission error occurred, the card returns a negative CRC status ('101'). If the transmission completed successfully, the card returns a positive CRC status ('010') and starts programming the data. If an error occurred while programming the Flash memory, the card ignores all further data blocks. In this case the card will not send any CRC response and so, there will be no CRC start bit on the bus and the three CRC status bits will read ('111'). Figure 26 describes a Multiple Block data transmission with and without a card busy signal. Figure 26. Multiple Block Write Command Card Response CMD EZ Z P NWR DAT ****************** Write Data PPPPP NWR ****************** Write Data PPPPPPPPP Busy NWR CRC Status CRC Status Z Z P * P S Data+CRC E Z Z S Status E Z P * P S Data+CRC E Z Z S Status E S L * L E Z P * P ai1005 6.4 STOP_TRANSMISSION Command The STOP_TRANSMISSION command works in the same way as in the read mode. Figure 27 to Figure 30 describe the timings of the STOP_TRANSMISSION command in different card states. The card will consider that a data block was successfully received and is ready for programming only if the CRC data of the block was validated and the CRC status token, returned to the host. Figure 28 is an example of an interrupted (by a STOP_TRANSMISSION command from the host) attempt to transmit the CRC status token. The result is the same as in other examples 39/61 Timings SMSxxxAF, SMSxxxFF, SMSxxxBF where the STOP_TRANSMISSION command is implemented: the end bit of the STOP_TRANSMISSION command from the host is followed, on the data line, by one more data bit, then an end bit and two Z-bits. The two Z-bits, which correspond to two clock cycles, are used to switch the bus direction. The received data block is considered incomplete and will not be programmed. In the previous Stop Transmission examples, the host stopped the data transmission during an active data transfer. In Figure 29 and Figure 30 the STOP_TRANSMISSION command is received by the card after all the data blocks have been sent. In Figure 29, the card is busy programming the last block when the STOP_TRANSMISSION command is received whereas in Figure 30 the card is idle but the input buffers still contain data blocks to be programmed. In the second case, the card starts programming the blocks upon reception of the STOP_TRANSMISSION command and activates the busy signal. Figure 27. STOP_TRANSMISSION During Data Transfer From The Host Host Command CMD S T CONTENT CRC E Z Z P NCR Cycles P ****** P ST Card Response CONTENT CRC E Host Command ST CONTENT Card is programming DAT DDDDDDDDDDEZ ZSL ********************** E Z Z Z Z Z Z ZZ ai09518 Figure 28. STOP_TRANSMISSION During CRC Status Transfer From Card Host Command CMD S T CONTENT CRC E Z Z P Data Block DAT CRC Status (1) NCR Cycles P****** P Card Response S T CONTENT CRC E Host Command S T CONTENT Card is programming ********************** EZZZZZZZZ ai10062 D D D D D Z Z S Status E Z Z S L 1. The card CRC status response was interrupted by the host. Figure 29. STOP_TRANSMISSION Received After Last Data Block with Card Busy Programming Host Command NCR Cycles Card Response Host Command S T CONTENT CMD S T CONTENT CRC E Z Z P * * * P S T CONTENT CRC E Card is programming DAT SL ************************************** LEZZZZZZZZ ai10063 40/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Figure 30. STOP_TRANSMISSION Received After Last Data Block with Card Idle Host Command NCR Cycles Card Response Host Command S T CONTENT Timings CMD S T CONTENT CRC E Z Z P * * * P S T CONTENT CRC E Card is programming DAT ZZZZZZZZZZZSL ********************* LEZZZZZZZZ ai10064 6.4.1 Erase, Set and Clear Write Protect Timings The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be erased. The Erase command (CMD38), once issued, will erase all the selected write blocks. Similarly, Set and Clear Write Protect commands start a programming operation as well. The card will signal "busy" (by pulling the DAT line Low) for the duration of the erase or program operation. The bus transaction timings are the same as those given for the STOP_TRANSMISSION Command in Figure 30. 6.4.2 Re-selecting a busy card When a busy card in Disabled state is reselected, it restores its busy signaling on the data line. The timing diagram for this command / response / busy transaction is the same as that for STOP_TRANSMISSION command illustrated in Figure 30. 6.5 Timing Values Figure 25 gives all timings. Table 25. Timing Values Min 2 5 2 8 8 2 Max 64 5 TAAC + NSAC Unit clock cycle clock cycle clock cycle clock cycle clock cycle clock cycle Parameter NCR NID NAC NRC NCC NWR 41/61 Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF 7 Serial peripheral interface (SPI) mode The SPI mode is a secondary communication protocol, which is available in Flash memorybased SD Memory Cards. The SD Memory Card SPI implementation uses a subset of the SD Memory Card protocol and command set. The advantage of the SPI mode is the capability of using off-the-shelf host, hence reducing the design-in effort to a minimum. The disadvantage is the loss of performance (e.g., Single data line and hardware CS signal per card). The SPI mode is selected during the first Reset command after power-up (CMD0) and cannot be changed once the part is powered on. 7.1 SPI bus topology The SPI compatible communication mode of the SD Memory Card is designed to communicate with an SPI channel, commonly found in various microcontrollers on the market. The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD Memory Card SPI and SD modes use the same command set. Like all SPI devices, the SD Memory Card SPI channel uses the four following signals: ● ● ● ● CS: Host to card Chip Select signal. CLK: Host to card clock signal DataIn: Host to card data signal. DataOut: Card to host data signal. All data tokens are multiples of Bytes (8 bits) and always Byte-aligned to the CS signal. The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active Low) the CS signal (see Figure 31: SD Memory Card System SPI Mode Bus Topology).The CS signal must be continuously active for the duration of the SPI transaction. The only exception occurs during card programming, when the host can deassert the CS signal without affecting the programming process. The SPI interface uses 7 out of the 9 SD signals (DAT1 and DAT2 are not used, DAT3 is the CS signal) of the SD bus. 42/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode Figure 31. SD Memory Card System SPI Mode Bus Topology HOST CS(A) VDD VSS CS VDD VSS CLK, DataIN, DataOut CS(B) CS VDD VSS CLK, DataIN, DataOut CS VDD VSS CLK, DataIN, DataOut SD Memory Card (A) (SPI mode) CLK DataIN DataOut CS(B) SD Memory Card (B) (SPI mode) MultiMediaCard (C) (SPI mode) ai10065 7.2 SPI Bus Protocol Whereas the SD channel is based on command and data bit streams initiated by a start bit and terminated by a stop bit, the SPI channel is Byte-oriented. Every command or data block is built up with 8-bit Bytes and is Byte-aligned to the CS signal (that is, the length is a multiple of 8 clock cycles). Like in the SD protocol, messages in the SPI protocol consist of command, response and data-block tokens. All communications between host and cards are controlled by the host (master). The host starts every bus transaction by asserting the CS signal Low. The response behaviors in SPI mode and SD mode differ in three ways. In the SPI mode: ● ● ● the selected card always responds to the command. two additional (8 & 16 bit) response structures are used when the card encounters a data retrieval problem, it sends an error response in place of the expected data block (in the SD mode the card does not respond but implements a timeout). In addition to returning a response for every command received, the card returns a special data response token for every data block received during write operations. 7.2.1 Mode Selection The SD Memory Card wakes up in the SD mode. It will enter the SPI mode if the CS signal is asserted (Low) when the Reset command (CMD0) is received. The only way to return to the SD mode is to start a new power-down/power-up sequence. In SPI mode, the SD Card protocol state machine does not apply. 43/61 Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF 7.2.2 Bus Transfer Protection On entering the SPI mode the card defaults to the non-protected mode where there is no CRC (Cyclic Redundancy Check). So systems using reliable data links are not obliged to have the hardware and firmware necessary to implement CRC functions. In non-protected mode, the CRC bits are still present but are Don't Care. The CRC option can be turned on and off by the host through the CRC_ON_OFF command (CMD59). 7.2.3 Data Read Single and Multiple Block Read operations are supported in SPI mode. The main difference with the SD mode is that in SPI mode data and responses to the host are both sent on the DataOut line. As a consequence the data transfer may be interrupted and the last data block, replaced by the response to a STOP_TRANSMISSION command. The basic unit of data transfer is the block. The maximum size of a block is defined in the CSD Register (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks entirely contained in a physical block (as defined by READ_BL_LEN) may also be transmitted. Single Block Read operations are initiated by issuing the READ_SINGLE_BOCK command (CMD17). The start address can be any Byte in the valid address range of the card. Every block, however, must be contained in a single physical card sector. Multiple Block Read operations are initiated by issuing the READ_MULTIPLE_BLOCK command (CMD18) and every transferred block has a 16-bit CRC appended to it. The STOP_TRANSMISSION command (CMD12) will actually stop the data transfer operation (just like in the SD mode). Figure 32. Read Operation Mechanism from Host to Card Data in Command from Card to Host data from Card to Host next command Command Data out Response Data Block CRC ai10066 Figure 33. Multiple Block Read Operation from Host to Card Data in Command from Card to Host data from Card to Host next command STOP_TRANSMISSION Command Data out Response Data Block CRC Data Block CRC Data B. Response ai10067 44/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Figure 34. Read Data Error from Host to Card Data in Command from Card to Host Data Error message from Card to Host Serial peripheral interface (SPI) mode next command Command Data out Response Data Error ai10068 7.2.4 Data Write Single and Multiple Block Write operations are supported in SPI mode. Upon reception of a valid write command, the card sends a response token and waits for a data block to be sent from the host. Write operations, as illustrated in Figure 35., follow the same rules as Read operations (refer to Section 7.2.4: Data Write) as regards the CRC, block length and start address. After receiving a data block, the card returns a data response token. If the data block received contains no error, it is programmed. Throughout the programming operation the card sends a continuous stream of busy tokens to the host (by holding the DataOut line Low). Figure 35. Write Operation from Host to Card Data in from Card to Host Data start token data from Host to Card Data Response and Busy from Card data from Host to Card Data stop token > Command > Data Block > Data Block Data out Response Data Response Busy Data Response Busy ai10069 7.2.5 Erase & Write Protect Management The erase and write protect management procedures are the same in the SPI and SD modes. While the card is erasing or changing the write protection bits, it remains in the busy state and holds the DataOut line Low. Figure 36. Erase & Write Protect Operations from Host to Card Data in from Card to Host from Host to Card from Card to Host Command Command Data out Response Response Busy ai10070 45/61 Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF 7.2.6 Read CID/CSD Registers In SPI mode the CID and CSD Registers use a Block Read operation. When a Read command is issued, the card returns a response message followed by a 16 Byte data block with a 16-bit CRC. As TAAC, the Data Read Access Time, is stored in the CSD Register, it cannot be used as the read latency of the CSD Register. NCR (see Table 25: Timing Values) is used instead. 7.2.7 Reset Sequence The SD Memory Card requires a defined reset sequence. After power-on reset or CMD0 (software reset) the card enters an idle state. When idle, the only host commands the card will accept are CMD1 (SEND_OP_COND), ACMD41 (SD_SEND_OP_COND) and CMD58 (READ_OCR). In SPI mode CMD1 and ACMD41 have the same function. The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the 'in-idle-state' bit in the card response switches to Low, thus indicating that the card has completed its initialization process and is ready for the next command. In the SPI mode, as opposed to the SD mode, CMD1 (and ACMD41) has no operands and does not return the contents of the OCR register. Instead, the host may use CMD58 (available in SPI mode only) to read the OCR register. Also it is up to the host to pay attention not to gain access to cards that do not support its voltage range. The use of CMD58 is not restricted to the initializing phase, it can be issued at any time. 7.2.8 Memory Array Partitioning. It is the same as in the SD mode. 7.2.9 Card Lock/Unlock Commands. In the SPI mode, the Lock and Unlock commands are the same as in the SD mode. 7.2.10 Application Specific Commands. The only difference between the SD and SPI modes is the APP_CMD status bit, which is not available in the SPI mode. 7.3 SPI Mode Commands All the SPI commands are 6 Bytes long. The command always starts with the MSB of the string, which corresponds to the command code. See Table 26 for details of the command format. Like in the SD mode, the commands in the SPI mode are divided into classes. However, the classes supported by the two modes are different. See Table 27 For details. The commands supported in the SPI mode are described in detail in Table 27 If no argument is required in the command, the value of the field should be set to '0'. Reserved commands are reserved in both the MultiMediaCard and SPI modes. The contents of the 46/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode command index field are binary: for example, it is '000000' for CMD0 and '100111' for CMD39. For more details about commands and arguments, please refer to the SD Memory Card Specification. Table 26. Bit Position Width (bits) Value Descriptions Command Format 47 1 0 Start Bit 46 1 1 Transmission Bit [45:40] 6 x Command Index [39:8] 32 x Argument [7:1] 7 x CRC7 0 1 1 End Bit Table 27. Card CMD Class (CCC) Class 0 Class 1 Class 2 Class 3 Class 4 Class 5 Class 6 Class 7 Class 8 Class 9 Class 10 Class 11 Command Classes in SPI Mode Supported Commands Class Description 0 1 9 10 12 13 16 17 18 24 25 27 28 29 30 32 33 38 42 55 56 58 59 Basic Not supported in SPI Block Read Not supported in SPI Block Write Erase Write Protection (optional) Lock Card (optional) Application specific Not supported in SPI Reserved +++ + ++ +++ +++ +++ ++++++ ++ 7.4 Responses There are several types of response tokens. As in the SD mode, all are transmitted MSB first. 7.4.1 R1 Format The card sends this response token after every command except for the SEND_STATUS command. R1 Format Responses are one Byte long. The MSB is always zero and the other bits indicate errors, an error being indicated by a '1'. 47/61 Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF 7.4.2 R1b Format This response token is similar to the R1 Format response token but for the option of adding the busy signal. The busy signal token can be any number of Bytes. A zero value indicates that the card is busy. A non-zero value indicates that the card is ready for the next command. 7.4.3 R2 Format This response token is two Bytes long. It is sent as a response to the SEND_STATUS command. 7.4.4 R3 Format This response token is sent by the card when a READ_OCR command is received. The response length is 5 Bytes. The structure of the first Byte is identical to that of the R1 Format response. The other four Bytes contain the OCR register. For more details about responses, please refer to the SD Memory Card Specification v.1.01. 7.5 Clearing Status Bits In the SPI mode, as described in the previous paragraphs, status bits are reported to the host in three different formats: R1 Format response, R2 Format response and data error token (the same bits may exist in several response types - e.g. Card ECC failed). As in the SD mode, error bits are cleared when read by the host, regardless of the response format. State indicators are cleared either when read by the host or in accordance with the card state. For more details, please refer to the SD Memory Card Specification. 7.6 SPI Bus Timings Figure 38 illustrates the basic Command/Response transaction in SPI mode (that is, when the card is ready). Figure 39 describes a Command/ Response transaction when the card is busy (R1b response format). For timings, refer to Table 25. Table 28. S T P E Z D * SPI Timing Symbols Start Bit (=0) Transmitter Bit (Host = 1, Card = 0) One-Cycle Pull-up (=1) End Bit (= 1) High impedance stage Data Bits Repeater 48/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 29. Timing NCS NCR NCX NRC NAC NWR NEC NDS NBR Serial peripheral interface (SPI) mode SPI Timing Values Min 0 1 0 1 1 1 0 0 1 1 Specified in CSD Register 8 8 Max Unit 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles 8 clock cycles Figure 37. Host Command to Card Response - Card is Ready CS H HL L L ********************* L L L L HHH NCS Data In X X H**H 6 Byte Command HH HH H ********** NEC H**H X X X NEC Data Out Z ZZ HHHH ********* H H**H 1 or 2 Byte Response H HH HH Z Z ai10071 Figure 38. Host Command to Card Response - Card is Busy CS HLL L NCS ********************* L L L L H H H L L L L L LH H NEC NDS NEC Data In X H**H 6 Byte Command HHHHHHHHHH**H NCR X*X HHHH*H XX Data Out ZZHHHH ********* H**H Response Busy L Z Z Z Busy H H H H Z ai10072 49/61 Serial peripheral interface (SPI) mode Figure 39. Card Response to Host Command CS L L L L L SMSxxxAF, SMSxxxFF, SMSxxxBF ********************* L L HHH Data In H H HH HH ********** HH HH 6 Byte Command HH HH X X X NRC Data Out H HHHH 1 or 2 Byte Response H**H ********* H HH HH Z Z ai10073 7.6.1 Data Read Timings The timing diagram for deselecting the card by de-asserting CS after the last card response corresponds to a standard command-to-response timing diagram as illustrated in Figure 39 During open-ended Multiple Block Read operations, the STOP_TRANSMISSION command may be sent while the card is transmitting data to the host. In this case, the card stops transmitting the data block within two clock cycles (the bits in the first Byte may not all be set to '1') and returns the response message after a time measured in numbers of clock cycles (NCR). See Figure 40., for details. For timings, refer to Table 25. Figure 40. Single Block Read Operation CS H L L L ********************* L L NEC Read Command HH HH H ************ NAC Card Response H**H Data Block H HH H Z Z Z H*H X X X X L HHHHH NCS Data In X H**H NCR Data Out Z ZHHH H ******* H**H ai10074 Figure 41. STOP_TRANSMISSION between Blocks During Multiple Block Read CS HLL NCS ********************* L L LL L Data In X H * H Read Command HHHH NCR *********** NAC NAC H H STOP_TRAN. H H H H H H H CMD NCR Card Response ai10075 Data Out ZZHHH **** Card H * H Response H * H Data Block H * H Data Block H H * H 50/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode Figure 42. STOP_TRANSMISSION within a Block During Multiple Block Read CS HLL NCS ********************* L L LL L Data In XH*H Read Command HHHH NCR ******** NAC H H H STOP_TRAN. H H H H H H H H H H CMD NAC NCR Data Out ZZHHH **** Card Card H * H Response H * H Data Block H * H Data X X H * * H Response ai10076 Figure 43. CSD Register Read Operation CS HLLL NCS Data In X H**H Read Command H H H H H NCR Data Out ZZHHHH ****** H**H Card Response ********** NCX H**H Data Block H H H H Z Z Z ai10077 ********************* L L LHHHH NEC H*H XXXX 7.6.2 Data Write Timings The host may deselect a card at any moment during Single and Multiple Block Write operations. The card will release the DataOut line one clock cycle after it is deselected (CS High). To check whether the card is still busy, the host must reselect it by driving CS Low. The card will then take control of the DataOut line one clock cycle after being reselected. In Multiple Block Write operations, the timings from the command being issued to the first data block being transmitted by the card are the same as for Single Block Write operations (see Figure 44 for details). The timing of Stop Tran prefixes is the same as that of data blocks. After the card receives the STOP_TRANSMISSION command, the data on the DataOut line is undefined for one Byte (NBR), then a busy message may be sent by the card. For timings, refer to Table 25. Figure 44. Single Block Write Operation CS HL NCS Data In ********************* NWR L L L L L L L L LHHHL L L L NEC NDS X H * H Write Command H H H H H H H H * H Data Block H H H H H * H X * X H H H H NCR NCX Busy L Z Z Z Busy H ai10078 Data Out ZZHHH **** Card Data H * H Response H H H H H H H Response 51/61 Serial peripheral interface (SPI) mode Figure 45. Multiple Block Write Operation CS SMSxxxAF, SMSxxxFF, SMSxxxBF L ********************* LLLLL LLLLLLLLLLLLLLL NWR NWR Data In STOP_TR H Data Block H H H H H H H H * H Data Block H H H H H H H H * H HH H H H CMD NBR Data Out HHHHH Data Response Busy HHHHHHH Data Response Busy H H H H H H X * X Busy ai10079 52/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Package mechanical data 8 Package mechanical data Figure 46. Full-Size Secure Digital Memory Card Dimensions TD2 TD1 T8 8 7 6 5 4 3 2 1 9 T9 FD D A T7 E1 SE FE T1 E MMC-002 1. Drawing is not to scale. Table 30. Symbol Full-Size Secure Digital Memory Card Mechanical Data millimeters Typ Min 2.050 31.900 23.900 – 3.900 3.900 – 1.400 1.400 0.900 1.100 – 5.000 Max 2.250 32.100 24.100 – 4.100 4.100 – – – – – 1.600 – Typ 0.0827 1.2598 0.9449 0.5906 0.1575 0.1575 0.3198 – – – – – – inches Min 0.0807 1.2559 0.9409 – 0.1535 0.1535 – 0.0551 0.0551 0.0353 0.04331 – 0.19685 Max 0.0886 1.2638 0.9488 – 0.1614 0.1614 – – – – – 0.06299 – A D E E1 FD FE SE T1 T9 T8 T7 TD1 TD2 2.100 32.000 24.000 15.000 4.000 4.000 8.125 – – – – – – 53/61 Package mechanical data Figure 47. mini Secure Digital Card Dimensions A4 A3 B4 B3 B8 B6 B5 a e A3 B7 C SMSxxxAF, SMSxxxFF, SMSxxxBF A1 A2 R R3 B9 B2 B1 R2 R1 R1 R2 R1 R2 R3 R2 Θ J2 J3 B R4 G2 R1 G4 M1 M2 G3 A D3 G1 MINI SD CARD Table 31. Symbol MiniSD package mechanical data millimeters Typ Min 19.90 18.35 0.50 1.45 0.85 21.40 7.60 5.40 1.3 Max 20.10 18.65 0.70 2.05 1.15 21.60 7.80 5.60 1.5 Typ 0.7874 0.7283 0.0236 0.0748 0.1082 0.0393 0.8464 0.3031 0.2165 0.0196 0.0078 0.1496 0.1614 0.0393 0.1968 0.1771 0.0551 inches Note Min 0.7834 0.7244 0.0216 0.0708 0.1062 0.0374 0.8425 0.3011 0.2145 0.0177 0.1476 0.1594 0.0374 0.2342 0.1751 0.0511 Max 0.7913 0.7322 0.0255 0.0767 0.1102 0.0413 0.8503 0.3051 0.2185 0.0216 0.1515 0.1633 0.0413 0.1988 0.1791 0.0590 20 18.50 0.60 2.75 1.00 21.50 7.70 5.50 0.50 0.20 3.8 4.10 1.00 5.00 4.50 1.4 A A1 A2 A3 A4 a B B1 B2 B3 B4 B5 B6 B7 B8 B9 C 54/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 31. Symbol Typ D3 e G1 G2 G3 G4 J2 J3 M1 M2 R R1 R2 R3 R4 Θ 1.30 0.60 1 1.20 3.00 3.60 0.50 0.30 0.10 0.20 1.00 45 0.60 10 0.90 1.00 1.10 1.40 Min Max Typ 0.1929 0.0511 0.0236 0.0255 0.4015 0.0078 0.0393 0.0472 0.1181 0.1417 0.0196 0.0118 0.0039 0.0078 0.0393 45 Min 0.1909 0.0492 0.0216 0.0236 0.3976 0.0374 0.0452 0.1161 0.1397 - Package mechanical data MiniSD package mechanical data (continued) millimeters inches Note Max 0.1948 0.0531 0.0255 0.0275 0.4055 0.0413 0.0492 0.1200 0.1437 Radius Radius Radius Radius Radius 55/61 Package mechanical data Figure 48. MicroSD card mechanical dimensions A3 A2 A4 A5 B7 B8 B5 B10 B4 C1 C2 R3 SMSxxxAF, SMSxxxFF, SMSxxxBF A1 R4 R1 R2 1 35 B1 ˚ R19 R18 B11 R17 R11 R7 B 4 5˚ B2 R10 B3 A8 C C3 R5 A R6 MICRO SD Table 32. Symbol MicroSD package mechanical data millimeters Min Typ 11.00 9.70 3.85 7.70 1.10 0.80 0.70 15.00 6.40 1.84 1.50 0.52 2.90 0.30 1.10 7.90 1.20 Max 11.10 9.80 – 7.80 – 0.85 0.80 15.10 6.50 2.04 1.70 0.62 3.00 0.40 1.20 8.00 1.30 Min 0.429 0.378 – 0.299 – 0.030 0.024 0.587 0.248 0.065 0.051 0.017 0.110 0.008 0.039 0.307 0.043 inches Typ 0.433 0.382 0.152 0.303 0.043 0.031 0.028 0.591 0.252 0.072 0.059 0.020 0.114 0.012 0.043 0.311 0.047 Max 0.437 0.386 – 0.307 – 0.033 0.031 0.594 0.256 0.080 0.067 0.024 0.118 0.016 0.047 0.315 0.051 A A1 A2 A3 A4 A5 A8 B B1 B2 B3 B4 B5 B7 B8 B10 B11 10.90 9.60 – 7.60 – 0.75 0.60 14.90 6.30 1.64 1.30 0.42 2.80 0.20 1.00 7.80 1.10 56/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Table 32. Symbol Min c C1 C2 C3 R1 R2 R3 R4 R5 R6 R7 R10 R11 R17 R18 R19 0.17 0.60 0.20 0.90 0.20 0.20 0.70 0.70 0.70 0.70 29.50 0.10 0.20 0.05 Typ 0.21 0.70 0.30 1.00 0.40 0.40 0.80 0.80 0.80 0.80 30.00 0.20 0.20 0.20 0.40 Max 0.25 0.80 0.40 1.10 0.60 0.60 0.90 0.90 0.90 0.90 30.50 0.30 0.60 0.20 Min 0.007 0.024 0.008 0.035 0.008 0.008 0.028 0.028 0.028 0.028 1.161 0.004 0.008 0.002 Package mechanical data MicroSD package mechanical data (continued) millimeters inches Typ 0.008 0.028 0.012 0.039 0.016 0.016 0.031 0.031 0.031 0.031 1.181 0.008 0.008 0.008 0.016 Max 0.010 0.031 0.016 0.043 0.024 0.024 0.035 0.035 0.035 0.035 1.201 0.012 0.024 0.008 57/61 Part numbering SMSxxxAF, SMSxxxFF, SMSxxxBF 9 Part numbering Table 33. Example: Ordering Information Scheme SMS 256 A F A 5 E Memory Card Standard SMS = Storage Medium, Secure Digital Density 064 = 64 MBytes 128 = 128 MBytes 256 = 256 MBytes 512 = 512 MBytes 01G = 1GByte Options of the Standard A = SD full size B = MiniSD (reduced size) F = MicroSD Memory Type F = Flash Memory Card Version A = Version depending on device mix. Temperature Range 5 = − to 85°C 25 Packing E = ECOPACK package, standard packing (tray) Note: Other digits may be added to the ordering code for preprogrammed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’. For further information on any aspect of the device, please contact the nearest Numonyx Sales Office. 58/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Power supply decoupling Appendix A Power supply decoupling The VSS1, VSS2 and VDD lines supply the card with the operating voltage. To do this, decoupling capacitors for buffering current peak are used. These capacitors are placed on the bus side corresponding to Figure 49. Figure 49. Power supply decoupling single card slot Lmax = 13 mm VSS1 C VSS SD Memory Card VSS2 single card slot C=100 nF Ai11729 The host controller includes a central buffer capacitor for VDD. Its value is 1 µF/slot. 59/61 Revision history SMSxxxAF, SMSxxxFF, SMSxxxBF 10 Revision history Table 34. Date 28-Jul-2006 Document Revision History Rev. 1 First issue. Added SD, miniSD and MicroSD available in Halogen free and Antimony free packages. Information on power dissipation removed from Features section. VDD updated in Note 1 below Table 3: Power consumption. Figure 10: Data Packet format and Figure 11: SD Memory Card State Diagram (Card Identification Mode) updated. Applied Numonyx branding. Description of Revision 15-Dec-2006 2 10-Dec-2007 3 60/61 SMSxxxAF, SMSxxxFF, SMSxxxBF Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 61/61