74ABT00PW,112

74ABT00 Quad 2-input NAND gate Rev. 3 — 11 August 2016 Product data sheet 1. General description The 74ABT00 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT00 is a quad 2-input NAND gate. 2. Features and benefits  Latch-up protection exceeds 500 mA per JESD78B class II level A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT00D 40 C to +85 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ABT00DB 40 C to +85 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74ABT00PW 40 C to +85 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ABT00 NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram   $  % <   $  % <   $  % <   $  % <            $ <  % PQD Fig 1. PQD Logic symbol Fig 2. PQD IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning $%7 $%7 $   9&& %   % $   9&& <   $ %   % $   < <   $ $   < %   % <   $ *1'   < %   % <   *1'   $ < DDD Fig 4. DDD Pin configuration for SO14 Fig 5. Pin configuration for SSOP14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74ABT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 12 74ABT00 NXP Semiconductors Quad 2-input NAND gate 6. Functional description Table 3. Function table[1] Input Output nA nB nY L X H X L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V [1] 1.2 +7.0 V [1] 0.5 +5.5 V VI input voltage VO output voltage output HIGH or LOW IIK input clamping current VI < 0 V 18 - mA IOK output clamping current VO < 0 V 50 - mA IO output current output in LOW-state Tj junction temperature Tstg storage temperature [2] - 40 mA - 150 C 65 +150 C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VIH Conditions Min Typ Max Unit 4.5 - 5.5 V 0 - VCC V HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current 15 - - mA IOL LOW-level output current - - 20 mA t/V input transition rise and fall rate 0 - 5 ns/V Tamb ambient temperature 40 - +85 74ABT00 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 August 2016 C © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 12 74ABT00 NXP Semiconductors Quad 2-input NAND gate 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 C Conditions 40 C to +85 C Unit Min Typ Max Min Max 1.2 0.9 - 1.2 - V 2.5 2.9 - 2.5 - V 0.5 - 0.5 V VIK input clamping voltage VCC = 4.5 V; IIK = 18 mA VOH HIGH-level output voltage VCC = 4.5 V; IOH = 15 mA; VI = VIL or VIH VOL LOW-level output voltage VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH - 0.35 II input leakage current VCC = 5.5 V; VI = GND or 5.5 V - 0.01 1.0 - 1.0 A IOFF power-off leakage current VCC = 0 V; VI or VO  4.5 V - 5.0 100 - 100 A ICEX output high leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC - 5.0 50 - 50 A IO output current VCC = 5.5 V; VO = 2.5 V 50 75 180 50 180 mA ICC supply current VCC = 5.5 V; VI = GND or VCC - 2 50 - 50 A - 0.25 500 - 500 A - 3 - - - pF 40 C to +85 C; VCC = 5.0 V  0.5 V Unit ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND CI input capacitance VI = 0 V or VCC [1] [2] [1] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [2] This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 7. Symbol Parameter 25 C; VCC = 5.0 V Conditions Min Typ Max Min Max tPLH LOW to HIGH propagation delay nA, nB to nY; see Figure 6 1.0 2.5 3.6 1.0 4.1 ns tPHL HIGH to LOW propagation delay nA, nB to nY; see Figure 6 1.0 2.0 2.8 1.0 3.4 ns tsk(o) output skew time - 0.4 0.5 - 0.5 ns [1] [1] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74ABT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 12 74ABT00 NXP Semiconductors Quad 2-input NAND gate 11. Waveforms 9, 90 Q$Q%LQSXW *1' W3+/ W3/+ 92+ 90 Q