INTEGRATED CIRCUITS
74ABT16373B
16-bit transparent latch (3-State)
Product data
Replaces 74ABT16373B/74ABTH16373B of 1998 Feb 27
2004 Feb 27
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
FEATURES
PIN CONFIGURATION
• 16-bit transparent latch
• Multiple VCC and GND pins minimize switching noise
• Power-up 3-State
• Live insertion/extraction permitted
• Power-up reset
• 3-State output buffers
• Output capability: +64 mA/–32 mA
• ICCL –19 mA maximum
• Latch-up protection exceeds 500 mA per JEDEC Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is HIGH. The latch remains
transparent to the data inputs while nE is HIGH, and stores the data
that is present one set-up time before the HIGH-to-LOW enable
transition.
1OE
1
48
1E
1Q0
2
47
1D0
1Q1
3
46
1D1
GND
4
45
GND
1Q2
5
44
1D2
1Q3
6
43
1D3
VCC
7
42
VCC
1Q4
8
41
1D4
1Q5
9
40
1D5
GND
10
39
GND
1Q6
11
38
1D6
1Q7
12
37
1D7
2Q0
13
36
2D0
2Q1
14
35
2D1
GND
15
34
GND
2Q2
16
33
2D2
2Q3
17
32
2D3
VCC
18
31
VCC
2Q4
19
30
2D4
2Q5
20
29
2D5
GND
21
28
GND
2Q6
22
27
2D6
2Q7
23
26
2D7
2OE
24
25
2E
SA00379
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
When nOE is LOW, the latched or transparent data appears at the
outputs. When nOE is HIGH, the outputs are in the high-impedance
“OFF” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
CL = 50 pF; VCC = 5 V
2.5
2.0
ns
CIN
Input capacitance
VI = 0 V or VCC
4
pF
COUT
ICCZ
ICCL
Output capacitance
Quiescent supply current
VO = 0 V or VCC; 3-State
7
pF
Outputs disabled; VCC = 5.5 V
500
µA
Outputs low; VCC = 5.5 V
8
mA
ORDERING INFORMATION
Tamb = –40 °C to +85 °C
Type number
Package
Name
Description
Version
74ABT16373BDL
SSOP48
plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
74ABT16373BDGG
TSSOP48
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2004 Feb 27
2
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
PIN NUMBER
SYMBOL
FUNCTION
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
1D0 – 1D7
2D0 – 2D7
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1Q0 – 1Q7
2Q0 – 2Q7
Data outputs
1, 24
1OE, 2OE
Output enable inputs
(active-LOW)
1OE
1
1EN
1E
48
C3
2OE
24
2EN
2E
25
C4
1D0
47
3D
2
1Q0
1D1
46
3
1Q1
1D2
44
5
1Q2
1D3
43
6
1Q3
1D4
41
8
1Q4
1D5
40
9
1Q5
1D6
38
11
1Q6
1D7
37
12
1Q7
2D0
36
13
2Q0
2D1
35
14
2Q1
2D2
33
16
2Q2
2D3
32
17
2Q3
2D4
30
19
2Q4
1E
2D5
29
20
2Q5
1OE
2D6
27
22
2Q6
2D7
26
23
2Q7
48, 25
Data inputs
Enable inputs
(active-HIGH)
1E, 2E
4, 10, 15, 21, 28, 34,
39, 45
GND
7, 18, 31, 42
VCC
Ground (0 V)
Positive supply voltage
LOGIC SYMBOL
47
46
44
43
41
40
38
37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1∇
2∇
4D
SA00380
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
2E
24
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
LOGIC DIAGRAM
nD1
nD0
D
E
nD2
D
Q
E
nD3
D
Q
E
nD4
D
D
E
Q
nD5
Q
E
nD6
D
Q
E
nD7
D
Q
E
D
Q
E
Q
nE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
2004 Feb 27
3
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
FUNCTION TABLE
INPUTS
OUTPUTS
nOE
nE
nDx
INTERNAL
REGISTER
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
i
h
L
H
L
H
Latch and read register
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
H =
h =
L =
l =
NC=
X =
Z =
↓ =
nQ0 – nQ7
OPERATING MODE
Hold
Disable outputs
HIGH voltage level
HIGH voltage level one set-up time prior to the HIGH-to-LOW E transition
LOW voltage level
LOW voltage level one set-up time prior to the HIGH-to-LOW E transition
No change
Don’t care
High-impedance “off” state
HIGH-to-LOW E transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
VCC
IIK
PARAMETER
DC input diode current
VI
DC input
DC output diode current
DC output voltage3
IOUT
O
DC output current
Tstg
Storage temperature range
RATING
UNIT
–0.5 to +7.0
V
–18
mA
VI < 0 V
voltage3
IOK
VOUT
CONDITIONS
DC supply voltage
–1.2 to +7.0
V
VO < 0 V
–50
mA
output in Off or HIGH state
–0.5 to +5.5
V
output in LOW state
128
output in HIGH state
–64
mA
°C
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
MIN
DC supply voltage
MAX
UNIT
4.5
5.5
V
0
VCC
V
2.0
–
V
–
0.8
V
HIGH-level output current
–
–32
mA
LOW-level output current
–
64
mA
∆t/∆v
Input transition rise or fall rate
0
10
ns/V
Tamb
Operating free-air temperature range
–40
+85
°C
VI
Input voltage
VIH
HIGH-level input voltage
VIL
LOW-level Input voltage
IOH
IOL
2004 Feb 27
4
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Tamb = –40 °C
to +85 °C
Tamb = +25 °C
TEST CONDITIONS
MIN
TYP
MAX
–
–0.9
–1.2
VCC = 4.5 V; IOH = –3 mA; VI = VIL or VIH
2.5
2.9
–
VCC = 5.0 V; IOH = –3 mA; VI = VIL or VIH
3.0
3.4
–
VCC = 4.5 V; IOH = –32 mA; VI = VIL or VIH
VCC = 4.5 V; IIK = –18 mA
MIN
UNIT
MAX
–1.2
V
2.5
–
V
3.0
–
V
2.0
2.4
–
2.0
–
V
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
–
0.42
0.55
–
0.55
V
VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
–
0.13
0.55
–
0.55
V
Input leakage current
VCC = 5.5 V; VI = VCC or GND
–
±0.01
±1
–
±1
µA
Power-off leakage current
VCC = 0.0 V; VO or VI ≤ 4.5 V
–
±5.0
±100
–
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC;
VOE = GND
–
±5.0
±50
–
±50
µA
IOZH
3-State output HIGH
current
VCC = 5.5 V; VO = 5.5 V; VI = VIL or VIH
–
0.5
10
–
10
µA
IOZL
3-State output LOW current
VCC = 5.5 V; VO = 0.0 V; VI = VIL or VIH
–
–0.5
–10
–10
µA
–50
–70
–180
–50
–180
mA
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
–
0.1
50
–
50
µA
VCC = 5.5 V; Outputs HIGH;
VI = GND or VCC
–
0.5
2
–
2
mA
VCC = 5.5 V; Outputs Low;
VI = GND or VCC
–
8
19
–
19
mA
VCC = 5.5 V; Outputs 3-State;
VI = GND or VCC
–
0.5
2
–
2
mA
VCC = 5.5 V; one input at 3.4 V, other inputs
at VCC or GND
–
5
100
–
100
µA
VRST
II
IOFF
IPU/IPD
IO
ICEX
Power-up output
Output
voltage3
current1
Output HIGH leakage
current
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current
per input pin2
VCC = 5.5 V; VO = 2.5 V
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 msec. From VCC = 2.1 to VCC = 5 V ± 10% a
transition time of up to 100 µsec is permitted.
5. Unused pins at VCC or GND.
2004 Feb 27
5
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25 °C
VCC = +5.0 V
WAVEFORM
Tamb = –40 °C to +85 °C
VCC = +5.0V ± 0.5 V
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
2
1.5
1.1
2.5
2.0
3.8
3.1
1.5
1.1
4.4
3.8
ns
tPLH
tPHL
Propagation delay
nE to nQx
1
1.6
1.3
2.5
2.1
3.8
3.1
1.6
1.3
4.4
3.6
ns
tPZH
tPZL
Output enable time
to HIGH and LOW level
4
5
1.2
1.3
2.3
2.3
3.5
3.5
1.2
1.3
4.6
4.5
ns
tPHZ
tPLZ
Output disable time
from HIGH and LOW level
4
5
1.9
1.7
3.1
2.6
4.5
3.8
1.9
1.7
5.3
4.2
ns
AC SET-UP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25 °C
VCC = +5.0 V
WAVEFORM
Tamb = –40 °C to +85 °C
VCC = +5.0 V ± 0.5 V
MIN
TYP
MIN
UNIT
ts(H)
ts(L)
Set-up time, HIGH or LOW
nDx to nE
3
1.0
1.0
0.0
0.3
1.0
1.0
ns
th(H)
th(L)
Hold time, HIGH or LOW
nDx to nE
3
0.5
0.5
–0.2
0.0
0.5
0.5
ns
tw(H)
Enable pulse width
HIGH
1
2.5
1.0
2.5
ns
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
nE
VM
VM
VM
nDx
VM
VM
SA00047
2004 Feb 27
tPHL
tPLH
nQx
Waveform 1.
VM
tPLH
tw(H)
tPHL
nQx
VM
VM
VM
SA00048
Propagation Delay, Enable to Output, and
Enable Pulse Width
Waveform 2. Propagation Delay for Data to Outputs
6
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
nDx
74ABT16373B
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉÉ
ÉÉÉ
VM
VM
ts(H)
VM
ts(L)
th(H)
nE
VM
nOE
VM
VM
th(L)
VM
tPZL
tPLZ
VM
VM
nQx
VOL + 0.3V
VOL
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00051
SA00049
Waveform 3.
Data Set-up and Hold Times
VM
nOE
Waveform 5. 3-State Output Enable Time to LOW Level and
Output Disable Time from LOW Level
VM
tPZH
tPHZ
VOH
nQx
VOH – 0.3V
VM
0V
SA00050
Waveform 4. 3-State Output Enable Time to HIGH Level and
Output Disable Time from HIGH Level
TEST CIRCUIT AND WAVEFORM
VCC
7.0 V
PULSE
GENERATOR
VOUT
VIN
tW
90%
VM
NEGATIVE
PULSE
10%
0V
tTHL (tF)
CL
tTLH (tR)
tTLH (tR)
RL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
TEST
SWITCH
tPLZ
closed
tPZL
closed
All other
open
AMP (V)
VM
10%
RL
D.U.T.
RT
90%
0V
VM = 1.5 V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
74ABT
Amplitude
Rep. Rate
3.0 V
1 MHz
tW
tR
500 ns 2.5 ns
tF
2.5 ns
SA00654
2004 Feb 27
7
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
2004 Feb 27
8
SOT370-1
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
2004 Feb 27
9
SOT362-1
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
REVISION HISTORY
Rev
Date
Description
_3
20040227
Product data (9397 750 12821); 853-1751 ECN 01–A15429 of 27 January 2004.
Replaces data sheet 74ABT_H16373B_2 of 1998 Feb 27 (9397 750 03491).
Modifications:
• Delete all references to 74ABTH16373B (product discontinued).
_2
19980227
_1
19950803
2004 Feb 27
Product specification (9397 750 03491); ECN 853-1751 19027 of 27 February 1998.
Supersedes data of 1995 Aug 03.
10
Philips Semiconductors
Product data
16-bit transparent latch (3-State)
74ABT16373B
Data sheet status
Level
Data sheet status [1]
Product
status [2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 01-04
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
2004 Feb 27
11
9397 750 12985
