74ABT16821A

74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Rev. 03 — 16 March 2010 Product data sheet 1. General description The 74ABT16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the register operation. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features and benefits 20-bit positive-edge triggered register Multiple VCC and GND pins minimize switching noise Live insertion and extraction permitted Output capability: +64 mA and −32 mA Power-up 3-state Power-up reset Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74ABT16821ADL 74ABT16821ADGG −40 °C to +85 °C −40 °C to +85 °C Name SSOP56 TSSOP56 Description plastic shrink small outline package; 56 leads; body width 7.5 mm plastic thin shrink small outline package; 56 leads; body width 6.1 mm Version SOT371-1 SOT364-1 Type number 4. Functional diagram 1 56 1OE 1CP EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 28 2OE 29 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 001aae85 5 Fig 1. IEC logic symbol 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 2 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 55 54 52 51 49 48 47 45 44 43 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 56 1 1CP 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 29 28 2CP 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 27 001aae856 Fig 2. Logic symbol nD0 D nD1 D nD2 D nD3 D nD4 D nD5 D nD6 D nD7 D nD8 D nD9 D CP Q nCP CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 001aae857 Fig 3. Logic diagram 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 3 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 5. Pinning information 5.1 Pinning 74ABT16821A 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 56 1CP 55 1D0 54 1D1 53 GND 52 1D2 51 1D3 50 VCC 49 1D4 48 1D5 47 1D6 46 GND 45 1D7 44 1D8 43 1D9 42 2D0 41 2D1 40 2D2 39 GND 38 2D3 37 2D4 36 2D5 35 VCC 34 2D6 33 2D7 32 GND 31 2D8 30 2D9 29 2CP 001aae854 1Q6 10 GND 11 1Q7 12 1Q8 13 1Q9 14 2Q0 15 2Q1 16 2Q2 17 GND 18 2Q3 19 2Q4 20 2Q5 21 VCC 22 2Q6 23 2Q7 24 GND 25 2Q8 26 2Q9 27 2OE 28 Fig 4. Pin configuration 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 4 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 5.2 Pin description Table 2. Symbol 1OE, 2OE 1Q0 to 1Q9 GND VCC 2Q0 to 2Q9 2CP, 1CP 2D0 to 2D9 1D0 to1D9 Pin description Pin 1, 28 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 29, 56 Description output enable input (active LOW) data output ground (0 V) supply voltage clock pulse input (active rising edge) 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input 6. Functional description Table 3. Input nOE L L L H H [1] Function table[1] Output nCP ↑ ↑ H or L L or H ↑ nDx l h X X Dn nQ0 to nQ9 L H NC Z Z L H NC NC Dn load + read register load + read register hold disable output disable output Internal register Operating mode H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ↑ = LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state. 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 5 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IOK IO Tj Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature Conditions [1] Min −0.5 −1.2 −0.5 −18 −50 −64 [2] Max +7.0 +7.0 +5.5 128 150 +150 Unit V V V mA mA mA mA °C °C output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [1] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VIH VIL IOH IOL Δt/ΔV Tamb Parameter supply voltage input voltage HIGH-level input voltage LOW-level Input voltage HIGH-level output current LOW-level output current input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 −32 0 −40 Typ Max 5.5 VCC 0.8 64 10 +85 Unit V V V V mA mA ns/V °C 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 6 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 9. Static characteristics Table 6. Symbol VIK VOH Static characteristics Parameter Conditions Min input clamping voltage VCC = 4.5 V; IIK = −18 mA HIGH-level output voltage VI = VIL or VIH VCC = 4.5 V; IOH = −3 mA VCC = 5.0 V; IOH = −3 mA VCC = 4.5 V; IOH = −32 mA VOL VOL(pu) II IOFF IO(pu/pd) IOZ LOW-level output voltage power-up LOW-level output voltage input leakage current power-off leakage current VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = VCC or GND VCC = 0 V; VI or VO ≤ 4.5 V [2] [1] 25 °C Typ −0.9 2.9 3.4 2.4 0.36 0.13 Max 0.55 0.55 −1.2 2.5 3.0 2.0 - −40 °C to +85 °C Unit Min −1.2 2.5 3.0 2.0 Max 0.55 0.55 ±1.0 ±100 ±50 V V V V V V μA μA μA ±0.01 ±1.0 ±5.0 ±5.0 ±100 ±50 power-up/power-down VCC = 2.1 V; VO = 0.5 V; output current VI = GND or VCC; nOE don’t care OFF-state output current VCC = 5.5 V; VI = VIL or VIH output HIGH-state at VO = 2.7 V output LOW-state at VO = 0.5 V [3] 1.0 −1.0 5.0 −90 0.5 10 0.5 0.25 10 −10 50 −50 1.0 19 1.0 1.5 −180 - 10 −10 50 −50 1.0 19 1.0 1.5 μA μA μA mA mA mA mA mA ILO IO ICC output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC output current supply current VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs 3-state −180 - ΔICC additional supply current input capacitance output capacitance per input pin; VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND VI = 0 V or VCC outputs disabled; VO = 0 V or VCC [4] - CI CO [1] [2] [3] [4] - 3 7 - - - For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 % a transition time of up to 100 μs is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V. 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 7 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 8. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tsu(H) tsu(L) th(H) th(L) tWH tWL maximum frequency LOW to HIGH propagation delay HIGH to LOW propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay set-up time HIGH set-up time LOW hold time HIGH hold time LOW pulse width HIGH pulse width LOW see Figure 5 nCP to nQx, see Figure 5 nCP to nQx, see Figure 5 nOE to nQx; see Figure 6 nOE to nQx; see Figure 6 nOE to nQx; see Figure 6 nOE to nQx; see Figure 6 nDx to nCP; see Figure 7 nDx to nCP; see Figure 7 nDx to nCP; see Figure 7 nDx to nCP; see Figure 7 nCP; see Figure 5 nCP; see Figure 5 160 1.3 1.1 1.4 1.2 1.6 1.3 1.8 +1.8 1.0 +1.0 2.5 2.5 Typ 250 2.4 2.0 2.5 2.3 3.2 2.3 1.2 −0.9 0.8 −1.0 0.8 1.0 Max 3.3 2.6 3.3 3.0 4.1 3.1 −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min 160 1.3 1.1 1.4 1.2 1.6 1.3 1.8 +1.8 1.0 +1.0 2.5 2.5 Max 3.7 3.0 4.1 3.7 4.8 3.3 MHz ns ns ns ns ns ns ns ns ns ns ns ns 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 8 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 11. Waveforms 1 / fmax VI nCP 0V VM tWH tPHL VOH VM tWL VM tPLH nQx VOL VM VM 001aae858 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency VI nOE input GND tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aal294 VM tPZL VM VOL + 0.3 V tPZH VOH − 0.3 V VM VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH- level 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 9 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state VI nDx VM VM th(H) VM tsu(L) VM th(L) 0V tsu(H) VI CP VM VM 0V 001aae860 The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 1.5 V Fig 7. Set-up and hold times data input (nDx) to clock (CP) VI negative pulse 0V tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW 001aai298 90 % VEXT VCC VI VO DUT RT CL RL RL G VI positive pulse 0V 90 % VM 10 % mna616 a. Input pulse definition Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. b. Test circuit RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 8. Input VI 3.0 V Load circuitry for switching times Test data Load fI 1 MHz tW 500 ns tr, tf ≤ 2.5 ns CL 50 pF RL 500 Ω VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 10 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 12. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE vM A Z 56 29 Q A2 A1 (A 3) θ Lp 1 28 A pin 1 index L wM detail X e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC MO-118 A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 18.55 18.30 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 9. Package outline SOT371-1 (SSOP56) 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 11 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT364-1 (TSSOP56) 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 12 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 13. Abbreviations Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 14. Revision history Table 10. Revision history Release date 20100316 Data sheet status Product data sheet Change notice Supersedes 74ABT_H16821A_2 Document ID 74ABT16821A_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type number 74ABTH16821ADGG removed from Section 3 “Ordering information”. Product specification Product specification 74ABT_H16821A - 74ABT_H16821A_2 74ABT_H16821A 20021213 19980227 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 13 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ABT16821A_3 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 14 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 15 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 March 2010 Document identifier: 74ABT16821A_3