74ABT544DB

74ABT544 Octal latched transceiver with dual enable; inverting; 3-state Rev. 04 — 15 January 2009 Product data sheet 1. General description The 74ABT544 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64 mA. 2. Features I I I I I I I I I I Combines 74ABT640 and 74ABT373 type functions in one device 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Live insertion and extraction permitted Output capability: +64 mA to −32 mA Power-up 3-state Power-up reset Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74ABT544D 74ABT544DB 74ABT544PW −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C SO24 SSOP24 TSSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT137-1 SOT340-1 SOT355-1 Type number NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 4. Functional diagram 2 23 1 13 11 14 1EN3 (BA) G1 1C5 2EN4 (AB) G2 2C6 22 21 20 19 18 17 16 15 001aae901 3 4 5 6 7 8 9 10 3 11 23 14 1 A0 A1 A2 A3 A4 A5 A6 A7 EAB EBA LEAB LEBA B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 001aae900 3 6D 5D 2 4 5 OEAB OEBA 13 2 6 7 8 9 10 Fig 1. Logic symbol Fig 2. IEC logic symbol OEBA 2 13 OEAB EBA LEBA 23 1 11 14 EAB LEAB DETAIL A D LE A0 3 Q D LE Q 22 B0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 DETAIL A × 7 21 20 19 18 17 16 15 001aac758 B1 B2 B3 B4 B5 B6 B7 Fig 3. Logic diagram 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 2 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 5. Pinning information 5.1 Pinning 74ABT544 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 1 2 3 4 5 6 7 8 9 24 VCC 23 EBA 22 B0 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 LEAB 13 OEAB 001aac755 A7 10 EAB 11 GND 12 Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol LEBA OEBA A0 to A7 EAB GND OEAB LEAB B0 to B7 EBA VCC Pin description Pin 1 2 3, 4, 5, 6, 7, 8, 9, 10 11 12 13 14 22, 21, 20, 19, 18, 17, 16, 15 23 24 Description B-to-A latch enable input (active LOW) B-to-A output enable input (active LOW) data input or output A-to-B enable input (active LOW) ground (0 V) A-to-B output enable input (active LOW) A-to-B latch enable input (active LOW) data input or output B-to-A enable input (active LOW) positive supply voltage 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 3 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 6. Functional description 6.1 Function table Table 3. Input OEXX H X L L L L [1] Function selection[1] Output EXX X H ↑ L L L LEXX X X L ↑ L H An or Bn X X h l h l H L X Bn or An Z Z Z Z L H L H NC hold transparent latch + display disabled + latch disabled Status H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); ↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA); NC = no change; X = don’t care; Z = high-impedance OFF-state. 6.2 Description The 74ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs. 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 4 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tj Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature Conditions [1] Min −0.5 −1.2 −0.5 −18 −50 [2] Max +7.0 +7.0 +5.5 128 150 +150 Unit V V V mA mA mA °C °C output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state [1] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Symbol VCC VI VIH VIL IOH IOL ∆t/∆V Tamb Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 −32 0 −40 Typ Max 5.5 VCC 0.8 64 10 +85 Unit V V V V mA mA ns/V °C 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol VIK VOH Parameter Conditions Min input clamping voltage VCC = 4.5 V; IIK = −18 mA HIGH-level output voltage VI = VIL or VIH VCC = 4.5 V; IOH = −3 mA VCC = 5.0 V; IOH = −3 mA VCC = 4.5 V; IOH = −32 mA VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH 2.5 3.0 2.0 3.2 3.7 2.3 0.42 0.55 2.5 3.0 2.0 0.55 V V V V −1.2 25 °C Typ −0.9 Max −40 °C to +85 °C Unit Min −1.2 Max V 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 5 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol VOL(pu) II Parameter power-up LOW-level output voltage input leakage current Conditions Min VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = GND or 5.5 V control pins An, Bn IOFF IO(pu/pd) power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V [2] [1] 25 °C Typ 0.13 Max 0.55 - −40 °C to +85 °C Unit Min Max 0.55 V - ±0.01 ±5.0 ±5.0 ±5.0 ±1.0 ±100 ±100 ±50 - ±1.0 ±100 ±100 ±50 µA µA µA µA power-up/power-down VCC = 2.1 V; VO = 0.5 V; output current VI = GND or VCC; OEAB, OEBA don’t care OFF-state output current VCC = 5.5 V; VI = VIL or VIH VO = 2.7 V VO = 0.5 V IOZ [3] 5.0 −5.0 5.0 −65 110 20 110 0.3 50 −50 50 −50 250 30 250 1.5 −180 - 50 −50 50 −50 250 30 250 1.5 µA µA µA mA µA mA µA mA ILO IO ICC output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC output current supply current VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs disabled −180 - ∆ICC additional supply current input capacitance input/output capacitance per input pin; VCC = 5.5 V; one input pin at 3.4 V, other inputs at VCC or GND VI = 0 V or VCC outputs disabled; VO = 0 V or VCC [4] - CI CI/O - 4 7 - - - pF pF [1] [2] [3] [4] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 ms is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 10. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min tPLH LOW to HIGH propagation delay An to Bn or Bn to An; see Figure 5 LEBA to An or LEAB to Bn; see Figure 6 1.7 2.1 Typ 3.0 3.5 Max 3.8 4.2 −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min 1.7 2.1 Max 4.7 5.2 ns ns 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 6 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state Table 7. Dynamic characteristics …continued GND = 0 V; for test circuit, see Figure 10. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min tPHL tPZH tPZL tPHZ tPLZ tsu(H) tsu(L) th(H) th(L) tWL HIGH to LOW propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay set-up time HIGH set-up time LOW hold time HIGH hold time LOW pulse width LOW An to Bn or Bn to An; see Figure 5 LEBA to An or LEAB to Bn; see Figure 6 OEBA to An, OEAB to Bn; see Figure 7 EBA to An, EAB to Bn; see Figure 7 OEBA to An, OEAB to Bn; see Figure 8 EBA to An, EAB to Bn; see Figure 8 OEBA to An, OEAB to Bn; see Figure 7 EBA to An, EAB to Bn; see Figure 7 OEBA to An, OEAB to Bn; see Figure 8 EBA to An, EAB to Bn; see Figure 8 An to LEAB, Bn to LEBA; see Figure 9 An to EAB, Bn to EBA; see Figure 9 An to LEAB, Bn to LEBA; see Figure 9 An to EAB, Bn to EBA; see Figure 9 LEAB to An, LEBA to Bn; see Figure 9 EAB to An, EBA to Bn; see Figure 9 LEAB to An, LEBA to Bn; see Figure 9 EAB to An, EBA to Bn; see Figure 9 latch enable; see Figure 9 2.4 3.0 1.8 1.9 2.9 3.1 2.0 2.1 2.0 2.0 3.0 3.0 3.0 3.0 +0.5 +0.5 +0.5 +0.5 3.5 Typ 3.6 4.4 3.0 3.4 4.2 4.6 3.3 3.4 2.8 3.0 1.5 1.5 0.6 0.6 −0.3 −0.2 −1.3 −1.3 1.8 Max 4.5 5.3 3.9 4.1 5.2 5.5 4.3 4.5 5.8 6.2 −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min 2.4 3.0 1.8 1.9 2.9 3.1 2.0 2.1 2.0 2.0 3.0 3.0 3.0 3.0 0.5 0.5 0.5 0.5 3.5 Max 5.2 6.2 4.7 5.0 6.1 6.5 4.9 5.2 6.3 6.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11. Waveforms VI An, Bn GND tPHL VOH VM VM tPLH Bn, An VOL VM VM 001aac759 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 7 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state VI LEBA, LEAB GND tPLH VOH VM VM tPHL An, Bn VOL VM VM 001aac761 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) VI OEAB, OEBA, EAB, EBA VM VM GND tPZH VOH An, Bn tPHZ VOH − 0.3 V VM GND 001aae907 VM = 1.5 V VOH is a typical voltage output level that occurs with the output load. Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level VI OEAB, OEBA, EAB, EBA GND VM VM tPZL 3.5 V An, Bn VOL VM tPLZ VOL + 0.3 V 001aae906 VM = 1.5 V VOL is a typical voltage output level that occurs with the output load. Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 8 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 3.0 V An, Bn VM tsu(H) VM th(H) VM tsu(L) tWL VM th(L) GND 3.0 V LEAB, LEBA, EAB, EBA GND VM VM 001aae905 VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times and latch enable pulse width VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aac221 RT 90 % VM VCC VI VO DUT CL RL RL VEXT G VI positive pulse 0V VM 10 % mna616 a. Input pulse definition Test data is given in Table 8. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. b. Test circuit RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Load circuitry for switching times Table 8. Input VI 3.0 V fI 1 MHz tW 500 ns tr, tf ≤ 2.5 ns Test data Load CL 50 pF RL 500 Ω VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 9 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT137-1 (SO24) 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 10 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT340-1 (SSOP24) 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 11 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT355-1 (TSSOP24) 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 12 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 13. Abbreviations Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 14. Revision history Table 10. Revision history Release date 20100115 Data sheet status Product data sheet Change notice Supersedes 74ABT544_3 (9397 750 14756) Document ID 74ABT544_4 Modifications: • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification Product specification Product specification 74ABT544_2 (9397 750 10752) 74ABT544 - 74ABT544_3 (9397 750 14756) 74ABT544_2 (9397 750 10752) 74ABT544 20050420 20021118 19930701 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 13 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 14 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 January 2009 Document identifier: 74ABT544_4