74ABT573AD,112

Philips Semiconductors Product specification 74ABT573A Octal D-type transparent latch (3-State) The 74ABT573A device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74ABT573A is functionally identical to the 74ABT373 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. FEATURES • 74ABT573A is flow-through pinout version of 74ABT373 • Inputs and outputs on opposite side of package allow easy interface to microprocessors • 3-State output buffers • Common output enable • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. and 200 V per Machine Model • Power-up 3-State • Power-up reset The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. DESCRIPTION When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance ”OFF” state, which means they will neither drive nor load the bus. The 74ABT573A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V CIN TYPICAL UNIT 2.8 3.3 ns pF Input capacitance VI = 0V or VCC 3 COUT Output capacitance Outputs disabled; VO = 0V or VCC 6 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 100 µA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic DIP PACKAGES –40°C to +85°C 74ABT573A N 74ABT573A N SOT146-1 20-Pin plastic SO –40°C to +85°C 74ABT573A D 74ABT573A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT573A DB 74ABT573A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT573A PW 74ABT573APW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs Q0-Q7 Data outputs 17 Q2 19, 18, 17, 16, 15, 14, 13, 12 5 16 Q3 11 E 6 15 Q4 10 GND Ground (0V) D5 7 14 Q5 20 VCC Positive supply voltage D6 8 13 Q6 D7 9 12 Q7 OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 D3 D4 GND 10 Output enable input (active-Low) Enable input (active-High) 11 E SA00185 1995 Sep 06 1 853–1455 15703 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) LOGIC SYMBOL (IEEE/IEC) 74ABT573A LOGIC SYMBOL 1 EN 11 C1 2 2D 19 1 3 18 4 17 5 16 6 15 7 14 8 13 9 12 11 2 3 D0 D1 4 5 D2 D3 6 7 8 9 D4 D5 D6 D7 E 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 SA00187 SA00186 FUNCTION TABLE INTERNAL OUTPUTS OE INPUTS E Dn REGISTER Q0 – Q7 L L H H L H L H L H Enable and read register L L ↓ ↓ l h L H L H Latch and read register L L X NC NC H H L H X Dn NC Dn Z Z H = h = L = l = NC= X = Z = ↓ = OPERATING MODE Hold Disable outputs High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D E D Q E D Q E D Q E D Q E D Q E D Q E D Q E Q 11 E 1 OE 19 Q0 18 Q1 17 16 Q2 Q3 15 Q4 14 Q5 13 Q6 12 Q7 SA00188 1995 Sep 06 2 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.0V; VO = 0.5V; VOE = Don’t Care; VI = GND or VCC ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –180 mA IOFF IPU/IPD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –40 –180 –40 VCC = 5.5V; Outputs High, VI = GND or VCC 100 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 24 30 30 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 100 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V
10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ Max Min Max UNIT tPLH tPHL Propagation delay Dn to Qn 2 1.5 2.2 2.8 3.3 4.0 4.8 1.5 2.2 4.5 5.3 ns tPLH tPHL Propagation delay E to Qn 1 1.2 1.8 2.5 3.0 4.0 4.4 1.2 1.8 4.5 4.7 ns tPZH tPZL Output enable time to High and Low level 4 5 1.2 2.7 3.0 3.8 4.5 5.3 1.2 2.7 5.2 5.7 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.5 1.2 2.8 2.2 4.1 3.4 1.5 1.2 4.5 3.8 ns 1995 Sep 06 4 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Min 3 1.0 1.0 0.3 0.2 1.0 1.0 ns Hold time, High or Low Dn to E 3 1.0 1.0 –0.1 –0.2 1.0 1.0 ns E pulse width High 1 2.0 0.7 2.0 ns ts(H) ts(L) Setup time, High or Low Dn to E th(H) th(L) tw(H) AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VM E VM VM tw(H) tPHL OE VM VM tPZH tPHZ tPLH VM Qn Qn VM VOH–0.3V VM 0V SA00063 SA00066 Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width Dn VM Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level OE VM tPLH Qn VM VM tPZL tPHL VM VM Qn tPLZ VM VOL+0.3V VOL SA00064 SA00332 Waveform 2. Propagation Delay for Data to Outputs Dn Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM VM ts(H) E VM th(H) VM VM ts(L) th(L) VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00065 Waveform 3. Data Setup and Hold Times 1995 Sep 06 5 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 6