74ABT652A

74ABT652A Octal transceiver/register; non-inverting; 3-state Rev. 02 — 12 March 2010 Product data sheet 1. General description The 74ABT652A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH. Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus management. 2. Features and benefits I I I I I I I I I Independent registers for A and B buses Multiplexed real-time and stored data 3-state outputs Live insertion/extraction permitted Power-up 3-state Power-up reset Output capability: +64 mA to −32 mA Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74ABT652AD −40 °C to +85 °C SO24 SSOP24 TSSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm Version SOT137-1 Type number 74ABT652ADB −40 °C to +85 °C 74ABT652APW −40 °C to +85 °C plastic shrink small outline package; 24 leads; body width SOT340-1 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 4. Block diagram 21 3 23 22 1 2 EN1[BA] EN2[AB] C4 G5 C6 G7 ≥1 7 7 5 5 ≥1 1 2 19 18 17 16 15 14 13 001aae846 4 4 5 6 7 8 9 10 11 5 6 3 21 7 8 9 10 11 20 19 18 17 16 15 14 13 001aae845 1 6D 1 4D 20 23 22 2 1 A0 A1 A2 A3 A4 A5 A6 A7 CPBA SBA SAB CPAB B0 B1 B2 B3 B4 B5 B6 B7 OEAB OEBA Fig 1. Logic symbol Fig 2. IEC logic symbol 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 02 — 12 March 2010 3 of 19 74ABT652A_2 NXP Semiconductors REAL TIME BUS TRANSFER BUS B TO BUS A REAL TIME BUS TRANSFER BUS A TO BUS B STORAGE FROM A, B, OR A AND B TRANSFER STORED DATA TO A OR B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. A B A B A B A B Octal transceiver/register; non-inverting; 3-state OEAB OEBA CPAB CPBA X L L X SAB X SBA L OEAB OEBA CPAB CPBA H H X X SAB L SBA X OEAB OEBA CPAB CPBA H X X X X L H L SAB X X X SBA X X X OEAB OEBA CPAB CPBA H L H/L H/L SAB H SBA H 001aae847 74ABT652A Fig 3. Real time bus transfer and storage NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state OEBA 21 OEAB 3 CPBA SBA CPAB SAB 23 22 1 2 1 of 8 channels 1D C1 Q A0 4 1D C1 Q 20 B0 A1 A2 A3 A4 A5 A6 A7 5 6 7 8 9 10 11 DETAIL A × 7 19 18 17 16 15 14 13 001aae848 B1 B2 B3 B4 B5 B6 B7 Fig 4. Logic diagram 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 4 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 5. Pinning information 5.1 Pinning 74ABT652A CPAB SAB OEAB A0 A1 A2 A3 A4 A5 1 2 3 4 5 6 7 8 9 24 VCC 23 CPBA 22 SBA 21 OEBA 20 B0 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 001aae844 A6 10 A7 11 GND 12 Fig 5. Pin configuration 5.2 Pin description Table 2. Symbol CPAB SAB OEAB A0, A1, A2, A3, A4, A5, A6, A7 GND B0, B1, B2, B3, B4, B5, B6, B7 OEBA SBA CPBA VCC Pin description Pin 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 12 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 24 Description A to B clock input A to B select input A to B output enable input data input/output (A side) ground (0 V) data input/output (B side) B to A output enable input (active LOW) B to A select input B to A clock input positive supply voltage 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 5 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 6. Functional description 6.1 Function table Table 3. Inputs OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CPAB H or L ↑ ↑ ↑ H or L ↑ X X X H or L H or L CPBA H or L ↑ H or L ↑ ↑ ↑ X H or L X X H or L SAB X X X [3] Function table [1] Data I/O SBA X X X X X [3] Operating mode Bn input input unspecified output [2] unspecified output [2] input input input input output output output isolation store A and B data store A, hold B store A in both registers hold A, store B store B in both registers real time B data to A bus stored B data to A bus real time A data to B bus store A data to B bus stored A data to B bus; stored B data to A bus An input input input input unspecified output [2] unspecified output [2] output output input input output X X X X L H H L H X X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition. The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock. If both select controls (SAB and SBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must be staggered in order to load both registers. [2] [3] Figure 3 demonstrates the four fundamental bus-management functions that can be performed with the 74ABT652A. The select pins determine whether data is stored or transferred through the device in real time. The output enable pins determine the direction of the data flow. 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 6 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IOK IO Tj Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature Conditions [1] Min −0.5 −1.2 −0.5 −18 −50 [2] Max +7.0 +7.0 +5.5 128 150 +150 Unit V V V mA mA mA °C °C output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state [1] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Symbol VCC VI VIH VIL IOH IOL ∆t/∆V Tamb Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 −32 0 −40 Typ Max 5.5 VCC 0.8 64 10 +85 Unit V V V V mA mA ns/V °C 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 7 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 9. Static characteristics Table 6. Static characteristics Conditions Min VIK VOH input clamping voltage HIGH-level output voltage VCC = 4.5 V; IIK = −18 mA VI = VIL or VIH VCC = 4.5 V; IOH = −3 mA VCC = 5.0 V; IOH = −3 mA VCC = 4.5 V; IOH = −32 mA VOL VOL(pu) II LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH power-up LOW-level output voltage input leakage current VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = GND or 5.5 V control pins data pins IOFF IO(pu/pd) power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V power-up/power-down output current VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; OEAB, OEBA don’t care VO = 2.7 V VO = 0.5 V ILO IO ICC output leakage current output current supply current VCC = 5.5 V; HIGH-state; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs disabled ∆ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND VI = 0 V or VCC outputs disabled; VO = 0 V or VCC [4] [3][5] [2] [1] Symbol Parameter 25 °C Typ −0.9 3.0 3.5 2.4 0.3 0.13 Max 0.55 0.55 −1.2 2.5 3.0 2.0 - −40 °C to +85 °C Unit Min −1.2 2.5 3.0 2.0 Max 0.55 0.55 V V V V V V - ±0.01 ±1.0 ±5 ±5.0 ±5.0 ±100 ±100 ±50 - ±1.0 ±100 ±100 ±50 µA µA µA µA IOZ OFF-state output current VCC = 5.5 V; VI = VIL or VIH −180 5.0 −5.0 5.0 −65 110 20 110 0.3 50 −50 50 −40 250 30 250 1.5 −180 50 −50 50 −40 250 30 250 1.5 µA µA µA mA µA mA µA mA CI CO input capacitance output capacitance - 4 7 - - - pF pF [1] [2] [3] [4] [5] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 µs is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V. This data sheet limit may vary among suppliers. 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 8 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 12. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min fmax tPLH maximum frequency LOW to HIGH propagation delay see Figure 6 CPAB to Bn or CPBA to An; see Figure 6 An to Bn or Bn to An; see Figure 7 SAB to Bn or SBA to An; see Figure 8 tPHL HIGH to LOW propagation delay CPAB to Bn or CPBA to An; see Figure 6 An to Bn or Bn to An; see Figure 7 SAB to Bn or SBA to An; see Figure 8 tPZH tPZL tPHZ tPLZ tsu(H) tsu(L) th(H) th(L) tWH tWL [1] −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min 125 2.2 1.5 1.5 1.7 1.5 1.5 2 2 3 3 1.5 1.5 1.5 1.5 3.0 3.0 0.0 0.0 4.0 4.0 Max 5.6 4.8 6.5 5.6 5.4 5.9 5.8 6.5 8.5 7.4 5.3[1] 5.5 4.1 5.1 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typ 300 3.7 3.0 3.5 4.3 3.6 4.2 3.2 3.5 4.5 4.7 3.9 3.8 2.9 3.0 0.7 0.7 −0.5 −0.5 1.0 1.0 Max 5.1 4.3 5.1 5.1 4.6 5.2[1] 4.6 6.1 6.8 6.5 4.7[1] 4.6[1] 3.8 4.4 - 125 2.2 1.5 1.5 1.7 1.5 1.5 2 2 3 3 1.5 1.5 1.5 1.5 3.0 3.0 0.0 0.0 4.0 4.0 OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay set-up time HIGH set-up time LOW hold time HIGH hold time LOW pulse width HIGH pulse width LOW OEBA to An; see Figure 10 OEAB to Bn; see Figure 10 OEBA to An; see Figure 11 OEAB to Bn; see Figure 11 OEBA to An; see Figure 10 OEAB to Bn; see Figure 10 OEBA to An; see Figure 11 OEAB to Bn; see Figure 11 An to CPAB, Bn to CPBA; see Figure 9 An to CPAB, Bn to CPBA; see Figure 9 An to CPAB, Bn to CPBA; see Figure 9 An to CPAB, Bn to CPBA; see Figure 9 CPAB, CPBA; see Figure 6 CPAB, CPBA; see Figure 6 This data sheet limit may vary among suppliers. 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 9 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 11. Waveforms 1 / fmax VI CPBA or CPAB GND tWH tPHL VOH An or Bn VOL VM VM VOL 001aae839 001aae904 VI VM VM tWL VM An or Bn GND VM VM tPLH tPLH VOH Bn or An tPHL VM VM VM = 1.5 V VM = 1.5 V Fig 6. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency Fig 7. Propagation delay, An to Bn or Bn to An VI SBA or SAB VM VM GND tPHL VOH An or Bn VOL VM VM 001aae852 tPLH VM = 1.5 V Fig 8. Propagation delay, SBA to An or SAB to Bn VI An, Bn VM GND VI tsu(H) VM th(H) VM tsu(L) tWL VM th(L) CPBA or CPAB VM GND VM 001aae849 VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 10 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state OEBA VI VM VM OEAB GND tPZH VOH An or Bn GND VM tPHZ VOH − 0.3 V 001aae851 VM = 1.5 V Fig 10. 3-state output enable time to HIGH-level and output disable time from HIGH-level OEBA VI VM VM OEAB GND tPZL 3.5 V An or Bn VOL VM tPLZ VOL + 0.3 V 001aae853 VM = 1.5 V Fig 11. 3-state output enable time to LOW-level and output disable time from LOW-level 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 11 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW 001aai298 90 % VEXT VCC VI VO DUT RT CL RL RL G VI positive pulse 0V 90 % VM 10 % mna616 a. Input pulse definition Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. b. Test circuit RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 12. Test circuit for measuring switching times Table 8. Input VI 3.0 V fI 1 MHz tW 500 ns tr, tf ≤ 2.5 ns Test data Load CL 50 pF RL 500 Ω VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 12 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT137-1 (SO24) 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 13 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT340-1 (SSOP24) 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 14 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT355-1 (TSSOP24) 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 15 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 13. Abbreviations Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 14. Revision history Table 10. Revision history Release date 20100312 Data sheet status Product data sheet Change notice Supersedes 74ABT652A Document ID 74ABT652A_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12 “Package outline”. Product specification - 74ABT652A 19950419 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 16 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ABT652A_2 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 17 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 18 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 March 2010 Document identifier: 74ABT652A_2