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74ABT899D,118

74ABT899D,118

  • 厂商:

    NXP(恩智浦)

  • 封装:

    SOIC28_300MIL

  • 描述:

    IC 9BIT DUAL LATCH TXRX 28SOIC

  • 数据手册
  • 价格&库存
74ABT899D,118 数据手册
INTEGRATED CIRCUITS 74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) Product specification Supersedes data of 1993 Oct 04 IC23 Data Handbook       1998 Jan 16 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) FEATURES 74ABT899 DESCRIPTION • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. B-to-A directions • Independent transparent latches for A-to-B and B-to-A directions • Selectable ODD/EVEN parity • Continuously checks parity of both A bus and B bus latches as Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. ERRA and ERRB • Ability to simultaneously generate and check parity • Can simultaneously read/latch A and B bus data • Output capability: +64 mA/–32mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 FUNCTIONAL DESCRIPTION The 74ABT899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. and 200 V per Machine Model Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) • Power up 3-State • Power-up reset • Live insertion/extraction permitted Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: • Transparent latch / 1 bus latched / both buses latched • Feed-through parity / generate parity • Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 5V 2.9 ns tPLH tPHL Propagation delay An to ERRA CL = 50pF; VCC = 5V 6.1 ns CIN Input capacitance VI = 0V or VCC 4 pF CI/O Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 50 µA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 28-Pin Plastic PLCC PACKAGES –40°C to +85°C 74ABT899 A 74ABT899 A SOT261-3 28-Pin Plastic SOP –40°C to +85°C 74ABT899 D 74ABT899 D SOT136-1 28-Pin Plastic SSOP –40°C to +85°C 74ABT899 DB 74ABT899 DB SOT341-1 1998 Jan 16 2 853-1623 18864 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) PIN CONFIGURATION 74ABT899 PLCC PIN CONFIGURATION ODD/EVEN 1 28 VCC ERRA 2 27 OEB LEA 3 26 B0 A0 4 25 B1 A1 5 24 B2 B1 B2 B3 B4 B5 B6 B7 25 24 23 22 21 20 19 B0 26 A2 A3 6 23 7 22 B4 A4 8 21 B5 A5 9 20 B6 19 17 LEB VCC 28 16 SEL B3 ODD/ 1 EVEN ERRA 2 TOP VIEW A6 10 18 BPAR OEB 27 15 ERRB 14 GND LEA 3 13 OEA A0 4 12 APAR B7 A7 11 18 BPAR APAR 12 17 LEB OEA 13 16 SEL GND 14 15 ERRB 6 5 7 8 9 10 11 A1 A2 A3 A4 A5 A6 A7 SA00291 SA00289 PIN DESCRIPTION LOGIC SYMBOL SYMBOL PIN NUMBER A0 - A7 4, 5, 6, 7, 8, 9, 10, 11 Latched A bus 3-State inputs/outputs B0 - B7 19, 20, 21, 22, 23, 24, 25, 26 Latched B bus 3-State inputs/outputs APAR BPAR ODD/ EVEN 12 18 1 NAME AND FUNCTION 5 6 7 8 9 10 11 12 A0 A1 A2 A3 A4 A5 A6 A7 APAR A bus parity 3-State input 16 LEA, LEB 3, 17 Latch enable inputs (transparent High) ERRA, ERRB 2, 15 Error signal outputs (active-Low) GND 14 Ground (0V) VCC 28 Positive supply voltage 17 LEB 16 SEL ERRA 2 ODD/EVEN ERRB 15 13 OEB OEA B0 B1 B2 B3 B4 B5 B6 B7 BPAR Output enable inputs (gate A to B, B to A) SEL LEA 27 Parity select input (Low for EVEN parity) 13, 27 3 1 B bus parity 3-State input OEA, OEB 1998 Jan 16 4 26 25 24 23 22 21 20 19 Mode select input (Low for generate) 18 SA00290 3 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 OE 9–bit Transparent Latch LEA 3 A0 A1 4 5 A2 A3 6 7 A4 A5 8 9 A6 10 A7 11 12 APAR 27 OEB 26 25 24 B0 B1 9–bit Output Buffer LE 1 mux Parity Generator 0 23 22 21 20 19 B2 B3 B4 B5 B6 18 B7 BPAR 17 LEB 2 ERRA 15 ERRB 9–bit Transparent Latch 9–bit Output Buffer OEA 13 OE LE 1 mux Parity Generator 0 SEL ODD/ EVEN 16 1 SA00292 FUNCTION TABLE INPUTS OPERATING MODE OEB OEA SEL LEA LEB H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED) H = High voltage level L = Low voltage level X = Don’t care 1998 Jan 16 4 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 PARITY AND ERROR FUNCTION TABLE INPUTS H L t r * OUTPUTS SEL ODD/EVEN xPAR (A or B) Σ of High Inputs xPAR (B or A) ERRt ERRr* H H H Even Odd H H H L H L L L L H L H H H L Even Odd H L H Even Odd H H L H L H H L L Even Odd L L H L H L L H H Even Odd H L H L H H L H L Even Odd H L L H H H L L H Even Odd L H L H H H L L L Even Odd L H H L H H PARITY MODES Odd Mode Feed-through/check parity Even Mode Odd Mode Generate parity Even Mode = High voltage level = Low voltage level = Transmit–if the data path is from A→B then ERRt is ERRA = Receive–if the data path is from A→B then ERRr is ERRB Blocked if latch is not transparent ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current VOUT DC output voltage3 output in Off or High state –0.5 to +5.5 V IOUT DC output current output in Low state 128 mA Tstg Storage temperature range –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jan 16 5 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.5 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 4.0 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.6 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA II Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don’t care ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –80 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 50 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 28 34 34 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 50 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.3 1.5 1.5 mA IOFF IPU/IPD ICEX IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100µsec is permitted. 1998 Jan 16 6 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500Ω WAVEFORM Tamb = –40 to +85oC VCC = +5.0V ±10% CL = 50pF RL = 500Ω Min Typ Max Min Max UNIT tPLH tPHL Propagation delay An to Bn or Bn to An 1 1.0 1.0 3.2 2.7 4.5 4.1 1.0 1.0 4.9 4.6 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 2 3.0 2.5 6.0 6.4 7.5 7.9 3.0 2.5 9.0 8.8 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 3 2.8 2.8 6.0 6.7 8.0 8.5 2.8 2.8 9.1 9.3 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 1 2.0 1.3 4.0 3.2 5.2 4.4 2.0 1.3 5.7 5.0 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 6 1.5 1.5 4.2 4.0 5.4 5.4 1.5 1.5 6.0 6.1 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 5 2.6 2.5 5.5 5.3 6.8 6.7 2.6 2.5 8.1 7.8 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 4 2.3 2.6 5.4 5.7 6.8 7.2 2.3 2.6 7.9 8.4 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 8 1.3 1.4 4.1 4.1 5.2 5.3 1.3 1.4 6.0 5.9 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 8 3.7 5.1 6.8 8.3 8.3 9.7 3.7 5.1 9.8 11.0 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 9 1.0 1.0 3.2 3.1 4.4 4.5 1.0 1.0 4.9 5.0 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 9 2.0 1.7 6.8 6.3 8.3 7.9 2.0 1.7 9.7 9.0 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 7 2.0 2.0 6.3 7.1 8.3 9.2 2.0 2.0 9.6 10.3 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 11, 12 1.0 1.0 3.0 3.4 4.3 4.8 1.0 1.0 5.1 5.4 ns tPHZ tPLZ Output disable time OEA to An, APAR or OEB to Bn, BPAR 11, 12 1.0 0.5 3.4 3.0 4.7 4.2 1.0 0.5 5.5 4.7 ns AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS +25oC SYMBOL PARAMETER WAVEFORM Typ 10 2.0 1.5 0.4 0.0 2.0 1.5 ns Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 10 1.5 1.0 0.0 –0.2 1.5 1.0 ns Pulse width, High LEA or LEB 10 3.0 1.9 3.0 ns Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB th(H) th(L) tw(H) 7 Max Min UNIT Min ts(H) ts(L) 1998 Jan 16 Tamb = –40 to +85oC VCC = +5.0V ±10% CL = 50pF RL = 500Ω Tamb = VCC = +5.0V CL = 50pF RL = 500Ω Max Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V 1 SEL An, APAR (Bn, BPAR) INPUT VM VM tPLH tPHL Bn, BPAR (An, APAR) VM OUTPUT VM SA00293 Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR SEL 0 ODD/EVEN 0 LEA (LEB) An (Bn) 1 ODD PARITY EVEN PARITY VM VM tPHL ODD PARITY INPUT tPLH BPAR (APAR) VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00294 Waveform 2. Propagation Delay, An to BPAR or Bn to APAR ODD/EVEN 0 APAR (BPAR) 0 LEA (LEB) An (Bn) 1 ODD PARITY EVEN PARITY VM tPLH VM ODD PARITY INPUT tPHL ERRA (ERRB) VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00295 Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB 1998 Jan 16 8 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 1 APAR (BPAR) An (Bn) EVEN PARITY INPUT INPUT ODD/EVEN VM VM tPLH ERRA (ERRB) tPHL VM OUTPUT VM NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00296 Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB SEL 0 APAR (BPAR) 0 An (Bn) ODD/EVEN EVEN PARITY VM INPUT VM tPLH BPAR (APAR) INPUT tPHL VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00297 Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR 1998 Jan 16 9 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 ODD/EVEN 0 An (Bn) EVEN PARITY APAR (BPAR) VM INPUT VM tPLH ERRA (ERRB) INPUT tPHL VM OUTPUT VM NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00298 Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB 1 ODD/EVEN APAR (BPAR) 0 An (Bn) LEA (LEB) EVEN PARITY ODD PARITY VM EVEN PARITY INPUT VM tPHL tPLH ERRA (ERRB) INPUT VM VM OUTPUT NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o SA00299 Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB 1998 Jan 16 10 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 1 ODD/EVEN APAR (BPAR) 0 An (Bn) EVEN PARITY SEL VM INPUT INPUT VM tPHL tPLH BPAR (APAR) VM OUTPUT VM NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00300 Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR 1 SEL APAR, An] (BPAR, Bn) INPUT LEA (LEB) VM INPUT VM tPHL tPLH Bn, BPAR (An, APAR) VM OUTPUT VM SA00301 Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An ÉÉÉ ÉÉÉ ÉÉÉ APAR, BPAR, An, Bn VM ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ VM ts(H) VM th(H) VM ts(L) th(L) LEA, LEB VM VM tw(H) VM The shaded areas indicate when the input is permitted to change for predictable output performance. SA00302 Waveform 10. Data Setup and Hold Times, Pulse Width High 1998 Jan 16 11 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) OEA, OEB VM 74ABT899 VM tPZH tPHZ An, APAR, Bn, BPAR VOH –0.3V VM 0V SA00303 Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level OEA, OEB VM VM tPZL An, APAR, Bn, BPAR tPLZ VM VOL +0.3V SA00304 Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM 7V 500 Ω From Output Under Test S1 Open GND 500 Ω CL = 50 pF Load Circuit TEST S1 tpd open tPLZ/tPZL 7V tPHZ/tPZH open DEFINITIONS Load capacitance includes jig and probe capacitance; CL = see AC CHARACTERISTICS for value. SA00012 1998 Jan 16 12 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) PLCC28: plastic leaded chip carrer; 28 leads; pedestal 1998 Jan 16 13 74ABT899 SOT261-3 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) SO28: plastic small outline package; 28 leads; body width 7.5mm 1998 Jan 16 14 74ABT899 SOT136-1 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm 1998 Jan 16 15 74ABT899 SOT341-1 Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 74ABT899 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:       yyyy mmm dd 16 Date of release: 05-96 9397-750-03478
74ABT899D,118 价格&库存

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