74AHC259-Q100;
74AHCT259-Q100
8-bit addressable latch
Rev. 1 — 22 July 2013
Product data sheet
1. General description
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed 8-bit addressable latch
designed for general purpose storage applications in digital systems. It is a multifunctional
device capable of storing single-line data in eight addressable latches. It provides a 3-to-8
decoder and multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates
an active LOW common reset (MR) for resetting all latches as well as an active LOW
enable input (LE).
The 74AHC259-Q100; 74AHCT259-Q100 has four modes of operation:
• In the addressable latch mode, data on the data line (D) is written into the addressed
latch. The addressed latch follows the data input with all non-addressed latches
remaining in their previous states.
• In the memory mode, all latches remain in their previous states and are unaffected by
the data or address inputs.
• In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state
of the data input (D) with all other outputs in the LOW state.
• In the reset mode, all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74AHC259-Q100; 74AHCT259-Q100 as an address latch, changing
more than 1 bit of the address could impose a transient-wrong address. Therefore, only
change more than 1 bit while in the memory mode.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Inputs accept voltages higher than VCC
Input levels:
For 74AHC259-Q100: CMOS level
For 74AHCT259-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74AHC259D-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHC259PW-Q100
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74AHC259-Q100
74AHCT259-Q100
74AHCT259D-Q100
74AHCT259PW-Q100 40 C to +125 C
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
SOT109-1
© NXP B.V. 2013. All rights reserved.
2 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
4. Functional diagram
13
Z9
15
G8
14
G10
9,10D
DX
14
0
1
LE
Q0
13
D
Q1
Q2
Q3
1
2
3
A0
Q4
A1
Q5
A2
Q6
Q7
4
2
5
3
Fig 1.
4
C10
8R
0
G
2
6
0
7
5
1
6
2
7
3
7
9
9
4
10
10
5
11
11
12
6
12
MR
15
1
7
mna573
mna572
Logic symbol
Fig 2.
1
A0
2
A1
3
A2
IEC logic symbol
1-of-8
DECODER
8 LATCHES
Q0
4
Q1
5
Q2
6
Q3
7
Q4
9
14
LE
Q5 10
15
MR
Q6 11
13
D
Q7 12
mna571
Fig 3.
Functional diagram
74AHC_AHCT259_Q100
Product data sheet
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Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
3 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
5. Pinning information
5.1 Pinning
$+&4
$+&74
$
$
9&&
05
$
/(
4
'
4
4
4
4
4
4
*1'
4
DDD
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
A0
1
address input
A1
2
address input
A2
3
address input
Q0
4
latch output
Q1
5
latch output
Q2
6
latch output
Q3
7
latch output
GND
8
ground (0 V)
Q4
9
latch output
Q5
10
latch output
Q6
11
latch output
Q7
12
latch output
D
13
data input
LE
14
latch enable input (active LOW)
MR
15
conditional reset input (active LOW)
VCC
16
supply voltage
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
4 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Output
MR
LE
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
X
X
X
X
L
L
L
L
L
L
L
L
Demultiplexer
L
(active HIGH 8-channel)
decoder (when D = H)
L
Reset (clear)
d
L
L
L
Q=d L
L
L
L
L
L
L
d
H
L
L
L
Q=d L
L
L
L
L
L
d
L
H
L
L
L
Q=d L
L
L
L
L
d
H
H
L
L
L
L
Q=d L
L
L
L
d
L
L
H
L
L
L
L
Q=d L
L
L
d
H
L
H
L
L
L
L
L
Q=d L
L
d
L
H
H
L
L
L
L
L
L
Q=d L
d
H
H
H
L
L
L
L
L
L
L
Q=d
Memory (no action)
H
H
X
X
X
X
q0
q1
q2
q3
q4
q5
q6
q7
Addressable latch
H
L
d
L
L
L
Q = d q1
q2
q3
q4
q5
q6
q7
d
H
L
L
q0
Q = d q2
q3
q4
q5
q6
q7
d
L
H
L
q0
q1
Q = d q3
q4
q5
q6
q7
d
H
H
L
q0
q1
q2
Q = d q4
q5
q6
q7
d
L
L
H
q0
q1
q2
q3
Q = d q5
q6
q7
d
H
L
H
q0
q1
q2
q3
q4
Q = d q6
q7
d
L
H
H
q0
q1
q2
q3
q4
q5
Q = d q7
H
H
H
H
q0
q1
q2
q3
q4
q5
q6
[1]
Q=d
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
5 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 4.
Operating mode select table[1]
LE
MR
Mode
L
H
addressable latch
H
H
memory
L
L
active HIGH 8-channel demultiplexer
H
L
reset
[1]
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
VI
Conditions
Min
Max
Unit
supply voltage
0.5
+7.0
V
input voltage
0.5
+7.0
V
20
-
mA
20
+20
mA
input clamping current
VI < 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
VO = 0.5 V to (VCC + 0.5 V)
IIK
IO
output current
25
+25
mA
ICC
supply current
-
+75
mA
IGND
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
Max
Unit
Tamb = 40 C to +125 C
total power dissipation
Ptot
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
Conditions
Min
Typ
74AHC259-Q100
VCC
supply voltage
2.0
5.0
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 3.0 V to 3.6 V
-
-
100
ns/V
VCC = 4.5 V to 5.5 V
-
-
20
ns/V
4.5
5.0
5.5
V
74AHCT259-Q100
VCC
supply voltage
VI
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
-
-
20
ns/V
74AHC_AHCT259_Q100
Product data sheet
VCC = 4.5 V to 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
6 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
74AHC259-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
3.94
-
-
3.80
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
VI = VCC or GND
74AHCT259-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.80
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
7 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
ICC
additional
per input pin; VI = VCC 2.1 V;
supply current other pins at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
VI = VCC or GND
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
CL = 15 pF
-
5.8
11.5
1.0
13.5
1.0
15.0
ns
CL = 50 pF
-
7.3
14.5
1.0
17.0
1.0
18.5
ns
-
4.1
7.5
1.0
9.0
1.0
10.0
ns
-
5.3
9.5
1.0
11.0
1.0
12.0
ns
CL = 15 pF
-
7.5
14.5
1.0
17.0
1.0
18.5
ns
CL = 50 pF
-
9.1
18.0
1.0
21.0
1.0
23.0
ns
-
5.3
9.5
1.0
11.5
1.0
12.5
ns
-
6.5
11.5
1.0
13.5
1.0
15.0
ns
CL = 15 pF
-
6.2
12.0
1.0
14.0
1.0
15.2
ns
CL = 50 pF
-
7.7
15.5
1.0
17.5
1.0
19.0
ns
CL = 15 pF
-
4.3
8.0
1.0
9.5
1.0
10.5
ns
CL = 50 pF
-
5.5
10.0
1.0
11.5
1.0
12.5
ns
74AHC259-Q100
tpd
propagation D to Qn; see Figure 5
delay
VCC = 3.0 V to 3.6 V
[2]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
An to Qn; see Figure 6
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
LE to Qn; see Figure 7
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
8 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
tpd
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
CL = 15 pF
-
5.4
10.5
1.0
12.5
1.0
13.5
ns
CL = 50 pF
-
7.0
13.5
1.0
15.5
1.0
17.0
ns
CL = 15 pF
-
3.9
7.0
1.0
8.5
1.0
9.5
ns
CL = 50 pF
-
5.1
9.0
1.0
10.5
1.0
11.5
ns
VCC = 3.0 V to 3.6 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 4.5 V to 5.5 V
5.0
-
-
5.0
-
5.0
-
ns
VCC = 3.0 V to 3.6 V
4.0
-
-
4.0
-
4.0
-
ns
VCC = 4.5 V to 5.5 V
4.0
-
-
4.0
-
4.0
-
ns
1.0
-
-
1.0
-
1.0
-
ns
[3]
propagation MR to Qn; see Figure 8
delay
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
tW
pulse width
LE HIGH or LOW;
see Figure 7
MR LOW; see Figure 8
tsu
th
set-up time
hold time
D, An to LE; see Figure 9
and Figure 10
D, An to LE; see Figure 9
and Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
1.0
-
-
1.0
-
1.0
-
ns
-
13
-
-
-
-
-
pF
-
4.1
7.5
1.0
9.0
1.0
10.0
ns
-
5.4
9.5
1.0
11.0
1.0
12.0
ns
-
5.5
9.5
1.0
11.5
1.0
12.5
ns
-
6.6
12.0
1.0
14.0
1.0
15.5
ns
CL = 15 pF
-
4.3
8.0
1.0
9.5
1.0
10.4
ns
CL = 50 pF
-
5.5
10.0
1.0
12.0
1.0
13.0
ns
-
3.9
7.0
1.0
8.5
1.0
9.5
ns
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
[4]
74AHCT259-Q100; VCC = 4.5 V to 5.5 V
tpd
propagation D to Qn; see Figure 5
delay
CL = 15 pF
[2]
CL = 50 pF
An to Qn; see Figure 6
[2]
CL = 15 pF
CL = 50 pF
LE to Qn; see Figure 7
MR to Qn; see Figure 8
CL = 15 pF
CL = 50 pF
tW
pulse width
74AHC_AHCT259_Q100
Product data sheet
[2]
[3]
-
5.1
9.0
1.0
10.5
1.0
11.5
ns
LE HIGH or LOW;
see Figure 7
5.0
-
-
5.0
-
5.0
-
ns
MR LOW; see Figure 8
5.0
-
-
5.0
-
5.0
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
9 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
Min
Max
tsu
set-up time
D, An to LE; see Figure 9
and Figure 10
4.0
-
-
4.0
-
4.0
-
ns
th
hold time
D, An to LE; see Figure 9
and Figure 10
1.0
-
-
1.0
-
1.0
-
ns
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
-
17
-
-
-
-
-
pF
[4]
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
tpd is the same as tPHL only.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
11. Waveforms
VCC
D input
VM
GND
tPHL
tPLH
VOH
VM
Qn output
VOL
001aah123
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5.
Data input to output propagation delays
74AHC_AHCT259_Q100
Product data sheet
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Rev. 1 — 22 July 2013
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74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
VCC
VM
An input
GND
tPLH
tPHL
VOH
VM
Qn output
VOL
001aah122
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Address input to output propagation delays
VCC
D input
GND
VCC
LE input
VM
GND
tW
tPHL
tPLH
VOH
VM
Qn output
VOL
001aah121
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Enable input to output propagation delays and pulse width
VCC
MR input
VM
GND
tW
tPHL
VOH
VM
Qn output
VOL
001aah124
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
Conditional reset input to output propagation delays
74AHC_AHCT259_Q100
Product data sheet
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Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
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74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
VCC
LE input
VM
GND
tsu
tsu
th
VCC
th
VM
D input
GND
VOH
Qn output
VM
Q=D
Q=D
VOL
001aah125
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Data input to latch enable input set-up and hold times
VCC
An input
VM
ADDRESS STABLE
GND
tsu
th
VCC
LE input
VM
GND
001aah126
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Address input to latch enable input set-up and hold times
Table 9.
Measurement points
Type
Input
Output
VM
VM
74AHC259-Q100
0.5 VCC
0.5 VCC
74AHCT259-Q100
1.5 V
0.5 VCC
74AHC_AHCT259_Q100
Product data sheet
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Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
12 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
VI
negative
pulse
tW
90 %
VM
VM
10 %
GND
tr
tf
tr
VI
positive
pulse
GND
tf
90 %
VM
VM
10 %
tW
VCC
G
VI
VO
DUT
RT
CL
001aah768
Test data is given in Table 10.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 11. Load circuitry for measuring switching times
Table 10.
Test data
Type
Input
Load
Test
VI
tr, tf
CL
74AHC259-Q100
VCC
3.0 ns
15 pF, 50 pF
tPLH, tPHL
74AHCT259-Q100
3.0 V
3.0 ns
15 pF, 50 pF
tPLH, tPHL
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
13 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT109-1 (SO16)
74AHC_AHCT259_Q100
Product data sheet
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Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
14 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 13. Package outline SOT403-1 (TSSOP16)
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
15 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
13. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
MIL
Military
TTL
Transistor-Transistor Logic
14. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT259_Q100 v.1
20130722
Product data sheet
-
-
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
16 of 19
74AHC259-Q100; 74AHCT259-Q100
NXP Semiconductors
8-bit addressable latch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AHC_AHCT259_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
17 of 19
NXP Semiconductors
74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2013
© NXP B.V. 2013. All rights reserved.
18 of 19
NXP Semiconductors
74AHC259-Q100; 74AHCT259-Q100
8-bit addressable latch
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 July 2013
Document identifier: 74AHC_AHCT259_Q100