74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 02 — 12 June 2008 Product data sheet
1. General description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. For versions associated with the 74AHC377; 74AHCT377, refer to the following:
• For the master reset version, see 74AHC273; 74AHCT273 • For the transparent latch version, see 74AHC373; 74AHCT373 • For the 3-state version, see 74AHC374; 74AHCT374
2. Features
I I I I I I I Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Ideal for addressable register applications Data enable for address and data synchronization Eight positive-edge triggered D-type flip-flops Input levels: N For 74AHC377: CMOS level N For 74AHCT377: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74AHC377 74AHC377D 74AHC377PW 74AHCT377 74AHCT377D 74AHCT377PW −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1 −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1 Description Version Type number
4. Functional diagram
3 4 7 8
D0
Q0 Q1 Q2
FF1 to FF8
2 5 6 9
D1 D2 D3
OUTPUTS
Q3
13 D4 14 D5 17 D6 18 D7
Q4 12 Q5 15 Q6 16 Q7 19
1
E
11 CP
mna606
Fig 1.
Functional diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
2 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
11 1 11 3 4 7 8 13 14 17 18 CP D0 D1 D2 D3 D4 D5 D6 D7 E 1
mna918
1C2 G1
3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 17 18 4 7 8 13 14
2D
2 5 6 9 12 15 16 19
mna919
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
E
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
FF1 CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
mna610
Q7
Fig 4.
Logic diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
3 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
E Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 VCC 19 Q7 18 D7 17 D6
377
16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP
mna917
GND 10
Fig 5.
Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2. Symbol E Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND CP Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description data enable input (active LOW) flip-flop output data input data input flip-flop output flip-flop output data input data input flip-flop output ground (0 V) clock input (LOW-to-HIGH, edge triggered) flip-flop output data input data input flip-flop output flip-flop output data input data input flip-flop output supply voltage
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
4 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
6. Functional description
Table 3. Function table[1] Control E Load 1 Load 0 Hold (do nothing) l l h H
[1]
Operating mode
Input CP ↑ ↑ ↑ X Dn h l X X
Output Qn H L no change no change
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ↑ = LOW-to-HIGH CP transition; X = don’t care.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation
Conditions
Min −0.5 −0.5
Max +7.0 +7.0 +20 +25 +75 +150 500
Unit V V mA mA mA mA mA °C mW
VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V)
[1] [1]
−20 −20 −25 −75 −65
Tamb = −40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
5 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
8. Recommended operating conditions
Table 5. 74AHC377 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 74AHCT377 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Conditions Min Typ Max Unit Symbol Parameter
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC377 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V
74AHC_AHCT377_2
Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 -
25 °C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36
−40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 V V V V V V V V V V V V V V V V
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
6 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II ICC CI input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ 3 Max 0.1 4.0 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 40 10 Min Max 2.0 80 10 µA µA pF
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VI = VCC or GND
74AHCT377 VIH VIL VOH VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2.0 0.8 2.0 0.8 2.0 0.8 V V
HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V
4.4 3.94 -
4.5 0 -
0.1 0.36 0.1 4.0 1.35
4.4 3.80 -
0.1 0.44 1.0 40 1.5
4.4 3.70 -
0.1 0.55 2.0 80 1.5
V V V V µA µA mA
VOL
II ICC ∆ICC
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance VI = VCC or GND
CI
-
3
10
-
10
-
10
pF
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
7 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 74AHC377 tpd propagation CP to Qn; see Figure 6 delay VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tW pulse width CP HIGH or LOW; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time Dn, E to CP; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time Dn, E to CP; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance
[3] [2]
Conditions Min
25 °C Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max
-
5.6 8.0 3.9 5.6
12.8 16.0 9.0 10.5
1.0 1.0 1.0 1.0
15.0 18.0 10.5 12.0
1.0 1.0 1.0 1.0
16.0 20.0 11.5 13.5
ns ns ns ns
80 50 125 85
125 75 175 120
-
70 45 110 75
-
70 45 110 75
-
MHz MHz MHz MHz
5.0 5.0 5.0 4.5 1.5 2.0 -
20
-
5.0 5.0 5.0 4.5 1.5 2.0 -
-
5.0 5.0 5.0 4.5 1.5 2.0 -
-
ns ns ns ns ns ns pF
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
8 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min 74AHCT377; VCC = 4.5 V to 5.5 V tpd propagation CP to Qn; see Figure 6 delay CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 6 CL = 15 pF CL = 50 pF tW tsu th CPD pulse width set-up time hold time CP HIGH or LOW; see Figure 6 Dn, E to CP; see Figure 7 Dn, E to CP; see Figure 7
[3] [2]
25 °C Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max
90 85 5.0 4.5 2.0 -
4.0 5.7 140 130 23
9.0 10.5 -
1.0 1.0 80 75 5.0 4.5 2.0 -
10.5 12.0 -
1.0 1.0 80 75 5.0 4.5 2.0 -
11.5 13.5 -
ns ns MHz MHz ns ns ns pF
power fi = 1 MHz; VI = GND to VCC dissipation capacitance
[1] [2] [3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
9 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
11. Waveforms
1/fmax VI CP input GND tW t PHL VOH Qn output VOL VM
001aac426
VM
t PLH
Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Clock pulse width, maximum frequency and input to output propagation delays
VCC E input GND th tsu VCC Dn input GND tsu th VCC CP input GND
mna609
VM
th tsu
VM
tW
VM
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Table 8. Type
Data set-up and hold times Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC
74AHC377 74AHCT377
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
10 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
VI negative pulse GND
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G
VI VO
VM
VI positive pulse GND
VM
DUT
RT CL
001aah768
Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance.
Fig 8. Table 9. Type
Load circuitry for measuring switching times Test data Input VI tr, tf ≤ 3.0 ns ≤ 3.0 ns VCC 3.0 V Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test
74AHC377 74AHCT377
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
11 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
θ
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9.
Package outline SOT163-1 (SO20)
© NXP B.V. 2008. All rights reserved.
74AHC_AHCT377_2
Product data sheet
Rev. 02 — 12 June 2008
12 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
θ Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT360-1 (TSSOP20)
74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
13 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
13. Abbreviations
Table 10. Acronym CDM CMOS DUT ESD HBM LSTTL MM Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model
14. Revision history
Table 11. Revision history Release date 20080612 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT377_1 Document ID 74AHC_AHCT377_2 Modifications:
• • •
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. Product specification -
74AHC_AHCT377_1
20000815
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
14 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
15 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 June 2008 Document identifier: 74AHC_AHCT377_2