74AHC573BQ

74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Rev. 05 — 25 March 2010 Product data sheet 1. General description The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but has a different pin arrangement. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt trigger action Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Inputs accept voltages higher than VCC Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC573 74AHC573D 74AHC573PW 74AHC573BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 DHVQFN20 plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT163-1 SOT360-1 SOT764-1 Name Description Version Type number 74AHCT573 74AHCT573D 74AHCT573PW 74AHCT573BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 DHVQFN20 SOT163-1 SOT360-1 SOT764-1 4. Functional diagram 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 11 LE 1 OE mna809 Fig 1. Functional diagram 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 2 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 11 1 1 2 3 4 5 6 7 8 9 OE D0 D1 D2 D3 D4 D5 D6 D7 LE 11 mna807 C1 EN1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 4 5 6 7 8 9 3 1D 19 18 17 16 15 14 13 12 mna808 Fig 2. Logic symbol Fig 3. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LATCH 1 LE LE LATCH 2 LE LE LATCH 3 LE LE LATCH 4 LE LE LATCH 5 LE LE LATCH 6 LE LE LATCH 7 LE LE LATCH 8 LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig 4. Logic diagram 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 3 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 5. Pinning information 5.1 Pinning 74AHC573 74AHCT573 terminal 1 index area D0 D1 OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE 001aad099 2 3 4 5 6 7 8 9 GND 10 LE 11 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 D2 D3 D4 D5 D6 D7 573 1 OE GND 10 001aal532 Transparent top view Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Symbol OE D0 to D7 GND LE Q0 to Q7 VCC Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 Description output enable input (active LOW) data input ground (0 V) latch enable (active HIGH) data output supply voltage 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 4 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 6. Functional description Table 3. Function table[1] Input OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs L L H LE H L L Dn L H l h l h [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. Operating mode Internal latch L H L H L H Output Qn L H L H Z Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 +20 +25 +75 +150 500 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −20 −25 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 5 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 8. Recommended operating conditions Table 5. Symbol 74AHC573 VCC VI VO Tamb Δt/ΔV 74AHCT573 VCC VI VO Tamb Δt/ΔV supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Parameter Conditions Min Typ Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC573 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 μA; VCC = 2.0 V IO = −50 μA; VCC = 3.0 V IO = −50 μA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 μA; VCC = 2.0 V IO = 50 μA; VCC = 3.0 V IO = 50 μA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V 74AHC_AHCT573_5 Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 - 25 °C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 −40 °C to +85 °C Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 −40 °C to +125 °C Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Typ Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 Unit V V V V V V V V V V V V V V V V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 6 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ Conditions Min OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V input leakage current VI = VCC or GND; VCC = 0 V to 5.5 V 25 °C Typ Max ±0.25 −40 °C to +85 °C Min Max ±2.5 −40 °C to +125 °C Min Typ Max ±10.0 μA Unit II ICC CI CO - 3 4 0.1 4.0 10 - - 1.0 40 10 - - - 2.0 80 10 10 μA μA pF pF supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND 74AHCT573 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 μA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 μA IO = 8.0 mA OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 ±0.25 4.4 3.80 - 0.1 0.44 ±2.5 4.4 3.70 - - 0.1 0.55 V V V V VOL IOZ ±10.0 μA II ICC ΔICC - - 0.1 4.0 1.35 - 1.0 40 1.5 - - 2.0 80 1.5 μA μA mA supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V input capacitance output capacitance VI = VCC or GND CI CO - 3 4 10 - - 10 - - - 10 10 pF pF 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 7 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter 74AHC573 tpd propagation delay Dn to Qn; see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF LE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tW pulse width LE HIGH; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time Dn to LE; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 3.5 3.5 3.5 3.5 3.5 3.5 ns ns 5.0 5.0 5.0 5.0 5.0 5.0 ns ns 4.6 7.4 7.7 9.7 1.0 1.0 9.0 11.0 1.0 1.0 10.0 12.5 ns ns 6.8 9.7 11.0 14.5 1.0 1.0 13.0 16.5 1.0 1.0 14.0 18.5 ns ns [4] [3] [2] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 5.5 7.8 3.9 5.5 11.0 14.5 6.8 8.8 1.0 1.0 1.0 1.0 13.0 16.5 8.0 10.0 1.0 1.0 1.0 1.0 14.0 18.5 8.5 11.0 ns ns ns ns - 5.8 8.3 4.2 5.9 11.9 15.4 7.7 9.7 1.0 1.0 1.0 1.0 14.0 17.5 9.0 11.0 1.0 1.0 1.0 1.0 15.0 19.5 10.0 12.5 ns ns ns ns - 5.8 8.3 4.4 6.3 11.5 15.0 7.7 9.7 1.0 1.0 1.0 1.0 13.5 17.0 9.0 11.0 1.0 1.0 1.0 1.0 14.5 19.0 10.0 12.5 ns ns ns ns 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 8 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter th hold time Conditions Min Dn to LE; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance propagation delay fi = 1 MHz; VI = GND to VCC [5] 25 °C Typ[1] 12 Max - −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 1.5 Max Min 1.5 1.5 Max ns ns pF 1.5 1.5 - 74AHCT573; VCC = 4.5 V to 5.5 V tpd Dn to Qn; see Figure 7 CL = 15 pF CL = 50 pF LE to Qn; see Figure 8 CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 9 CL = 15 pF CL = 50 pF tW tsu th CPD pulse width set-up time hold time power dissipation capacitance LE HIGH; see Figure 8 Dn to LE; see Figure 10 Dn to LE; see Figure 10 fi = 1 MHz; VI = GND to VCC [5] [4] [3] [2] [2] 5.0 3.5 1.5 - 3.5 4.9 3.9 5.5 4.1 5.9 4.5 6.4 18 5.5 7.5 6.0 8.5 6.5 8.5 6.5 9.0 - 1 1 1 1 1 1 1 1 5.0 3.5 1.5 - 6.5 8.5 7.0 9.5 7.5 10.0 7.5 10.0 - 1 1 1 1 1 1 1 1 5.0 3.5 1.5 - 7.0 9.5 7.5 11.0 8.5 11.0 8.5 11.5 - ns ns ns ns ns ns ns ns ns ns ns pF [1] [2] [3] [4] [5] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 9 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 11. Waveforms VI Dn input GND tPHL VOH Qn output VOL VM mna811 VM tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Data input to output propagation delays 1/fmax VI LE input GND tW t PHL VOH Qn output VOL VM mna812 VM t PLH VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Latch enable input to output propagation delays 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 10 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state VI OE input GND t PLZ VCC Qn output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH Qn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna813 VM t PZL VM VX t PZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times VI Dn input GND th t su VI LE input GND mna814 VM th t su VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 10. Data set-up and hold times Table 8. Type 74AHC573 74AHCT573 Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC VX VOL + 0.3 V VOL + 0.3 V VY VOH − 0.3 V VOH − 0.3 V 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 11 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 11. Test circuitry for switching times Table 9. Type 74AHC573 74AHCT573 Test data Input VI VCC 3.0 V tr, tf ≤ 3.0 ns ≤ 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 12 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 8o o 0 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 13 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 14 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 14. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 15 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 13. Abbreviations Table 10. Acronym CDM CMOS ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20100325 20100303 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74AHC_AHCT573_4 74AHC_AHCT573_3 Document ID 74AHC_AHCT573_5 74AHC_AHCT573_4 Modifications: 74AHC_AHCT573_3 74AHC_AHCT573_2 74AHC_AHCT573_1 • Added type numbers 74AHC573BQ and 74AHCT573BQ (DHVQFN20 / SOT764-1 package). Product data sheet Product specification Product specification 74AHC_AHCT573_2 74AHC_AHCT573_1 - 20080424 20031208 19990927 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 16 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74AHC_AHCT573_5 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 17 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT573_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 18 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 March 2010 Document identifier: 74AHC_AHCT573_5