74AHCT164PW

74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register Rev. 03 — 24 April 2008 Product data sheet 1. General description The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW-level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. 2. Features I I I I Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: N For 74AHC164: CMOS level N For 74AHCT164: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AHC164 74AHC164D 74AHC164PW 74AHC164BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO14 TSSOP14 DHVQFN14 plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT402-1 Description Version Type number plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT402-1 74AHCT164 74AHCT164D 74AHCT164PW 74AHCT164BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO14 TSSOP14 DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 4. Functional diagram DSA DSB CP MR 1 2 8 9 3 4 5 6 10 11 12 13 8-BIT SERIAL−IN/PARALLEL−OUT SHIFT REGISTER Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac425 Fig 1. Functional diagram 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 2 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register SRG8 8 9 1 2 C1/ R 3 4 & 1D DSA DSB 3 1 2 4 5 6 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac424 5 6 10 11 12 13 CP MR 8 9 11 12 13 001aac423 Fig 2. Logic symbol Fig 3. IEC logic symbol DSA D DSB Q D Q D Q D Q D Q D Q D Q D Q CP FF1 RD CP FF2 RD CP FF3 RD CP FF4 RD CP FF5 RD CP FF6 RD CP FF7 RD CP FF8 RD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac616 Fig 4. Logic diagram 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 3 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 5. Pinning information 5.1 Pinning DSA 2 3 4 5 6 7 GND CP 8 1 14 VCC 13 Q7 12 Q6 11 Q5 10 Q4 9 MR DSA DSB Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 001aac422 14 VCC 13 Q7 12 Q6 terminal 1 index area DSB Q0 Q1 Q2 Q3 164 11 Q5 10 Q4 9 8 MR CP 164 GND(1) 001aac828 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14 5.2 Pin description Table 2. Symbol DSA DSB Q0 Q1 Q2 Q3 GND CP MR Q4 Q5 Q6 Q7 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description serial data input A serial data input B output 0 output 1 output 2 output 3 ground (0 V) clock input (LOW-to-HIGH edge-triggered) master reset input (active LOW) output 4 output 5 output 6 output 7 supply voltage 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 4 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 6. Functional description Table 3. Function table[1] Control MR Reset (clear) Shift L H CP X ↑ Input DSA X l l h h [1] Operating mode Output DSB X l h l h Q0 L L L L H Q1 to Q7 L to L q0 to q6 q0 to q6 q0 to q6 q0 to q6 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ↑ = LOW-to-HIGH transition; X = don’t care; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 +20 +25 +75 +150 500 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −20 −25 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 5 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 8. Recommended operating conditions Table 5. Symbol 74AHC164 VCC VI VO Tamb ∆t/∆V 74AHCT164 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Parameter Conditions Min Typ Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC164 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V 74AHC_AHCT164_3 Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 - 25 °C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 V V V V V V V V V V V V V V V V © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 6 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II ICC CI input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ 3 Max 0.1 4.0 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 40 Min Max 2.0 80 µA µA pF supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 74AHCT164 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 0.1 4.0 1.35 4.4 3.80 - 0.1 0.44 1.0 40 1.5 4.4 3.70 - 0.1 0.55 2.0 80 1.5 V V V V µA µA mA VOL II ICC ∆ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V input capacitance CI - 3 10 - - - - pF 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 7 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 74AHC164 tpd propagation CP to Qn; see Figure 7 delay VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF MR to Qn; see Figure 8 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tW pulse width CP HIGH or LOW; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tWL pulse width LOW MR; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time DSA, DSB to CP; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time DSA, DSB to CP; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 2.0 1.5 2.0 1.5 2.0 ns ns 5.0 4.5 6.0 4.5 6.0 4.5 ns ns 5.0 5.0 5.0 5.0 5.0 5.0 ns ns 5.0 5.0 5.0 5.0 5.0 5.0 ns ns 125 85 175 115 105 75 85 65 MHz MHz 80 50 125 75 65 45 50 35 MHz MHz 4.0 5.8 8.6 10.6 1.0 1.0 10.0 12.0 1.0 1.0 11.0 13.5 ns ns 5.3 7.6 12.8 16.3 1.0 1.0 15.0 18.5 1.0 1.0 16.0 20.5 ns ns [3] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 6.5 9.3 4.5 6.4 12.8 16.3 9.0 11.0 1.0 1.0 1.0 1.0 15.0 18.5 10.5 12.5 1.0 1.0 1.0 1.0 16.0 20.5 11.5 14.0 ns ns ns ns 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 8 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter trec recovery time Conditions Min MR to CP; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD fi = 1 MHz; VI = GND to VCC power dissipation capacitance propagation CP to Qn; see Figure 7 delay CL = 15 pF CL = 50 pF MR to Qn; see Figure 8 CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 7 CL = 15 pF CL = 50 pF tW tWL tsu th trec CPD pulse width pulse width LOW set-up time hold time recovery time CP HIGH or LOW; see Figure 7 MR; see Figure 8 DSA, DSB to CP; see Figure 9 DSA, DSB to CP; see Figure 9 MR to CP; see Figure 8 [4] [3] [4] 25 °C Typ[1] 48 Max - −40 °C to +85 °C −40 °C to +125 °C Unit Min 2.5 2.5 Max Min 2.5 2.5 Max ns ns pF 2.5 2.5 - 74AHCT164; VCC = 4.5 V to 5.5 V tpd [2] 125 85 5.0 5.0 4.5 2.0 2.5 - 3.4 4.9 3.5 5.0 175 115 51 9.0 11.0 8.6 10.6 - 1.0 1.0 1.0 1.0 105 75 5.0 5.0 4.5 2.0 2.5 - 10.5 12.5 10.0 12.0 - 1.0 1.0 1.0 1.0 85 65 5.0 5.0 4.5 2.0 2.5 - 11.5 14.0 11.0 13.5 - ns ns ns ns MHz MHz ns ns ns ns ns pF power fi = 1 MHz; VI = GND to VCC dissipation capacitance [1] [2] [3] [4] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. tpd is the same as tPHL only. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 9 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 11. Waveforms 1/fmax VI CP input GND tW t PHL VOH Qn output VOL VM 001aac426 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock pulse width, maximum frequency and input to output propagation delays VI MR input GND t WL VI CP input GND t PHL VOH Qn output VOL 001aac446 VM t rec VM VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Master reset pulse width, recovery time and propagation delays 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 10 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register VI CP input GND t su th VI DSA, DSB input GND VM t su th VM VOH Qn output VOL 001aaf612 VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Table 8. Type Data set-up and hold times Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC 74AHC164 74AHCT164 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 11 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance Fig 10. Load circuitry for measuring switching times Table 9. Type 74AHC164 74AHCT164 Test data Input VI VCC 3.0 V tr, tf ≤ 3.0 ns ≤ 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 12 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT108-1 (SO14) 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 13 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 12. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 14 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 15 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 13. Abbreviations Table 10. Acronym CDM CMOS ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080424 Data sheet status Product data sheet Product data sheet Product specification Change notice Supersedes 74AHC_AHCT164_2 74AHC_AHCT164_1 Document ID 74AHC_AHCT164_3 Modifications: 74AHC_AHCT164_2 74AHC_AHCT164_1 (9397 750 07332) • Table 6: the conditions for input leakage current have been changed. 20061129 20000815 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 16 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 April 2008 17 of 18 NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 April 2008 Document identifier: 74AHC_AHCT164_3