74AHCT240D

74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state Rev. 2 — 26 November 2010 Product data sheet 1. General description The 74AHC240 and 74AHCT240 are 8-bit inverting buffer/line drivers with 3-state outputs. These devices can be used as two 4-bit buffers or one 8-bit buffer. They feature two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are over voltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits       Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC For 74AHC240 only: operates with CMOS input levels For 74AHCT240 only: operates with TTL input levels ESD protection:  HBM JESD22-A114F exceeds 2000 V  CDM JESD22-C101D exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC240D 74AHCT240D 74AHC240PW 74AHCT240PW 74AHC240BQ 74AHCT240BQ 40 C to +125 C DHVQFN20 40 C to +125 C TSSOP20 40 C to +125 C Name SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Type number plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package; no leads; 20 terminals; body 2.5  4.5  0.85 mm NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 4. Functional diagram 1 EN 18 16 14 12 2 2 17 4 15 6 13 8 11 1 19 1A0 2A0 1A1 2A1 1A2 2A2 1A3 2A3 1OE 2OE mgu779 1Y0 18 2Y0 3 1Y1 16 2Y1 5 4 6 8 19 1Y2 14 2Y2 7 11 13 15 17 EN 9 7 5 3 mgu778 1Y3 12 2Y3 9 Fig 1. Logic symbol Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning 74AHC240 74AHCT240 1OE 2 3 4 5 6 7 8 9 GND 10 2A3 11 GND(1) 1 terminal 1 index area 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 74AHC240 74AHCT240 1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 1 2 3 4 5 6 7 8 9 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 11 2A3 001aal192 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 GND 10 001aal193 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. 74AHC_AHCT240 Pin configuration SO20 and TSSOP20 Fig 4. Pin configuration DHVQFN20 © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 26 November 2010 2 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 5.2 Pin description Table 2. Symbol 1OE 2OE Pin description Pin 1 19 Description output enable input (active LOW) output enable input (active LOW) data input data input data output data output ground (0 V) power supply 1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 2A0, 2A1, 2A2, 2A3 17, 15, 13, 11 1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12 2Y0, 2Y1, 2Y2, 2Y3 3, 5, 7, 9 GND VCC 10 20 6. Functional description Table 3. Control nOE L L H [1] Function table[1] Input nAn L H X Output nYn H L Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min 0.5 0.5 Max +7.0 +7.0 20 25 75 +150 500 Unit V V mA mA mA mA mA C mW VI < 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V) [1] [1] 20 75 65 Tamb = 40 C to +125 C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO20 package: above 70 C the value of Ptot derates linearly with 8.0 mW/K. For TSSOP20 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 package: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 3 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 8. Recommended operating conditions Table 5. Symbol 74AHC240 VCC VI VO Tamb t/V 74AHCT240 VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 5 V  0.5 V 4.5 0 0 40 5.0 +25 5.5 5.5 VCC +125 20 V V V C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V  0.3 V VCC = 5 V  0.5 V 2.0 0 0 40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V C ns/V ns/V Recommended operating conditions Parameter Conditions Min Typ Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC240 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V 74AHC_AHCT240 Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 - 25 C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 40 C to +85 C 40 C to +125 C Unit Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 V V V V V V V V V V V V V V V V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 4 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOZ input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 C Typ Max 0.1 0.25 40 C to +85 C 40 C to +125 C Unit Min Max 1.0 2.5 Min Max 2.0 10.0 A A OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND ICC CI CO - 3 4 4.0 10 - - 40 10 - - 80 10 - A pF pF 74AHCT240 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 0.1 0.25 4.4 3.80 - 0.1 0.44 1.0 2.5 4.4 3.70 - 0.1 0.55 2.0 10.0 V V V V A A VOL II IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC  2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance output capacitance VI = VCC or GND ICC ICC - - 4.0 1.35 - 40 1.5 - 80 1.5 A mA CI CO - 3 4 10 - - 10 - - 10 - pF pF 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 5 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions Min 74AHC240 tpd propagation delay nAn to nYn; see Figure 5 VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V; CL = 50 pF VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF ten enable time nOE to nYn; see Figure 6 VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V; CL = 50 pF VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF tdis disable time nOE to nYn; see Figure 6 VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V; CL = 50 pF VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF CPD power dissipation capacitance VI = GND to VCC; CL = 50 pF; fi = 1 MHz [3] [2] [2] [2] 25 C Typ[1] Max 40 C to +125 C Min Max (85 C) Max (125 C) Unit - 3.9 5.8 2.8 4.2 4.4 5.8 3.1 4.1 5.3 8.9 3.9 6.2 9 7.5 11.0 4.8 7.3 10.0 13.5 6.5 8.5 9.0 13.0 5.8 8.7 - 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 - 8.6 12.5 5.7 8.5 12.0 15.5 7.7 10.0 10.0 14.5 6.5 9.5 - 10.8 15.6 7.1 10.6 19.4 19.4 12.5 12.5 18.1 18.1 8.1 11.8 - ns ns ns ns ns ns ns ns ns ns ns ns pF 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 6 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions Min 74AHCT240 tpd propagation delay nAn to nYn; see Figure 5 VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF ten enable time nOE to nYn; see Figure 6 VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF tdis disable time nOE to nYn; see Figure 6 VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF CPD power dissipation capacitance VI = GND to VCC; CL = 50 pF; fi = 1 MHz [3] [2] [2] [2] 25 C Typ[1] Max 40 C to +125 C Min Max (85 C) Max (125 C) Unit - 3.0 4.4 3.4 4.5 3.9 6.2 9 5.8 8.4 7.5 9.5 6.1 8.7 - 1.0 1.0 1.0 1.0 1.0 1.0 - 6.8 9.5 9.0 11.5 6.7 9.2 - 8.5 11.9 14.4 14.4 8.3 11.5 - ns ns ns ns ns ns pF [1] [2] [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms VI nAn input GND tPHL VOH nYn output VOL mgu781 VM VM tPLH VM VM Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (nAn) to output (nYn) 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 7 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state VI nOE input GND tPLZ VCC nYn output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH nYn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mgu782 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Table 8. Type Enable and disable times Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC VX VOL + 0.3 V VOL + 0.3 V VY VOH  0.3 V VOH  0.3 V 74AHC240 74AHCT240 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 8 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Table 9. Type Load circuitry for switching times Test data Input VI tr, tf 3.0 ns 3.0 ns VCC 3.0 V Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC240 74AHCT240 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 9 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 8o o 0 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT163-1 (SO20) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. 74AHC_AHCT240 Product data sheet Rev. 2 — 26 November 2010 10 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT360-1 (TSSOP20) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. 74AHC_AHCT240 Product data sheet Rev. 2 — 26 November 2010 11 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 12 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM TTL Abbreviations Description Charge Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date Data sheet status Product data sheet Product data sheet Change notice Supersedes 74AHC_AHCT240 v.1 Document ID Modifications: 74AHC_AHCT240 v.2 20101126 • Figure note [1] of Figure 4: changed. 74AHC_AHCT240 v.1 20100111 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 13 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 14 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 15 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 November 2010 Document identifier: 74AHC_AHCT240