74AHCT373D,118

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74AHC373; 74AHCT373 Octal D-type transparant latch; 3-state Rev. 03 — 20 May 2008 Product data sheet 1. General description The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, but has a different pin arrangement. 2. Features n n n n n n Balanced propagation delays All inputs have a Schmitt-trigger action Common 3-state output enable input Inputs accepts voltages higher than VCC Functionally identical to the 74AHC573; 74AHCT573 Input levels: u For 74AHC373: CMOS input level u For 74AHCT373: TTL input level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC373D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHC373PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHCT373D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHCT373PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHC373 74AHCT373 4. Functional diagram 3 4 7 8 13 14 17 18 11 1 D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 TO 8 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 LE OE 001aae050 Fig 1. Functional diagram 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 2 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 1 OE LE EN 11 C1 11 3 4 7 8 13 14 17 18 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 6 D4 15 D5 16 D6 19 D7 1 Q 8 9 13 12 14 15 17 16 18 19 D2 D Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae049 Fig 3. D1 D 6 001aae048 Logic symbol D0 5 D3 12 Q0 7 D2 9 2 1D 4 D1 5 OE Fig 2. 3 D0 LE Q D3 D Q IEC logic symbol D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig 4. Logic diagram LE LE LE D Q LE Fig 5. 001aae051 Logic diagram (one latch) 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 3 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 5. Pinning information 5.1 Pinning 74AHC373 74AHCT373 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE 001aai132 Fig 6. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) Q0 2 3-state latch output D0 3 data input D1 4 data input Q1 5 3-state latch output Q2 6 3-state latch output D2 7 data input D3 8 data input Q3 9 3-state latch output GND 10 ground (0 V) LE 11 latch enable input (active HIGH) Q4 12 3-state latch output D4 13 data input D5 14 data input Q5 15 3-state latch output Q6 16 3-state latch output D6 17 data input 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 4 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state Table 2. Pin description …continued Symbol Pin Description D7 18 data input Q7 19 3-state latch output VCC 20 supply voltage 6. Functional description Table 3. Function table[1] Operating mode Enable and read register (transparent mode) Control Input OE LE Dn Internal latch L H L L L H H H l L L h H H X X Z X X Z Latch and read register L L Latch register and disable outputs H X [1] Output Q0 to Q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V −20 - mA −20 +20 mA input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] VO = −0.5 V to (VCC + 0.5 V) IIK IO output current −25 +25 mA ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 5 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit V 74AHC373 VCC supply voltage 2.0 5.0 5.5 VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT373 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC373 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 6 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V - - ±0.2 5 - ±2.5 - ±10.0 µA II input leakage current VI = VCC or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - 10 pF VI = VCC or GND 74AHCT373 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - ±0.2 5 - ±2.5 - ±10.0 µA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 µA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - 10 pF VI = VCC or GND 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 7 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 6.0 11.4 1.0 13.5 1.0 14.5 ns CL = 50 pF - 7.8 14.9 1.0 17.0 1.0 19.0 ns - 4.0 7.2 1.0 8.5 1.0 9.0 ns - 5.3 9.2 1.0 10.5 1.0 11.5 ns CL = 15 pF - 6.3 11.0 1.0 13.0 1.0 14.0 ns CL = 50 pF - 8.3 14.5 1.0 16.5 1.0 18.5 ns - 4.3 7.2 1.0 8.5 1.0 9.0 ns - 5.6 9.7 1.0 11.1 1.0 12.5 ns CL = 15 pF - 5.6 11.4 1.0 13.5 1.0 14.5 ns CL = 50 pF - 7.5 14.9 1.0 17.0 1.0 19.0 ns CL = 15 pF - 3.8 8.1 1.0 9.5 1.0 10.5 ns CL = 50 pF - 5.2 10.1 1.0 11.5 1.0 13.0 ns CL = 15 pF - 5.6 10.0 1.0 12.0 1.0 13.0 ns CL = 50 pF - 9.2 13.3 1.0 15.0 1.0 17.0 ns CL = 15 pF - 4.3 7.2 1.0 8.5 1.0 9.5 ns CL = 50 pF - 6.4 9.2 1.0 10.5 1.0 11.5 ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 - - 4.0 - 4.0 - ns VCC = 4.5 V to 5.5 V 4.0 - - 4.0 - 4.0 - ns 74AHC373 tpd propagation delay Dn to Qn; see Figure 7 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF LE to Qn; see Figure 8 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 [3] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tdis disable time OE to Qn; see Figure 9 [4] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW tsu pulse width set-up time LE HIGH or LOW; see Figure 8 Dn to LE; see Figure 10 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 8 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter th CPD hold time power dissipation capacitance 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns - 10 - - - - - pF CL = 15 pF - 4.0 8.5 1.0 9.5 1.0 11.0 ns CL = 50 pF - 5.2 9.5 1.0 10.5 1.0 12.0 ns - 4.3 12.3 1.0 13.5 1.0 15.5 ns - 5.5 13.3 1.0 14.5 1.0 17.0 ns - 4.0 10.9 1.0 12.5 1.0 14.0 ns - 5.2 11.9 1.0 13.5 1.0 15.0 ns CL = 15 pF - 4.4 10.2 1.0 11.0 1.0 13.0 ns CL = 50 pF - 6.5 11.2 1.0 12.0 1.0 14.0 ns 6.5 - - 6.5 - 6.5 - ns 3.5 - - 3.5 - 3.5 - ns Dn to LE; see Figure 10 fi = 1 MHz; VI = GND to VCC [5] 74AHCT373; VCC = 4.5 V to 5.5 V tpd propagation delay Dn to Qn; see Figure 7 [4] LE to Qn; see Figure 8 CL = 15 pF [4] CL = 50 pF ten enable time OE to Qn; see Figure 9 CL = 15 pF CL = 50 pF tdis disable time [4] OE to Qn; see Figure 9 tW pulse width LE HIGH; see Figure 8 tsu set-up time Dn to LE; see Figure 10 th hold time Dn to LE; see Figure 10 CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [4] [5] 1.5 - - 1.5 - 1.5 - ns - 12 - - - - - pF [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPHL and tPLH. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 9 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 11. Waveforms VI VM Dn input GND tPLH tPHL VOH VM Qn output mna811 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Data input to output propagation delays 1/fmax VI LE input VM GND tW t PHL t PLH VOH VM Qn output mna812 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Latch enable pulse width and input to output propagation delays 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 10 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state VI OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna813 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times VI VM Dn input GND th th t su t su VI LE input VM GND mna814 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 10. Data set-up and hold times Table 8. Measurement points Type Input Output VM VM VX VY 74AHC373 0.5 × VCC 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74AHCT373 1.5 V 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 11 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 11. Test circuitry for switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC373 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT373 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 12 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 13 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 14 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT373_3 20080520 Product data sheet - 74AHC_AHCT373_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 6: conditions for the input leakage current have been changed. 74AHC_AHCT373_2 19991123 Product specification - 74AHC_AHCT373_1 74AHC_AHCT373_1 19981211 Product specification - - 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 15 of 17 74AHC373; 74AHCT373 NXP Semiconductors Octal D-type transparant latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT373_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 20 May 2008 16 of 17 NXP Semiconductors 74AHC373; 74AHCT373 Octal D-type transparant latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 May 2008 Document identifier: 74AHC_AHCT373_3