74AHCU04D

74AHCU04 Hex inverter Rev. 03 — 14 November 2007 Product data sheet 1. General description The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHCU04 is a general purpose hex inverter. Each of the six inverters is a single stage. 2. Features s s s s Low power dissipation Balanced propagation delays Inputs accepts voltages higher than VCC ESD protection: x HBM JESD22-A114E: exceeds 2000 V x MM JESD22-A115-A: exceeds 200 V x CDM JESD22-C101C: exceeds 1000 V s Multiple package options s Specified from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74AHCU04D 74AHCU04PW 74AHCU04BQ Name Description Version Type number −40 °C to +125 °C SO14 −40 °C to +125 °C TSSOP14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 SOT762-1 −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 74AHCU04 Hex inverter 4. Functional diagram 1 1 2 1 1A 1Y 2 3 1 4 3 2A 2Y 4 5 1 6 5 3A 3Y 6 9 1 8 9 4A 4Y 8 11 5A 5Y 10 11 1 10 13 6A 6Y 12 13 1 mna343 12 A Y mna045 mna342 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one inverter) 5. Pinning information 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 7 GND 4Y 8 4A terminal 1 index area 1Y 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 001aac441 2 3 4 5 6 14 VCC 13 6A 12 6Y 2A 2Y 3A 3Y 04 11 5A 10 5Y 9 8 4A 4Y GND(1) 1 1A 04 001aac442 Transparent top view (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.1 Pin description Table 2. Symbol 1A 1Y 2A 2Y 74AHCU04_3 Pin description Pin 1 2 3 4 Description data input data output data input data output © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 2 of 14 NXP Semiconductors 74AHCU04 Hex inverter Table 2. Symbol 3A 3Y GND 4Y 4A 5Y 5A 6Y 6A VCC Pin description …continued Pin 5 6 7 8 9 10 11 12 13 14 Description data input data output ground (0 V) data output data input data output data input data output data input supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level Input nA L H Output nY H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC IIK VI IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output current supply current ground current storage temperature total power dissipation Conditions VI < −0.5 V [1] Min −0.5 −20 −0.5 −75 −65 Max +7.0 +7.0 ±20 ±25 75 +150 500 Unit V mA V mA mA mA mA °C mW VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 3 of 14 NXP Semiconductors 74AHCU04 Hex inverter 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Conditions Min 2.0 0 0 −40 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 Unit V V V °C ns/V ns/V 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions Min VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.7 2.4 4.4 1.8 2.7 4.0 2.58 3.94 25 °C Typ 2.0 3.0 4.5 0 0 0 3 Max 0.3 0.6 1.1 0.2 0.3 0.5 0.36 0.36 0.1 2.0 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.7 2.4 4.4 1.8 2.7 4.0 2.48 3.8 Max 0.3 0.6 1.1 0.2 0.3 0.5 0.44 0.44 1.0 20 10 Min 1.7 2.4 4.4 1.8 2.7 4.0 2.4 3.7 Max 0.3 0.6 1.1 0.2 0.3 0.5 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V V V V µA µA pF supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 4 of 14 NXP Semiconductors 74AHCU04 Hex inverter 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol tpd Parameter propagation delay Conditions Min nA to nY; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] [3] [1] [2] 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 3.0 3.4 2.4 3.5 9.1 7.1 10.6 5.5 7.0 - 1.0 1.0 1.0 1.0 - 8.5 12.0 6.5 8.0 - 1.0 1.0 1.0 1.0 - 9.0 13.5 7.0 9.0 - ns ns ns ns pF [1] [2] [3] [4] tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 11. Waveforms VI nA input GND t PHL VOH nY output VOL VM VM mna344 VM VM VCC t PLH PULSE GENERATOR VI VO DUT RT CL 50 pF mna034 VM = 0.5 × VCC; VI = GND to VCC. Test data is given in Table 7. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. The input (nA) to output (nY) propagation delay times 74AHCU04_3 Fig 7. Load circuit for switching times © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 5 of 14 NXP Semiconductors 74AHCU04 Hex inverter 12. Typical transfer characteristics mna352 2 VO (V) 1.5 VO mna353 700 ICC (µA) 500 4 VO (V) VO 3 6 ICC (mA) 4 ICC 1 300 2 ICC 2 0.5 100 0 1 0 0 0 0.5 1 1.5 V (V) i 2 −100 0 0 1 2 Vi (V) 3 −2 Tamb = 25 °C. Tamb = 25 °C. Fig 8. VCC = 2.0 V; IO = 0 A Fig 9. VCC = 3.0 V; IO = 0 A 8 VO (V) 6 mna351 30 ICC (mA) 20 4 10 Rbias = 560 kΩ VCC ICC 2 VO VI (f = 1 kHz) 0 0.47 µF input output 100 µF 0 0 2 4 Vi (V) 6 −10 A IO GND mna050 Tamb = 25 °C. ∆I o g fs = -------∆V i fi = 1 kHz at VO is constant Fig 10. VCC = 5.5 V; IO = 0 A Fig 11. Test set-up for measuring forward transconductance 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 6 of 14 NXP Semiconductors 74AHCU04 Hex inverter 40 g fs (mA/V) 30 mna355 20 10 0 0 2 4 VCC (V) 6 Tamb = 25 °C. Fig 12. Typical forward transconductance as a function of the supply voltage 13. Application information Some applications are: • Linear amplifier (see Figure 13) • In crystal oscillator design (see Figure 14) Remark: All values given are typical unless otherwise specified. R2 R1 VCC 1 µF R1 R2 U04 ZL U04 C1 C2 out mna052 mna053 Maximum Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. C1 = 47 pF (typical) C2 = 33 pF (typical) R1 = 1 MΩ to 10 MΩ (typical R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 5 mA at VCC = 5 V and fi = 10 MHz). G ol G v = – --------------------------------------R1 1 + ------ ( 1 + G ol ) R2 Gol = open loop gain Gv = voltage gain R1 ≥ 3 kΩ, R2 ≤ 1 MΩ ZL > 10 kΩ; Gol = 12 (typical) Typical unity gain bandwidth product is 5 MHz. Fig 13. Used as a linear amplifier 74AHCU04_3 Fig 14. Crystal oscillator configuration © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 7 of 14 NXP Semiconductors 74AHCU04 Hex inverter Table 8. External components for resonator (f < 1 MHz) All values given are typical and must be used as an initial set-up. Frequency 10 kHz to 15.9 kHz 16 kHz to 24.9 kHz 25 kHz to 54.9 kHz 55 kHz to 129.9 kHz 130 kHz to 199.9 kHz 200 kHz to 349.9 kHz 350 kHz to 600 kHz Table 9. Frequency 3 kHz 6 kHz 10 kHz 14 kHz >14 kHz Optimum value for R2 R2 2.0 kΩ 8.0 kΩ 1.0 kΩ 4.7 kΩ 0.5 kΩ 2.0 kΩ 0.5 kΩ 1.0 kΩ Optimum for minimum required ICC minimum influence due to change in VCC minimum required ICC minimum influence by VCC minimum required ICC minimum influence by VCC minimum required ICC minimum influence by VCC replace R2 by C3 with a typical value of 35 pF R1 22 MΩ 22 MΩ 22 MΩ 22 MΩ 22 MΩ 10 MΩ 10 MΩ R2 220 kΩ 220 kΩ 100 kΩ 100 kΩ 47 kΩ 47 kΩ 47 kΩ C1 56 pF 56 pF 56 pF 47 pF 47 pF 47 pF 47 pF C2 20 pF 10 pF 10 pF 5 pF 5 pF 5 pF 5 pF 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 8 of 14 NXP Semiconductors 74AHCU04 Hex inverter 14. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT108-1 (SO14) 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 9 of 14 NXP Semiconductors 74AHCU04 Hex inverter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 16. Package outline SOT402-1 (TSSOP14) 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 10 of 14 NXP Semiconductors 74AHCU04 Hex inverter DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT762-1 (DHVQFN14) 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 11 of 14 NXP Semiconductors 74AHCU04 Hex inverter 15. Abbreviations Table 10. Acronym CMOS LSTTL ESD HBM MM CDM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Low-power Schottky Transistor-Transistor Logic ElectroStatic Discharge Human Body Model Machine Model Charge Device Model Transistor-Transistor Logic 16. Revision history Table 11. Revision history Release date 20071114 Data sheet status Product data sheet Change notice Supersedes 74AHCU04_2 Document ID 74AHCU04_3 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 8: derating values added for DHVQFN14 package. Section 14: outline drawing added for DHVQFN14 package. Product specification Product specification 74AHCU04_1 - 74AHCU04_2 74AHCU04_1 19990927 19990226 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 12 of 14 NXP Semiconductors 74AHCU04 Hex inverter 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 13 of 14 NXP Semiconductors 74AHCU04 Hex inverter 19. Contents 1 2 3 4 5 5.1 6 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical transfer characteristics . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 November 2007 Document identifier: 74AHCU04_3