74ALVC125

74ALVC125 Quad buffer/line driver; 3-state Rev. 02 — 10 January 2008 Product data sheet 1. General description The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state. 2. Features s s s s s s s Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A 115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74ALVC125D −40 °C to +85 °C SO14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 SOT762-1 Type number 74ALVC125PW −40 °C to +85 °C 74ALVC125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 4. Functional diagram 2 1 5 4 9 10 12 13 1A 1OE 2A 2OE 1Y 3 2 1 3 2Y 6 1 5 EN1 6 4 3A 3OE 4A 4OE mna228 3Y 8 9 8 10 4Y 11 12 11 13 mna229 Fig 1. Logic symbol Fig 2. IEC logic symbol nA nY nOE mna227 Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning 74ALVC125 1OE 2 3 4 5 6 7 GND 3Y 8 GND(1) 1 terminal 1 index area 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 74ALVC125 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 001aah089 1A 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 8 3A 3Y 2Y 1Y 2OE 2A 001aah090 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 74ALVC125_2 Fig 5. Pin configuration DHVQFN14 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 2 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 5.2 Pin description Table 2. Symbol nA nY nOE VCC GND Pin description Pin 2, 5, 9, 12 3, 6, 8, 11 1, 4, 10, 13 14 7 Description data input bus output output enable (active LOW) supply voltage ground (0 V) 6. Functional description Table 3. Input nOE L L H [1] H = HIGH voltage level L = LOW voltage level X= don’t care Z = high-impedance OFF-state Function table[1] Output nA L H X nY L H Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO Parameter supply voltage input clamping current input voltage output clamping current output voltage VO > VCC or VO < 0 V output HIGH or LOW state output 3-state Power-down mode, VCC = 0 V IO ICC IGND Tstg Ptot [1] [2] [3] [2] [1][2] Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −0.5 −0.5 −0.5 −100 −65 Max +4.6 +4.6 ±50 VCC + 0.5 +4.6 +4.6 ±50 100 +150 500 Unit V mA V mA V V V mA mA mA °C mW output current supply current ground current storage temperature total power dissipation VO = 0 V to VCC Tamb = −40 °C to +85 °C [3] - The minimum input voltage ratings may be exceeded if the input current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. © NXP B.V. 2008. All rights reserved. 74ALVC125_2 Product data sheet Rev. 02 — 10 January 2008 3 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage output HIGH or LOW state output 3-state Power-down mode; VCC = 0 V Tamb ∆t/∆V ambient temperature input transition rise and fall rate in free air VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V Conditions Min 1.65 0 0 0 0 −40 0 0 Max 3.6 3.6 VCC 3.6 3.6 +85 20 10 Unit V V V V V °C ns/V ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions Min VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −6 mA; VCC = 1.65 V IO = −12 mA; VCC = 2.3 V IO = −18 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 6 mA; VCC = 1.65 V IO = 12 mA; VCC = 2.3 V IO = 18 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 18 mA; VCC = 3.0 V IO = 24 mA; VCC = 3.0 V II input leakage current VCC = 3.6 V; VI = 3.6 V or GND 0.11 0.17 0.25 0.16 0.23 0.30 ±0.1 0.2 0.3 0.4 0.6 0.4 0.4 0.55 ±5 V V V V V V V µA VCC − 0.2 1.25 1.8 1.7 2.2 2.4 2.2 1.51 2.10 2.01 2.53 2.76 2.68 V V V V V V V 0.65 × VCC 1.7 2.0 −40 °C to +85 °C Typ[1] Max 0.7 0.8 V V V V V Unit 0.35 × VCC V 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 4 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ IOFF ICC ∆ICC CI [1] Conditions Min VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND; VCC = 0 V; VI or VO = 0 V to 3.6 V VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 3.0 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - −40 °C to +85 °C Typ[1] ±0.1 ±0.1 0.2 5 3.5 Max ±10 ±10 10 750 - Unit µA µA µA µA pF OFF-state output current power-off leakage current supply current additional supply current input capacitance All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol tpd Parameter propagation delay Conditions nA to nY; see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time nOE to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [2] −40 °C to +85 °C Min 1.3 1.0 1.1 1.4 1.0 1.0 1.8 1.0 1.4 Typ[1] 2.4 1.7 2.0 1.8 3.9 2.2 2.7 1.9 3.9 2.1 2.9 2.7 Max 5.3 3.2 3.1 2.8 6.4 4.1 4.3 3.5 5.9 3.4 4.0 4.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 5 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol CPD Parameter power dissipation capacitance Conditions per buffer; VI = GND to VCC; VCC = 3.3 V outputs HIGH or LOW state outputs 3-state [1] [2] Typical values are measured at Tamb = 25 °C tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs [3] −40 °C to +85 °C Min Typ[1] 27 5 Max - Unit pF pF [3] 11. Waveforms VI nA input GND VM tPHL VOH nY output VOL tPLH VM mna230 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 6. Input nA to output nY propagation delay times Table 8. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.15 V VOH − 0.3 V VOH − 0.3 V Supply voltage 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 6 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled mna362 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Enable and disable times VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Test circuitry for switching times Table 9. Test data Input VI 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V VCC VCC 2.7 V 2.7 V tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open tPLZ, tPZL 2 × VCC 2 × VCC 6V 6V tPHZ, tPZH GND GND GND GND Supply voltage 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 7 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 8 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 9 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT762-1 (DHVQFN14) 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 10 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 13. Abbreviations Table 10. Acronym CDM DUT ESD HBM MM TTL Abbreviations Description Charged-Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080110 Data sheet status Product data sheet Change notice Supersedes 74ALVC125_1 Document ID 74ALVC125_2 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package. Section 12: outline drawing added for DHVQFN14 package. Product specification - 74ALVC125_1 20021118 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 11 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 12 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 January 2008 Document identifier: 74ALVC125_2